u32 vcd_device_power_event(struct vcd_dev_ctxt *dev_ctxt, u32 event,
struct vcd_clnt_ctxt *cctxt)
{
u32 rc = VCD_ERR_FAIL;
u32 set_perf_lvl;
switch (event) {
case VCD_EVT_PWR_DEV_INIT_BEGIN:
if (dev_ctxt->pwr_clk_state == VCD_PWRCLK_STATE_OFF &&
res_trk_get_max_perf_level(
&dev_ctxt->max_perf_lvl) &&
res_trk_power_up()) {
dev_ctxt->pwr_clk_state =
VCD_PWRCLK_STATE_ON_NOTCLOCKED;
dev_ctxt->curr_perf_lvl = 0;
dev_ctxt->reqd_perf_lvl = 0;
dev_ctxt->active_clnts = 0;
dev_ctxt->set_perf_lvl_pending = false;
rc = vcd_enable_clock(dev_ctxt, cctxt);
if (VCD_FAILED(rc)) {
res_trk_power_down();
dev_ctxt->pwr_clk_state = VCD_PWRCLK_STATE_OFF;
}
}
break;
case VCD_EVT_PWR_DEV_INIT_END:
case VCD_EVT_PWR_DEV_TERM_FAIL:
case VCD_EVT_PWR_DEV_SLEEP_BEGIN:
case VCD_EVT_PWR_DEV_HWTIMEOUT:
rc = vcd_gate_clock(dev_ctxt);
break;
case VCD_EVT_PWR_DEV_INIT_FAIL:
case VCD_EVT_PWR_DEV_TERM_END:
if (dev_ctxt->pwr_clk_state != VCD_PWRCLK_STATE_OFF) {
vcd_disable_clock(dev_ctxt);
res_trk_power_down();
dev_ctxt->pwr_clk_state = VCD_PWRCLK_STATE_OFF;
dev_ctxt->curr_perf_lvl = 0;
dev_ctxt->reqd_perf_lvl = 0;
dev_ctxt->active_clnts = 0;
dev_ctxt->set_perf_lvl_pending = false;
rc = VCD_S_SUCCESS;
}
break;
case VCD_EVT_PWR_DEV_TERM_BEGIN:
case VCD_EVT_PWR_DEV_SLEEP_END:
rc = vcd_un_gate_clock(dev_ctxt);
break;
case VCD_EVT_PWR_DEV_SET_PERFLVL:
set_perf_lvl = dev_ctxt->reqd_perf_lvl > 0 ?
dev_ctxt->reqd_perf_lvl : VCD_MIN_PERF_LEVEL;
rc = vcd_set_perf_level(dev_ctxt, set_perf_lvl, cctxt);
break;
}
return rc;
}
u32 vcd_device_power_event(struct vcd_dev_ctxt_type *p_dev_ctxt, u32 event,
struct vcd_clnt_ctxt_type_t *p_cctxt)
{
u32 rc = VCD_ERR_FAIL;
u32 n_set_perf_lvl;
switch (event) {
case VCD_EVT_PWR_DEV_INIT_BEGIN:
{
if (p_dev_ctxt->e_pwr_clk_state ==
VCD_PWRCLK_STATE_OFF) {
if (res_trk_get_max_perf_level(&p_dev_ctxt->
n_max_perf_lvl)) {
if (res_trk_power_up()) {
p_dev_ctxt->e_pwr_clk_state =
VCD_PWRCLK_STATE_ON_NOTCLOCKED;
p_dev_ctxt->n_curr_perf_lvl = 0;
p_dev_ctxt->n_reqd_perf_lvl = 0;
p_dev_ctxt->n_active_clnts = 0;
p_dev_ctxt->
b_set_perf_lvl_pending = FALSE;
rc = vcd_enable_clock(p_dev_ctxt,
p_cctxt);
if (VCD_FAILED(rc)) {
(void)res_trk_power_down();
p_dev_ctxt->e_pwr_clk_state =
VCD_PWRCLK_STATE_OFF;
}
}
}
}
break;
}
case VCD_EVT_PWR_DEV_INIT_END:
case VCD_EVT_PWR_DEV_TERM_FAIL:
case VCD_EVT_PWR_DEV_SLEEP_BEGIN:
case VCD_EVT_PWR_DEV_HWTIMEOUT:
{
rc = vcd_gate_clock(p_dev_ctxt);
break;
}
case VCD_EVT_PWR_DEV_INIT_FAIL:
case VCD_EVT_PWR_DEV_TERM_END:
{
if (p_dev_ctxt->e_pwr_clk_state !=
VCD_PWRCLK_STATE_OFF) {
(void)vcd_disable_clock(p_dev_ctxt);
(void)res_trk_power_down();
p_dev_ctxt->e_pwr_clk_state =
VCD_PWRCLK_STATE_OFF;
p_dev_ctxt->n_curr_perf_lvl = 0;
p_dev_ctxt->n_reqd_perf_lvl = 0;
p_dev_ctxt->n_active_clnts = 0;
p_dev_ctxt->b_set_perf_lvl_pending = FALSE;
rc = VCD_S_SUCCESS;
}
break;
}
case VCD_EVT_PWR_DEV_TERM_BEGIN:
case VCD_EVT_PWR_DEV_SLEEP_END:
{
rc = vcd_un_gate_clock(p_dev_ctxt);
break;
}
case VCD_EVT_PWR_DEV_SET_PERFLVL:
{
n_set_perf_lvl =
p_dev_ctxt->n_reqd_perf_lvl >
0 ? p_dev_ctxt->
n_reqd_perf_lvl : VCD_MIN_PERF_LEVEL;
rc = vcd_set_perf_level(p_dev_ctxt, n_set_perf_lvl,
p_cctxt);
break;
}
}
return rc;
}