void ncr5390_device::reset_soft()
{
state = IDLE;
scsi_bus->ctrl_wait(scsi_refid, S_SEL|S_BSY|S_RST, S_ALL);
status &= 0xef;
drq = false;
m_drq_handler(drq);
reset_disconnect();
}
void ncr5390_device::reset_soft()
{
state = IDLE;
scsi_bus->ctrl_wait(scsi_refid, S_SEL|S_BSY|S_RST, S_ALL);
status &= 0xef;
drq = false;
if(!m_drq_func.isnull())
m_drq_func(drq);
reset_disconnect();
}
void ncr5380n_device::reset_soft()
{
state = IDLE;
scsi_bus->ctrl_w(scsi_refid, 0, S_ALL); // clear any signals we're driving
scsi_bus->ctrl_wait(scsi_refid, S_ALL, S_ALL);
status = 0;
drq = false;
m_drq_handler(drq);
reset_disconnect();
}
void ncr5390_device::step(bool timeout)
{
UINT32 ctrl = scsi_bus->ctrl_r();
UINT32 data = scsi_bus->data_r();
UINT8 c = command[0] & 0x7f;
if(0)
logerror("%s: state=%d.%d %s\n",
tag(), state & STATE_MASK, (state & SUB_MASK) >> SUB_SHIFT,
timeout ? "timeout" : "change");
if(mode == MODE_I && !(ctrl & S_BSY)) {
state = IDLE;
istatus |= I_DISCONNECT;
reset_disconnect();
check_irq();
}
switch(state & SUB_MASK ? state & SUB_MASK : state & STATE_MASK) {
case IDLE:
break;
case ARB_COMPLETE << SUB_SHIFT: {
if(!timeout)
break;
int win;
for(win=7; win>=0 && !(data & (1<<win)); win--);
if(win != scsi_id) {
scsi_bus->data_w(scsi_refid, 0);
scsi_bus->ctrl_w(scsi_refid, 0, S_ALL);
fatalerror("need to wait for bus free\n");
break;
}
state = (state & STATE_MASK) | (ARB_ASSERT_SEL << SUB_SHIFT);
scsi_bus->ctrl_w(scsi_refid, S_SEL, S_SEL);
delay(6);
break;
}
case ARB_ASSERT_SEL << SUB_SHIFT:
if(!timeout)
break;
scsi_bus->data_w(scsi_refid, (1<<scsi_id) | (1<<bus_id));
state = (state & STATE_MASK) | (ARB_SET_DEST << SUB_SHIFT);
delay_cycles(4);
break;
case ARB_SET_DEST << SUB_SHIFT:
if(!timeout)
break;
state = (state & STATE_MASK) | (ARB_RELEASE_BUSY << SUB_SHIFT);
scsi_bus->ctrl_w(scsi_refid, c == CD_SELECT_ATN || c == CD_SELECT_ATN_STOP ? S_ATN : 0, S_ATN|S_BSY);
delay(2);
break;
case ARB_RELEASE_BUSY << SUB_SHIFT:
if(!timeout)
break;
if(ctrl & S_BSY) {
state = (state & STATE_MASK) | (ARB_DESKEW_WAIT << SUB_SHIFT);
if(c == CD_RESELECT)
scsi_bus->ctrl_w(scsi_refid, S_BSY, S_BSY);
delay_cycles(2);
} else {
state = (state & STATE_MASK) | (ARB_TIMEOUT_BUSY << SUB_SHIFT);
#ifdef DELAY_HACK
delay(1);
#else
delay(8192*select_timeout);
#endif
}
break;
case ARB_DESKEW_WAIT << SUB_SHIFT:
if(!timeout)
break;
scsi_bus->data_w(scsi_refid, 0);
scsi_bus->ctrl_w(scsi_refid, 0, S_SEL);
if(c == CD_RESELECT) {
logerror("%s: mode switch to Target\n", tag());
mode = MODE_T;
} else {
logerror("%s: mode switch to Initiator\n", tag());
mode = MODE_I;
}
state &= STATE_MASK;
step(true);
break;
case ARB_TIMEOUT_BUSY << SUB_SHIFT:
if(timeout) {
scsi_bus->data_w(scsi_refid, 0);
logerror("%s: select timeout\n", tag());
state = (state & STATE_MASK) | (ARB_TIMEOUT_ABORT << SUB_SHIFT);
delay(1000);
} else if(ctrl & S_BSY) {
state = (state & STATE_MASK) | (ARB_DESKEW_WAIT << SUB_SHIFT);
if(c == CD_RESELECT)
scsi_bus->ctrl_w(scsi_refid, S_BSY, S_BSY);
delay_cycles(2);
}
break;
case ARB_TIMEOUT_ABORT << SUB_SHIFT:
if(!timeout)
break;
if(ctrl & S_BSY) {
state = (state & STATE_MASK) | (ARB_DESKEW_WAIT << SUB_SHIFT);
if(c == CD_RESELECT)
scsi_bus->ctrl_w(scsi_refid, S_BSY, S_BSY);
delay_cycles(2);
} else {
scsi_bus->ctrl_w(scsi_refid, 0, S_ALL);
state = IDLE;
istatus |= I_DISCONNECT;
reset_disconnect();
check_irq();
}
break;
case SEND_WAIT_SETTLE << SUB_SHIFT:
if(!timeout)
break;
state = (state & STATE_MASK) | (SEND_WAIT_REQ_0 << SUB_SHIFT);
step(false);
break;
case SEND_WAIT_REQ_0 << SUB_SHIFT:
if(ctrl & S_REQ)
break;
state = state & STATE_MASK;
scsi_bus->data_w(scsi_refid, 0);
scsi_bus->ctrl_w(scsi_refid, 0, S_ACK);
step(false);
break;
case RECV_WAIT_REQ_1 << SUB_SHIFT:
if(!(ctrl & S_REQ))
break;
state = (state & STATE_MASK) | (RECV_WAIT_SETTLE << SUB_SHIFT);
delay_cycles(sync_period);
break;
case RECV_WAIT_SETTLE << SUB_SHIFT:
if(!timeout)
break;
if((state & STATE_MASK) != INIT_XFR_RECV_PAD)
fifo_push(scsi_bus->data_r());
scsi_bus->ctrl_w(scsi_refid, S_ACK, S_ACK);
state = (state & STATE_MASK) | (RECV_WAIT_REQ_0 << SUB_SHIFT);
step(false);
break;
case RECV_WAIT_REQ_0 << SUB_SHIFT:
if(ctrl & S_REQ)
break;
state = state & STATE_MASK;
step(false);
break;
case DISC_SEL_ARBITRATION:
if(c == CD_SELECT) {
state = DISC_SEL_WAIT_REQ;
command_length = derive_msg_size(fifo[0]);
} else
state = DISC_SEL_ATN_WAIT_REQ;
scsi_bus->ctrl_wait(scsi_refid, S_REQ, S_REQ);
if(ctrl & S_REQ)
step(false);
break;
case DISC_SEL_ATN_WAIT_REQ:
if(!(ctrl & S_REQ))
break;
if((ctrl & S_PHASE_MASK) != S_PHASE_MSG_OUT) {
function_complete();
break;
}
if(c == CD_SELECT_ATN)
scsi_bus->ctrl_w(scsi_refid, 0, S_ATN);
state = DISC_SEL_ATN_SEND_BYTE;
send_byte();
break;
case DISC_SEL_ATN_SEND_BYTE:
if(c == CD_SELECT_ATN_STOP) {
seq = 1;
function_complete();
} else {
command_length = derive_msg_size(fifo[0]);
state = DISC_SEL_WAIT_REQ;
}
break;
case DISC_SEL_WAIT_REQ:
if(!(ctrl & S_REQ))
break;
if((ctrl & S_PHASE_MASK) != S_PHASE_COMMAND) {
if(!command_length)
seq = 4;
scsi_bus->ctrl_wait(scsi_refid, 0, S_REQ);
function_bus_complete();
break;
}
if(seq < 3)
seq = 3;
state = DISC_SEL_SEND_BYTE;
send_byte();
break;
case DISC_SEL_SEND_BYTE:
if(command_length) {
command_length--;
if(!command_length)
seq = 4;
}
state = DISC_SEL_WAIT_REQ;
break;
case INIT_CPT_RECV_BYTE_ACK:
state = INIT_CPT_RECV_WAIT_REQ;
scsi_bus->ctrl_w(scsi_refid, 0, S_ACK);
break;
case INIT_CPT_RECV_WAIT_REQ:
if(!(ctrl & S_REQ))
break;
if((ctrl & S_PHASE_MASK) != S_PHASE_MSG_IN) {
command_pos = 0;
bus_complete();
} else {
state = INIT_CPT_RECV_BYTE_NACK;
recv_byte();
}
break;
case INIT_CPT_RECV_BYTE_NACK:
scsi_bus->ctrl_wait(scsi_refid, 0, S_REQ);
function_complete();
break;
case INIT_MSG_WAIT_REQ:
if((ctrl & (S_REQ|S_BSY)) == S_BSY)
break;
bus_complete();
break;
case INIT_XFR:
switch(xfr_phase) {
case S_PHASE_DATA_OUT:
dma_set(DMA_OUT);
if(tcount == 0 && fifo_pos == 1)
scsi_bus->ctrl_w(scsi_refid, 0, S_ATN);
state = INIT_XFR_SEND_BYTE;
send_byte();
break;
case S_PHASE_DATA_IN:
dma_set(DMA_IN);
state = tcount == fifo_pos+1 ?
INIT_XFR_RECV_BYTE_NACK : INIT_XFR_RECV_BYTE_ACK;
recv_byte();
break;
default:
logerror("%s: xfer on phase %d\n", tag(), scsi_bus->ctrl_r() & S_PHASE_MASK);
function_complete();
break;
}
break;
case INIT_XFR_WAIT_REQ:
if(!(ctrl & S_REQ))
break;
if((ctrl & S_PHASE_MASK) != xfr_phase) {
command_pos = 0;
bus_complete();
} else {
state = INIT_XFR;
step(false);
}
break;
case INIT_XFR_SEND_BYTE:
if(tcount == 0 && fifo_pos == 0)
bus_complete();
else
state = INIT_XFR_WAIT_REQ;
break;
case INIT_XFR_RECV_BYTE_ACK:
state = INIT_XFR_WAIT_REQ;
scsi_bus->ctrl_w(scsi_refid, 0, S_ACK);
break;
case INIT_XFR_RECV_BYTE_NACK:
function_complete();
break;
case INIT_XFR_SEND_PAD_WAIT_REQ:
if(!(ctrl & S_REQ))
break;
if((ctrl & S_PHASE_MASK) != xfr_phase) {
command_pos = 0;
bus_complete();
} else {
state = INIT_XFR_SEND_PAD;
send_byte();
}
break;
case INIT_XFR_SEND_PAD:
tcount--;
if(tcount) {
state = INIT_XFR_SEND_PAD_WAIT_REQ;
step(false);
} else
function_complete();
break;
case INIT_XFR_RECV_PAD_WAIT_REQ:
if(!(ctrl & S_REQ))
break;
if((ctrl & S_PHASE_MASK) != xfr_phase) {
command_pos = 0;
bus_complete();
} else {
state = INIT_XFR_RECV_PAD;
recv_byte();
}
break;
case INIT_XFR_RECV_PAD:
tcount--;
if(tcount) {
state = INIT_XFR_RECV_PAD_WAIT_REQ;
scsi_bus->ctrl_w(scsi_refid, 0, S_ACK);
step(false);
} else
function_complete();
break;
default:
logerror("%s: step() unexpected state %d.%d\n",
tag(),
state & STATE_MASK, (state & SUB_MASK) >> SUB_SHIFT);
exit(0);
}
}
void ncr5380n_device::step(bool timeout)
{
UINT32 ctrl = scsi_bus->ctrl_r();
UINT32 data = scsi_bus->data_r();
if(0)
printf("%s: state=%d.%d %s\n",
tag(), state & STATE_MASK, (state & SUB_MASK) >> SUB_SHIFT,
timeout ? "timeout" : "change");
if(mode == MODE_I && !(ctrl & S_BSY)) {
state = IDLE;
reset_disconnect();
check_irq();
}
switch(state & SUB_MASK ? state & SUB_MASK : state & STATE_MASK) {
case IDLE:
break;
case ARB_COMPLETE << SUB_SHIFT: {
if(!timeout)
break;
int win;
for(win=7; win>=0 && !(data & (1<<win)); win--);
// printf("arb complete: data %02x win %02x scsi_id %02x\n", data, win, scsi_id);
if(win != scsi_id) {
scsi_bus->data_w(scsi_refid, 0);
scsi_bus->ctrl_w(scsi_refid, 0, S_ALL);
fatalerror("need to wait for bus free\n");
break;
}
state &= STATE_MASK;
step(true);
break;
}
case SEND_WAIT_SETTLE << SUB_SHIFT:
if(!timeout)
break;
state = (state & STATE_MASK) | (SEND_WAIT_REQ_0 << SUB_SHIFT);
step(false);
break;
case SEND_WAIT_REQ_0 << SUB_SHIFT:
if(ctrl & S_REQ)
break;
state = state & STATE_MASK;
scsi_bus->data_w(scsi_refid, 0);
scsi_bus->ctrl_w(scsi_refid, 0, S_ACK);
step(false);
// byte's done, ask for another if the target hasn't said otherwise
if (m_mode & MODE_DMA)
{
drq_set();
}
break;
case RECV_WAIT_REQ_1 << SUB_SHIFT:
if(!(ctrl & S_REQ))
break;
state = (state & STATE_MASK) | (RECV_WAIT_SETTLE << SUB_SHIFT);
delay_cycles(sync_period);
break;
case RECV_WAIT_SETTLE << SUB_SHIFT:
if(!timeout)
break;
m_dmalatch = scsi_bus->data_r();
scsi_bus->ctrl_w(scsi_refid, S_ACK, S_ACK);
state = (state & STATE_MASK) | (RECV_WAIT_REQ_0 << SUB_SHIFT);
step(false);
break;
case RECV_WAIT_REQ_0 << SUB_SHIFT:
if(ctrl & S_REQ)
break;
state = state & STATE_MASK;
step(false);
drq_set(); // raise DRQ now that we've completed
break;
default:
printf("%s: step() unexpected state %d.%d\n",
tag(),
state & STATE_MASK, (state & SUB_MASK) >> SUB_SHIFT);
exit(0);
}
}
