int sceKernelRegisterSysEventHandler(SceSysEventHandler* handler)
{
int oldIntr1 = suspendIntr();
int oldIntr2 = suspendIntr();
SceSysEventHandler *cur = g_sysEvHandlers;
// CA90
while (cur != NULL)
{
if (cur == handler)
break;
cur = cur->next;
}
// CAA4
resumeIntr(oldIntr2);
if (cur == NULL)
{
handler->busy = 0;
// CAE0
handler->gp = pspGetGp();
handler->next = g_sysEvHandlers;
g_sysEvHandlers = handler;
resumeIntr(oldIntr1);
return 0;
}
resumeIntr(oldIntr1);
return 0x80020067;
}
int sceKernelUnregisterSysEventHandler(SceSysEventHandler *handler)
{
int oldIntr = suspendIntr();
if (handler->busy != 0)
{
// C8A8
resumeIntr(oldIntr);
return 0x80020001;
}
SceSysEventHandler *cur = g_sysEvHandlers;
SceSysEventHandler *prev = NULL;
// C84C
while (cur != NULL)
{
if (cur == handler)
{
// C88C
if (prev == NULL) {
// C8A0
g_sysEvHandlers = cur->next;
}
else
prev->next = cur->next;
break;
}
prev = cur;
cur = cur->next;
}
// C864
resumeIntr(oldIntr);
if (cur == NULL)
return 0x80020068;
return 0;
}
int sceKernelSysEventDispatch(int ev_type_mask, int ev_id, char* ev_name, void* param, int* result, int break_nonzero, SceSysEventHandler **break_handler)
{
int oldGp = pspGetGp();
int ret = 0;
int oldIntr = suspendIntr();
SceSysEventHandler *cur = g_sysEvHandlers;
// C928
while (cur != NULL)
{
if ((cur->type_mask & ev_type_mask) != 0)
{
// C984
cur->busy = 1;
resumeIntr(oldIntr);
pspSetGp(cur->gp);
ret = cur->handler(ev_id, ev_name, param, result);
oldIntr = suspendIntr();
cur->busy = 0;
if (ret < 0 && break_nonzero != 0)
{
// C9D8
if (break_handler != NULL)
*break_handler = cur;
break;
}
ret = 0;
}
// C934
cur = cur->next;
}
// C940
resumeIntr(oldIntr);
pspSetGp(oldGp);
return ret;
}
int sceKernelPowerUnlock(int unk)
{
if (g_powerHandlers == NULL)
{
// CB90
int oldIntr = suspendIntr();
g_numPowerLock--;
resumeIntr(oldIntr);
return 0;
}
return g_powerHandlers->unlock(unk);
}
int sceKernelRegisterResumeHandler(int reg, int (*handler)(int, void*), void *param)
{
if (reg < 0 || reg >= 32)
return -1;
int oldIntr = suspendIntr();
SceResumeHandler *cur = &g_resumeHandlers[reg];
cur->handler = handler;
cur->param = param;
cur->gp = pspGetGp();
resumeIntr(oldIntr);
return 0;
}
int sceKernelIsRegisterSysEventHandler(SceSysEventHandler* handler)
{
int oldIntr = suspendIntr();
SceSysEventHandler *cur = g_sysEvHandlers;
// CA24
while (cur != NULL)
{
if (cur == handler)
break;
cur = cur->next;
}
// CA38
resumeIntr(oldIntr);
return (cur != NULL);
}
//
// Get physical address from memory mapped TLB.
// SH3 version. SH4 can't do this method. because address/data array must be
// accessed from P2.
//
paddr_t
MemoryManager_SHMMU::searchPage(vaddr_t vaddr)
{
u_int32_t vpn, idx, s, dum, aae, dae, entry_idx, asid;
paddr_t paddr = ~0;
int way, kmode;
vpn = vaddr & SH3_PAGE_MASK;
// Windows CE uses VPN-only index-mode.
idx = vaddr & SH3_MMU_VPN_MASK;
kmode = SetKMode(1);
// Get current ASID
asid = _reg_read_4(SH3_PTEH) & SH3_PTEH_ASID_MASK;
// to avoid another TLB access, disable external interrupt.
s = suspendIntr();
do {
// load target address page to TLB
dum = _reg_read_4(vaddr);
_reg_write_4(vaddr, dum);
for (way = 0; way < SH3_MMU_WAY; way++) {
entry_idx = idx | (way << SH3_MMU_WAY_SHIFT);
// inquire MMU address array.
aae = _reg_read_4(SH3_MMUAA | entry_idx);
if (!(aae & SH3_MMU_D_VALID) ||
((aae & SH3_MMUAA_D_ASID_MASK) != asid) ||
(((aae | idx) & SH3_PAGE_MASK) != vpn))
continue;
// entry found.
// inquire MMU data array to get its physical address.
dae = _reg_read_4(SH3_MMUDA | entry_idx);
paddr = (dae & SH3_PAGE_MASK) | (vaddr & ~SH3_PAGE_MASK);
break;
}
} while (paddr == ~0);
resumeIntr(s);
SetKMode(kmode);
return paddr;
}
// INTC
void
SH4dev::icu_dump()
{
#define ON(x, c) ((x) & (c) ? check[1] : check[0])
#define _(n) DPRINTF((TEXT("%S %S "), #n, ON(r, SH4_ICR_ ## n)))
static const char *check[] = { "[_]", "[x]" };
u_int16_t r;
super::icu_dump_priority(_ipr_table);
r = _reg_read_2(SH4_ICR);
DPRINTF((TEXT("ICR: ")));
_(NMIL);
_(MAI);
_(NMIB);
_(NMIE);
_(IRLM);
DPRINTF((TEXT("0x%04x\n"), r));
#if 0 // monitoring SH4 interrupt request.
// disable SH3 internal devices interrupt.
suspendIntr();
_reg_write_2(SH4_IPRA, 0);
_reg_write_2(SH4_IPRB, 0);
_reg_write_2(SH4_IPRC, 0);
// _reg_write_2(SH4_IPRD, 0); SH7709S only.
resumeIntr(0); // all interrupts enable.
while (1) {
DPRINTF((TEXT("%04x ", _reg_read_2(HD64465_NIRR))));
bitdisp(_reg_read_4(SH4_INTEVT));
}
/* NOTREACHED */
#endif
#undef _
#undef ON
}
