void bootblock_mainboard_init(void)
{
if (rkclk_was_watchdog_reset())
reboot_from_watchdog();
gpio_output(GPIO(0, B, 3), 1); /* Power LED */
/* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */
setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL);
setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);
assert(CONFIG_PMIC_BUS == 0); /* must correspond with IOMUX */
i2c_init(CONFIG_PMIC_BUS, 400*KHz);
/* Slowly raise to max CPU voltage to prevent overshoot */
rk808_configure_buck(1, 1200);
udelay(175);/* Must wait for voltage to stabilize,2mV/us */
rk808_configure_buck(1, 1400);
udelay(100);/* Must wait for voltage to stabilize,2mV/us */
rkclk_configure_cpu(APLL_1800_MHZ);
/* i2c1 for tpm */
write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1);
i2c_init(1, 400*KHz);
/* spi2 for firmware ROM */
write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
setup_chromeos_gpios();
}
static void soc_init(struct device *dev)
{
/*
* Reserve the whole TZRAM area because it will be marked as secure-only
* by BL31 and can not be accessed by the non-secure kernel.
*/
mmio_resource(dev, 1, (TZRAM_BASE / KiB), (TZRAM_SIZE / KiB));
if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) && display_init_required())
rk_display_init(dev);
else
printk(BIOS_INFO, "Display initialization disabled.\n");
/* We don't need big CPUs, but bring them up as a courtesy to Linux. */
rkclk_configure_cpu(APLL_600_MHZ, CPU_CLUSTER_BIG);
}
static void mainboard_init(device_t dev)
{
gpio_output(GPIO_RESET, 0);
configure_usb();
configure_emmc();
configure_codec();
configure_3g();
/* No video. */
/* If recovery mode is detected, reduce frequency and voltage to reduce
* heat in case machine is left unattended. chrome-os-partner:41201. */
if (vboot_recovery_mode_enabled()) {
printk(BIOS_DEBUG, "Reducing APLL freq for recovery mode.\n");
rkclk_configure_cpu(APLL_600_MHZ);
rk808_configure_buck(1, 900);
}
}
void bootblock_soc_init(void)
{
rkclk_init();
rkclk_configure_cpu(APLL_600_MHZ, false);
/* all ddr range non-secure */
write32(&rk3399_pmusgrf->ddr_rgn_con[16], 0xff << 16 | 0);
/* tzma_rosize = 0, all sram non-secure */
write32(&rk3399_pmusgrf->soc_con4, 0x3ff << 16 | 0);
/* emmc master secure */
write32(&rk3399_pmusgrf->soc_con7, 1 << 23 | 1 << 24 | 0 << 8 | 0 << 7);
/* glb_slv_secure_bypass */
write32(&rk3399_pmusgrf->pmu_slv_con0, 1 << 16 | 1);
rockchip_mmu_init();
}
