static int c4iw_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
{
int len = vma->vm_end - vma->vm_start;
u32 key = vma->vm_pgoff << PAGE_SHIFT;
struct c4iw_rdev *rdev;
int ret = 0;
struct c4iw_mm_entry *mm;
struct c4iw_ucontext *ucontext;
u64 addr, paddr;
u64 va_regs_res = 0, va_udbs_res = 0;
u64 len_regs_res = 0, len_udbs_res = 0;
CTR3(KTR_IW_CXGBE, "%s:1 ctx %p vma %p", __func__, context, vma);
CTR4(KTR_IW_CXGBE, "%s:1a pgoff 0x%lx key 0x%x len %d", __func__,
vma->vm_pgoff, key, len);
if (vma->vm_start & (PAGE_SIZE-1)) {
CTR3(KTR_IW_CXGBE, "%s:2 unaligned vm_start %u vma %p",
__func__, vma->vm_start, vma);
return -EINVAL;
}
rdev = &(to_c4iw_dev(context->device)->rdev);
ucontext = to_c4iw_ucontext(context);
mm = remove_mmap(ucontext, key, len);
if (!mm) {
CTR4(KTR_IW_CXGBE, "%s:3 ucontext %p key %u len %u", __func__,
ucontext, key, len);
return -EINVAL;
}
addr = mm->addr;
kfree(mm);
va_regs_res = (u64)rman_get_virtual(rdev->adap->regs_res);
len_regs_res = (u64)rman_get_size(rdev->adap->regs_res);
va_udbs_res = (u64)rman_get_virtual(rdev->adap->udbs_res);
len_udbs_res = (u64)rman_get_size(rdev->adap->udbs_res);
CTR6(KTR_IW_CXGBE,
"%s:4 addr %p, masync region %p:%p, udb region %p:%p", __func__,
addr, va_regs_res, va_regs_res+len_regs_res, va_udbs_res,
va_udbs_res+len_udbs_res);
if (addr >= va_regs_res && addr < va_regs_res + len_regs_res) {
CTR4(KTR_IW_CXGBE, "%s:5 MA_SYNC addr %p region %p, reglen %u",
__func__, addr, va_regs_res, len_regs_res);
/*
* MA_SYNC register...
*/
paddr = vtophys(addr);
vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
ret = io_remap_pfn_range(vma, vma->vm_start,
paddr >> PAGE_SHIFT,
len, vma->vm_page_prot);
} else {
static int
bcma_nexus_attach(device_t dev)
{
int erom_rid;
int error;
struct resource *erom_res;
const struct bhnd_chipid *cid = BHND_BUS_GET_CHIPID(device_get_parent(dev), dev);
erom_rid = BCMA_NEXUS_EROM_RID;
error = bus_set_resource(dev, SYS_RES_MEMORY, erom_rid, cid->enum_addr, BCMA_EROM_TABLE_SIZE);
if (error != 0) {
BHND_ERROR_DEV(dev, "failed to set EROM resource");
return (error);
}
/* Map the EROM resource and enumerate our children. */
BHND_DEBUG_DEV(dev, "erom enum address: %jx", cid->enum_addr);
erom_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &erom_rid, RF_ACTIVE);
if (erom_res == NULL) {
BHND_ERROR_DEV(dev, "failed to allocate EROM resource");
return (ENXIO);
}
BHND_DEBUG_DEV(dev, "erom scanning start address: %p", rman_get_virtual(erom_res));
error = bcma_add_children(dev, erom_res, BCMA_EROM_TABLE_START);
/* Clean up */
bus_release_resource(dev, SYS_RES_MEMORY, erom_rid, erom_res);
if (error)
return (error);
/* Call our superclass' implementation */
return (bcma_attach(dev));
}
static int
xrpu_attach(device_t self)
{
struct softc *sc;
struct resource *res;
int rid, unit;
unit = device_get_unit(self);
sc = device_get_softc(self);
sc->mode = NORMAL;
rid = PCI_MAP_REG_START;
res = bus_alloc_resource(self, SYS_RES_MEMORY, &rid,
0, ~0, 1, RF_ACTIVE);
if (res == NULL) {
device_printf(self, "Could not map memory\n");
return ENXIO;
}
sc->virbase = (vm_offset_t)rman_get_virtual(res);
sc->physbase = rman_get_start(res);
sc->virbase62 = (u_int *)(sc->virbase + 0x800000);
if (bootverbose)
printf("Mapped physbase %#lx to virbase %#lx\n",
(u_long)sc->physbase, (u_long)sc->virbase);
make_dev(&xrpu_cdevsw, 0, UID_ROOT, GID_WHEEL, 0600, "xrpu%d", unit);
return 0;
}
static u_int32_t
ata_siiprb_softreset(device_t dev, int port)
{
struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
struct ata_channel *ch = device_get_softc(dev);
struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work;
u_int32_t signature;
int offset = ch->unit * 0x2000;
/* setup the workspace for a soft reset command */
bzero(prb, sizeof(struct ata_siiprb_command));
prb->control = htole16(0x0080);
prb->fis[1] = port & 0x0f;
/* issue soft reset */
if (ata_siiprb_issue_cmd(dev))
return -1;
ata_udelay(150000);
/* get possible signature */
prb = (struct ata_siiprb_command *)
((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset);
signature=prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24);
/* clear error bits/interrupt */
ATA_IDX_OUTL(ch, ATA_SERROR, 0xffffffff);
return signature;
}
static int
iop_pci_attach(device_t dev)
{
struct iop_softc *sc = device_get_softc(dev);
int rid;
bzero(sc, sizeof(struct iop_softc));
/* get resources */
rid = 0x10;
sc->r_mem =
bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
if (!sc->r_mem)
return 0;
rid = 0x00;
sc->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
RF_SHAREABLE | RF_ACTIVE);
/* now setup the infrastructure to talk to the device */
pci_enable_busmaster(dev);
sc->ibase = rman_get_virtual(sc->r_mem);
sc->reg = (struct i2o_registers *)sc->ibase;
sc->dev = dev;
mtx_init(&sc->mtx, "pst lock", NULL, MTX_DEF);
if (!iop_init(sc))
return 0;
return bus_generic_attach(dev);
}
static int
cy_isa_probe(device_t dev)
{
struct resource *mem_res;
cy_addr iobase;
int mem_rid;
if (isa_get_logicalid(dev) != 0) /* skip PnP probes */
return (ENXIO);
mem_rid = 0;
mem_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &mem_rid,
0ul, ~0ul, 0ul, RF_ACTIVE);
if (mem_res == NULL) {
device_printf(dev, "ioport resource allocation failed\n");
return (ENXIO);
}
iobase = rman_get_virtual(mem_res);
/* Cyclom-16Y hardware reset (Cyclom-8Ys don't care) */
cy_inb(iobase, CY16_RESET, 0); /* XXX? */
DELAY(500); /* wait for the board to get its act together */
/* this is needed to get the board out of reset */
cy_outb(iobase, CY_CLEAR_INTR, 0, 0);
DELAY(500);
bus_release_resource(dev, SYS_RES_MEMORY, mem_rid, mem_res);
return (cy_units(iobase, 0) == 0 ? ENXIO : 0);
}
void
vga_pci_unmap_bios(device_t dev, void *bios)
{
struct vga_resource *vr;
if (bios == NULL) {
return;
}
#if defined(__amd64__) || defined(__i386__) || defined(__ia64__)
if (vga_pci_is_boot_display(dev)) {
/* We mapped the BIOS shadow copy located at 0xC0000. */
pmap_unmapdev((vm_offset_t)bios, VGA_PCI_BIOS_SHADOW_SIZE);
return;
}
#endif
/*
* Look up the PCIR_BIOS resource in our softc. It should match
* the address we returned previously.
*/
vr = lookup_res(device_get_softc(dev), PCIR_BIOS);
KASSERT(vr->vr_res != NULL, ("vga_pci_unmap_bios: bios not mapped"));
KASSERT(rman_get_virtual(vr->vr_res) == bios,
("vga_pci_unmap_bios: mismatch"));
vga_pci_release_resource(dev, NULL, SYS_RES_MEMORY, PCIR_BIOS,
vr->vr_res);
}
void *
vga_pci_map_bios(device_t dev, size_t *size)
{
int rid;
struct resource *res;
#if defined(__amd64__) || defined(__i386__) || defined(__ia64__)
if (vga_pci_is_boot_display(dev)) {
/*
* On x86, the System BIOS copy the default display
* device's Video BIOS at a fixed location in system
* memory (0xC0000, 128 kBytes long) at boot time.
*
* We use this copy for the default boot device, because
* the original ROM may not be valid after boot.
*/
*size = VGA_PCI_BIOS_SHADOW_SIZE;
return (pmap_mapbios(VGA_PCI_BIOS_SHADOW_ADDR, *size));
}
#endif
rid = PCIR_BIOS;
res = vga_pci_alloc_resource(dev, NULL, SYS_RES_MEMORY, &rid, 0ul,
~0ul, 1, RF_ACTIVE);
if (res == NULL) {
return (NULL);
}
*size = rman_get_size(res);
return (rman_get_virtual(res));
}
void *os_map_pci_bar(
void *osext,
int index,
HPT_U32 offset,
HPT_U32 length
)
{
PHBA hba = (PHBA)osext;
HPT_U32 base;
hba->pcibar[index].rid = 0x10 + index * 4;
base = pci_read_config(hba->pcidev, hba->pcibar[index].rid, 4);
if (base & 1) {
hba->pcibar[index].type = SYS_RES_IOPORT;
hba->pcibar[index].res = bus_alloc_resource_any(hba->pcidev,
hba->pcibar[index].type, &hba->pcibar[index].rid, RF_ACTIVE);
hba->pcibar[index].base = (void *)(unsigned long)(base & ~0x1);
} else {
hba->pcibar[index].type = SYS_RES_MEMORY;
hba->pcibar[index].res = bus_alloc_resource_any(hba->pcidev,
hba->pcibar[index].type, &hba->pcibar[index].rid, RF_ACTIVE);
hba->pcibar[index].base = (char *)rman_get_virtual(hba->pcibar[index].res) + offset;
}
return hba->pcibar[index].base;
}
static int
nexus_deactivate_resource(device_t bus, device_t child, int type, int rid,
struct resource *r)
{
vm_offset_t va;
if (type == SYS_RES_MEMORY) {
va = (vm_offset_t)rman_get_virtual(r);
pmap_unmapdev(va, rman_get_size(r));
}
return (rman_deactivate_resource(r));
}
static int
nexus_deactivate_resource(device_t bus, device_t child, int type, int rid,
struct resource *r)
{
/*
* If this is a memory resource, unmap it.
*/
if (type == SYS_RES_MEMORY) {
pmap_unmapdev((vm_offset_t)rman_get_virtual(r),
rman_get_size(r));
}
return (rman_deactivate_resource(r));
}
static int
sbus_deactivate_resource(device_t bus, device_t child, int type, int rid,
struct resource *r)
{
if (type == SYS_RES_IRQ) {
return (BUS_DEACTIVATE_RESOURCE(device_get_parent(bus),
child, type, rid, r));
}
if (type == SYS_RES_MEMORY) {
sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r));
rman_set_virtual(r, NULL);
}
return (rman_deactivate_resource(r));
}
static int
zbpci_deactivate_resource(device_t bus, device_t child, int type, int rid,
struct resource *r)
{
vm_offset_t va;
if (type != SYS_RES_IOPORT) {
return (bus_generic_deactivate_resource(bus, child, type,
rid, r));
}
va = (vm_offset_t)rman_get_virtual(r);
pmap_unmapdev(va, rman_get_size(r));
return (rman_deactivate_resource(r));
}
static int
ofw_pci_deactivate_resource(device_t bus, device_t child, int type, int rid,
struct resource *res)
{
/*
* If this is a memory resource, unmap it.
*/
if ((type == SYS_RES_MEMORY) || (type == SYS_RES_IOPORT)) {
u_int32_t psize;
psize = rman_get_size(res);
pmap_unmapdev((vm_offset_t)rman_get_virtual(res), psize);
}
return (rman_deactivate_resource(res));
}
int
pci_map_mem(pcici_t cfg, u_long reg, vm_offset_t* va, vm_offset_t* pa)
{
int rid;
struct resource *res;
rid = reg;
res = bus_alloc_resource(cfg->dev, SYS_RES_MEMORY, &rid,
0, ~0, 1, RF_ACTIVE);
if (res) {
*pa = rman_get_start(res);
*va = (vm_offset_t) rman_get_virtual(res);
return (1);
}
return (0);
}
static int
nexus_deactivate_resource(device_t bus, device_t child, int type, int rid,
struct resource *r)
{
/*
* If this is a memory resource, unmap it.
*/
if ((rman_get_bustag(r) == I386_BUS_SPACE_MEM) && (r->r_end >= 1024 * 1024)) {
u_int32_t psize;
psize = r->r_end - r->r_start;
pmap_unmapdev((vm_offset_t)rman_get_virtual(r), psize);
}
return (rman_deactivate_resource(r));
}
static int
cy_isa_attach(device_t dev)
{
struct resource *irq_res, *mem_res;
void *irq_cookie, *vaddr, *vsc;
int irq_rid, mem_rid;
irq_res = NULL;
mem_res = NULL;
mem_rid = 0;
mem_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &mem_rid,
0ul, ~0ul, 0ul, RF_ACTIVE);
if (mem_res == NULL) {
device_printf(dev, "memory resource allocation failed\n");
goto fail;
}
vaddr = rman_get_virtual(mem_res);
vsc = cyattach_common(vaddr, 0);
if (vsc == NULL) {
device_printf(dev, "no ports found!\n");
goto fail;
}
irq_rid = 0;
irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, &irq_rid, 0ul, ~0ul, 0ul,
RF_SHAREABLE | RF_ACTIVE);
if (irq_res == NULL) {
device_printf(dev, "interrupt resource allocation failed\n");
goto fail;
}
if (bus_setup_intr(dev, irq_res, INTR_TYPE_TTY | INTR_FAST, cyintr,
vsc, &irq_cookie) != 0) {
device_printf(dev, "interrupt setup failed\n");
goto fail;
}
return (0);
fail:
if (irq_res != NULL)
bus_release_resource(dev, SYS_RES_IRQ, irq_rid, irq_res);
if (mem_res != NULL)
bus_release_resource(dev, SYS_RES_MEMORY, mem_rid, mem_res);
return (ENXIO);
}
static int
nexus_deactivate_resource(device_t bus __unused, device_t child __unused,
int type __unused, int rid __unused, struct resource *r)
{
/*
* If this is a memory resource, unmap it.
*/
if ((type == SYS_RES_MEMORY) || (type == SYS_RES_IOPORT)) {
bus_size_t psize;
psize = rman_get_size(r);
pmap_unmapdev((vm_offset_t)rman_get_virtual(r), psize);
}
return (rman_deactivate_resource(r));
}
static int
ata_siiprb_pm_write(device_t dev, int port, int reg, u_int32_t value)
{
struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
struct ata_channel *ch = device_get_softc(dev);
struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work;
int offset = ch->unit * 0x2000;
if (port < 0) {
ATA_IDX_OUTL(ch, reg, value);
return (0);
}
if (port < ATA_PM) {
switch (reg) {
case ATA_SSTATUS:
reg = 0;
break;
case ATA_SERROR:
reg = 1;
break;
case ATA_SCONTROL:
reg = 2;
break;
default:
return (EINVAL);
}
}
bzero(prb, sizeof(struct ata_siiprb_command));
prb->fis[0] = 0x27; /* host to device */
prb->fis[1] = 0x8f; /* command FIS to PM port */
prb->fis[2] = ATA_WRITE_PM;
prb->fis[3] = reg;
prb->fis[7] = port;
prb->fis[12] = value & 0xff;
prb->fis[4] = (value >> 8) & 0xff;
prb->fis[5] = (value >> 16) & 0xff;
prb->fis[6] = (value >> 24) & 0xff;
if (ata_siiprb_issue_cmd(dev)) {
device_printf(dev, "error writing PM port\n");
return ATA_E_ABORT;
}
prb = (struct ata_siiprb_command *)
((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset);
return prb->fis[3];
}
int
sparc64_bus_mem_unmap(bus_space_tag_t tag, bus_space_handle_t handle,
bus_size_t size)
{
vm_offset_t sva;
vm_offset_t va;
vm_offset_t endva;
if (tag->bst_cookie == NULL ||
(sva = (vm_offset_t)rman_get_virtual(tag->bst_cookie)) == 0)
return (0);
sva = trunc_page(sva);
endva = sva + round_page(size);
for (va = sva; va < endva; va += PAGE_SIZE)
pmap_kremove_flags(va);
tlb_range_demap(kernel_pmap, sva, sva + size - 1);
kmem_free(kernel_map, sva, size);
return (0);
}
static int
ata_siiprb_pm_read(device_t dev, int port, int reg, u_int32_t *result)
{
struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
struct ata_channel *ch = device_get_softc(dev);
struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work;
int offset = ch->unit * 0x2000;
if (port < 0) {
*result = ATA_IDX_INL(ch, reg);
return (0);
}
if (port < ATA_PM) {
switch (reg) {
case ATA_SSTATUS:
reg = 0;
break;
case ATA_SERROR:
reg = 1;
break;
case ATA_SCONTROL:
reg = 2;
break;
default:
return (EINVAL);
}
}
bzero(prb, sizeof(struct ata_siiprb_command));
prb->fis[0] = 0x27; /* host to device */
prb->fis[1] = 0x8f; /* command FIS to PM port */
prb->fis[2] = ATA_READ_PM;
prb->fis[3] = reg;
prb->fis[7] = port;
if (ata_siiprb_issue_cmd(dev)) {
device_printf(dev, "error reading PM port\n");
return EIO;
}
prb = (struct ata_siiprb_command *)
((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset);
*result = prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24);
return 0;
}
/* channel interface */
static void *
nmchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
{
struct sc_info *sc = devinfo;
struct sc_chinfo *ch;
u_int32_t chnbuf;
chnbuf = (dir == PCMDIR_PLAY)? sc->pbuf : sc->rbuf;
ch = (dir == PCMDIR_PLAY)? &sc->pch : &sc->rch;
ch->active = 0;
ch->blksize = 0;
ch->wmark = 0;
ch->buffer = b;
sndbuf_setup(ch->buffer, (u_int8_t *)rman_get_virtual(sc->buf) + chnbuf, NM_BUFFSIZE);
if (bootverbose)
device_printf(sc->dev, "%s buf %p\n", (dir == PCMDIR_PLAY)?
"play" : "rec", sndbuf_getbuf(ch->buffer));
ch->parent = sc;
ch->channel = c;
ch->dir = dir;
return ch;
}
static int
nexus_deactivate_resource(device_t bus, device_t child, int type, int rid,
struct resource *r)
{
/*
* If this is a memory resource, unmap it.
*/
if (type == SYS_RES_MEMORY) {
pmap_unmapdev((vm_offset_t)rman_get_virtual(r),
rman_get_size(r));
}
#ifdef PC98
if (type == SYS_RES_MEMORY || type == SYS_RES_IOPORT) {
bus_space_handle_t bh;
bh = rman_get_bushandle(r);
i386_bus_space_handle_free(rman_get_bustag(r), bh, bh->bsh_sz);
}
#endif
return (rman_deactivate_resource(r));
}
void *os_map_pci_bar(
void *osext,
int index,
HPT_U32 offset,
HPT_U32 length
)
{
PHBA hba = (PHBA)osext;
hba->pcibar[index].rid = 0x10 + index * 4;
if (pci_read_config(hba->pcidev, hba->pcibar[index].rid, 4) & 1)
hba->pcibar[index].type = SYS_RES_IOPORT;
else
hba->pcibar[index].type = SYS_RES_MEMORY;
hba->pcibar[index].res = bus_alloc_resource(hba->pcidev,
hba->pcibar[index].type, &hba->pcibar[index].rid, 0, ~0, length, RF_ACTIVE);
hba->pcibar[index].base = (char *)rman_get_virtual(hba->pcibar[index].res) + offset;
return hba->pcibar[index].base;
}
static int
smapi_attach (device_t dev)
{
struct smapi_softc *sc;
int error;
sc = device_get_softc(dev);
error = 0;
sc->dev = dev;
sc->rid = 0;
sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->rid,
RF_ACTIVE);
if (sc->res == NULL) {
device_printf(dev, "Unable to allocate memory resource.\n");
error = ENOMEM;
goto bad;
}
sc->header = (struct smapi_bios_header *)rman_get_virtual(sc->res);
sc->smapi32_entry = (u_int32_t)BIOS_PADDRTOVADDR(
sc->header->prot32_segment +
sc->header->prot32_offset);
sc->cdev = make_dev(&smapi_cdevsw,
device_get_unit(sc->dev),
UID_ROOT, GID_WHEEL, 0600,
"%s%d",
smapi_cdevsw.d_name,
device_get_unit(sc->dev));
device_printf(dev, "Version: %d.%02d, Length: %d, Checksum: 0x%02x\n",
bcd2bin(sc->header->version_major),
bcd2bin(sc->header->version_minor),
sc->header->length,
sc->header->checksum);
device_printf(dev, "Information=0x%b\n",
sc->header->information,
"\020"
"\001REAL_VM86"
"\002PROTECTED_16"
"\003PROTECTED_32");
if (bootverbose) {
if (sc->header->information & SMAPI_REAL_VM86)
device_printf(dev, "Real/VM86 mode: Segment 0x%04x, Offset 0x%04x\n",
sc->header->real16_segment,
sc->header->real16_offset);
if (sc->header->information & SMAPI_PROT_16BIT)
device_printf(dev, "16-bit Protected mode: Segment 0x%08x, Offset 0x%04x\n",
sc->header->prot16_segment,
sc->header->prot16_offset);
if (sc->header->information & SMAPI_PROT_32BIT)
device_printf(dev, "32-bit Protected mode: Segment 0x%08x, Offset 0x%08x\n",
sc->header->prot32_segment,
sc->header->prot32_offset);
}
return (0);
bad:
if (sc->res)
bus_release_resource(dev, SYS_RES_MEMORY, sc->rid, sc->res);
return (error);
}
static int
si_pci_attach(device_t dev)
{
struct si_softc *sc;
void *ih;
int error;
error = 0;
ih = NULL;
sc = device_get_softc(dev);
switch (pci_get_devid(dev)) {
case 0x400011cb:
sc->sc_type = SIPCI;
sc->sc_mem_rid = SIPCIBADR;
break;
case 0x200011cb:
sc->sc_type = SIJETPCI;
sc->sc_mem_rid = SIJETBADR;
break;
}
sc->sc_mem_res = bus_alloc_resource(dev, SYS_RES_MEMORY,
&sc->sc_mem_rid,
0, ~0, 1, RF_ACTIVE);
if (!sc->sc_mem_res) {
device_printf(dev, "couldn't map memory\n");
goto fail;
}
sc->sc_paddr = (caddr_t)rman_get_start(sc->sc_mem_res);
sc->sc_maddr = rman_get_virtual(sc->sc_mem_res);
sc->sc_irq_rid = 0;
sc->sc_irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->sc_irq_rid,
0, ~0, 1, RF_ACTIVE | RF_SHAREABLE);
if (!sc->sc_irq_res) {
device_printf(dev, "couldn't map interrupt\n");
goto fail;
}
sc->sc_irq = rman_get_start(sc->sc_irq_res);
error = bus_setup_intr(dev, sc->sc_irq_res, INTR_MPSAFE, si_intr, sc, &ih, NULL);
if (error) {
device_printf(dev, "could not activate interrupt\n");
goto fail;
}
error = siattach(dev);
if (error)
goto fail;
return (0); /* success */
fail:
if (error == 0)
error = ENXIO;
if (sc->sc_irq_res) {
if (ih)
bus_teardown_intr(dev, sc->sc_irq_res, ih);
bus_release_resource(dev, SYS_RES_IRQ,
sc->sc_irq_rid, sc->sc_irq_res);
sc->sc_irq_res = 0;
}
if (sc->sc_mem_res) {
bus_release_resource(dev, SYS_RES_MEMORY,
sc->sc_mem_rid, sc->sc_mem_res);
sc->sc_mem_res = 0;
}
return (error);
}
static int vgdrvFreeBSDAttach(device_t pDevice)
{
int rc;
int iResId;
struct VBoxGuestDeviceState *pState;
cUsers = 0;
/*
* Initialize IPRT R0 driver, which internally calls OS-specific r0 init.
*/
rc = RTR0Init(0);
if (RT_FAILURE(rc))
{
LogFunc(("RTR0Init failed.\n"));
return ENXIO;
}
pState = device_get_softc(pDevice);
/*
* Allocate I/O port resource.
*/
iResId = PCIR_BAR(0);
pState->pIOPortRes = bus_alloc_resource_any(pDevice, SYS_RES_IOPORT, &iResId, RF_ACTIVE);
pState->uIOPortBase = rman_get_start(pState->pIOPortRes);
pState->iIOPortResId = iResId;
if (pState->uIOPortBase)
{
/*
* Map the MMIO region.
*/
iResId = PCIR_BAR(1);
pState->pVMMDevMemRes = bus_alloc_resource_any(pDevice, SYS_RES_MEMORY, &iResId, RF_ACTIVE);
pState->VMMDevMemHandle = rman_get_bushandle(pState->pVMMDevMemRes);
pState->VMMDevMemSize = rman_get_size(pState->pVMMDevMemRes);
pState->pMMIOBase = rman_get_virtual(pState->pVMMDevMemRes);
pState->iVMMDevMemResId = iResId;
if (pState->pMMIOBase)
{
/*
* Call the common device extension initializer.
*/
rc = VGDrvCommonInitDevExt(&g_DevExt, pState->uIOPortBase,
pState->pMMIOBase, pState->VMMDevMemSize,
#if ARCH_BITS == 64
VBOXOSTYPE_FreeBSD_x64,
#else
VBOXOSTYPE_FreeBSD,
#endif
VMMDEV_EVENT_MOUSE_POSITION_CHANGED);
if (RT_SUCCESS(rc))
{
/*
* Add IRQ of VMMDev.
*/
rc = vgdrvFreeBSDAddIRQ(pDevice, pState);
if (RT_SUCCESS(rc))
{
/*
* Read host configuration.
*/
VGDrvCommonProcessOptionsFromHost(&g_DevExt);
/*
* Configure device cloning.
*/
clone_setup(&g_pvgdrvFreeBSDClones);
g_vgdrvFreeBSDEHTag = EVENTHANDLER_REGISTER(dev_clone, vgdrvFreeBSDClone, 0, 1000);
if (g_vgdrvFreeBSDEHTag)
{
printf(DEVICE_NAME ": loaded successfully\n");
return 0;
}
printf(DEVICE_NAME ": EVENTHANDLER_REGISTER(dev_clone,,,) failed\n");
clone_cleanup(&g_pvgdrvFreeBSDClones);
vgdrvFreeBSDRemoveIRQ(pDevice, pState);
}
else
printf((DEVICE_NAME ": VGDrvCommonInitDevExt failed.\n"));
VGDrvCommonDeleteDevExt(&g_DevExt);
}
else
printf((DEVICE_NAME ": vgdrvFreeBSDAddIRQ failed.\n"));
}
else
printf((DEVICE_NAME ": MMIO region setup failed.\n"));
}
else
printf((DEVICE_NAME ": IOport setup failed.\n"));
RTR0Term();
return ENXIO;
}
/*
* Probe and vendor specific initialization for the HP PC Lan+ Cards.
* (HP Part nos: 27247B and 27252A).
*
* The card has an asic wrapper around a DS8390 core. The asic handles
* host accesses and offers both standard register IO and memory mapped
* IO. Memory mapped I/O allows better performance at the expense of greater
* chance of an incompatibility with existing ISA cards.
*
* The card has a few caveats: it isn't tolerant of byte wide accesses, only
* short (16 bit) or word (32 bit) accesses are allowed. Some card revisions
* don't allow 32 bit accesses; these are indicated by a bit in the software
* ID register (see if_edreg.h).
*
* Other caveats are: we should read the MAC address only when the card
* is inactive.
*
* For more information; please consult the CRYNWR packet driver.
*
* The AUI port is turned on using the "link2" option on the ifconfig
* command line.
*/
int
ed_probe_HP_pclanp(device_t dev, int port_rid, int flags)
{
struct ed_softc *sc = device_get_softc(dev);
int error;
int n; /* temp var */
int memsize; /* mem on board */
u_char checksum; /* checksum of board address */
u_char irq; /* board configured IRQ */
uint8_t test_pattern[ED_HPP_TEST_SIZE]; /* read/write areas for */
uint8_t test_buffer[ED_HPP_TEST_SIZE]; /* probing card */
rman_res_t conf_maddr, conf_msize, conf_irq, junk;
error = ed_alloc_port(dev, 0, ED_HPP_IO_PORTS);
if (error)
return (error);
/* Fill in basic information */
sc->asic_offset = ED_HPP_ASIC_OFFSET;
sc->nic_offset = ED_HPP_NIC_OFFSET;
sc->chip_type = ED_CHIP_TYPE_DP8390;
sc->isa16bit = 0; /* the 8390 core needs to be in byte mode */
/*
* Look for the HP PCLAN+ signature: "0x50,0x48,0x00,0x53"
*/
if ((ed_asic_inb(sc, ED_HPP_ID) != 0x50) ||
(ed_asic_inb(sc, ED_HPP_ID + 1) != 0x48) ||
((ed_asic_inb(sc, ED_HPP_ID + 2) & 0xF0) != 0) ||
(ed_asic_inb(sc, ED_HPP_ID + 3) != 0x53))
return (ENXIO);
/*
* Read the MAC address and verify checksum on the address.
*/
ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_MAC);
for (n = 0, checksum = 0; n < ETHER_ADDR_LEN; n++)
checksum += (sc->enaddr[n] =
ed_asic_inb(sc, ED_HPP_MAC_ADDR + n));
checksum += ed_asic_inb(sc, ED_HPP_MAC_ADDR + ETHER_ADDR_LEN);
if (checksum != 0xFF)
return (ENXIO);
/*
* Verify that the software model number is 0.
*/
ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_ID);
if (((sc->hpp_id = ed_asic_inw(sc, ED_HPP_PAGE_4)) &
ED_HPP_ID_SOFT_MODEL_MASK) != 0x0000)
return (ENXIO);
/*
* Read in and save the current options configured on card.
*/
sc->hpp_options = ed_asic_inw(sc, ED_HPP_OPTION);
sc->hpp_options |= (ED_HPP_OPTION_NIC_RESET |
ED_HPP_OPTION_CHIP_RESET | ED_HPP_OPTION_ENABLE_IRQ);
/*
* Reset the chip. This requires writing to the option register
* so take care to preserve the other bits.
*/
ed_asic_outw(sc, ED_HPP_OPTION,
(sc->hpp_options & ~(ED_HPP_OPTION_NIC_RESET |
ED_HPP_OPTION_CHIP_RESET)));
DELAY(5000); /* wait for chip reset to complete */
ed_asic_outw(sc, ED_HPP_OPTION,
(sc->hpp_options | (ED_HPP_OPTION_NIC_RESET |
ED_HPP_OPTION_CHIP_RESET |
ED_HPP_OPTION_ENABLE_IRQ)));
DELAY(5000);
if (!(ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST))
return (ENXIO); /* reset did not complete */
/*
* Read out configuration information.
*/
ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_HW);
irq = ed_asic_inb(sc, ED_HPP_HW_IRQ);
/*
* Check for impossible IRQ.
*/
if (irq >= (sizeof(ed_hpp_intr_val) / sizeof(ed_hpp_intr_val[0])))
return (ENXIO);
/*
* If the kernel IRQ was specified with a '?' use the cards idea
* of the IRQ. If the kernel IRQ was explicitly specified, it
* should match that of the hardware.
*/
error = bus_get_resource(dev, SYS_RES_IRQ, 0, &conf_irq, &junk);
if (error)
bus_set_resource(dev, SYS_RES_IRQ, 0, ed_hpp_intr_val[irq], 1);
else {
if (conf_irq != ed_hpp_intr_val[irq])
return (ENXIO);
}
/*
* Fill in softconfig info.
*/
sc->vendor = ED_VENDOR_HP;
sc->type = ED_TYPE_HP_PCLANPLUS;
sc->type_str = "HP-PCLAN+";
sc->mem_shared = 0; /* we DON'T have dual ported RAM */
sc->mem_start = 0; /* we use offsets inside the card RAM */
sc->hpp_mem_start = NULL;/* no memory mapped I/O by default */
/*
* The board has 32KB of memory. Is there a way to determine
* this programmatically?
*/
memsize = 32768;
/*
* Check if memory mapping of the I/O registers possible.
*/
if (sc->hpp_options & ED_HPP_OPTION_MEM_ENABLE) {
u_long mem_addr;
/*
* determine the memory address from the board.
*/
ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_HW);
mem_addr = (ed_asic_inw(sc, ED_HPP_HW_MEM_MAP) << 8);
/*
* Check that the kernel specified start of memory and
* hardware's idea of it match.
*/
error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
&conf_maddr, &conf_msize);
if (error)
return (error);
if (mem_addr != conf_maddr)
return (ENXIO);
error = ed_alloc_memory(dev, 0, memsize);
if (error)
return (error);
sc->hpp_mem_start = rman_get_virtual(sc->mem_res);
}
/*
* Fill in the rest of the soft config structure.
*/
/*
* The transmit page index.
*/
sc->tx_page_start = ED_HPP_TX_PAGE_OFFSET;
if (device_get_flags(dev) & ED_FLAGS_NO_MULTI_BUFFERING)
sc->txb_cnt = 1;
else
sc->txb_cnt = 2;
/*
* Memory description
*/
sc->mem_size = memsize;
sc->mem_ring = sc->mem_start +
(sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE);
sc->mem_end = sc->mem_start + sc->mem_size;
/*
* Receive area starts after the transmit area and
* continues till the end of memory.
*/
sc->rec_page_start = sc->tx_page_start +
(sc->txb_cnt * ED_TXBUF_SIZE);
sc->rec_page_stop = (sc->mem_size / ED_PAGE_SIZE);
sc->cr_proto = 0; /* value works */
/*
* Set the wrap registers for string I/O reads.
*/
ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_HW);
ed_asic_outw(sc, ED_HPP_HW_WRAP,
((sc->rec_page_start / ED_PAGE_SIZE) |
(((sc->rec_page_stop / ED_PAGE_SIZE) - 1) << 8)));
/*
* Reset the register page to normal operation.
*/
ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_PERF);
/*
* Verify that we can read/write from adapter memory.
* Create test pattern.
*/
for (n = 0; n < ED_HPP_TEST_SIZE; n++)
test_pattern[n] = (n*n) ^ ~n;
#undef ED_HPP_TEST_SIZE
/*
* Check that the memory is accessible thru the I/O ports.
* Write out the contents of "test_pattern", read back
* into "test_buffer" and compare the two for any
* mismatch.
*/
for (n = 0; n < (32768 / ED_PAGE_SIZE); n ++) {
ed_hpp_writemem(sc, test_pattern, (n * ED_PAGE_SIZE),
sizeof(test_pattern));
ed_hpp_readmem(sc, (n * ED_PAGE_SIZE),
test_buffer, sizeof(test_pattern));
if (bcmp(test_pattern, test_buffer,
sizeof(test_pattern)))
return (ENXIO);
}
sc->sc_mediachg = ed_hpp_set_physical_link;
sc->sc_write_mbufs = ed_hpp_write_mbufs;
sc->readmem = ed_hpp_readmem;
return (0);
}
static int
sbsh_attach(device_t dev)
{
struct sbsh_softc *sc;
struct ifnet *ifp;
int unit, error = 0, rid;
sc = device_get_softc(dev);
unit = device_get_unit(dev);
rid = PCIR_MAPS + 4;
sc->mem_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
0, ~0, 4096, RF_ACTIVE);
if (sc->mem_res == NULL) {
kprintf ("sbsh%d: couldn't map memory\n", unit);
error = ENXIO;
goto fail;
}
rid = 0;
sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
RF_SHAREABLE | RF_ACTIVE);
if (sc->irq_res == NULL) {
kprintf("sbsh%d: couldn't map interrupt\n", unit);
error = ENXIO;
goto fail;
}
sc->mem_base = rman_get_virtual(sc->mem_res);
init_card(sc);
/* generate ethernet MAC address */
*(u_int32_t *)sc->arpcom.ac_enaddr = htonl(0x00ff0192);
read_random_unlimited(sc->arpcom.ac_enaddr + 4, 2);
ifp = &sc->arpcom.ac_if;
ifp->if_softc = sc;
if_initname(ifp, "sbsh", unit);
ifp->if_mtu = ETHERMTU;
ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
ifp->if_ioctl = sbsh_ioctl;
ifp->if_start = sbsh_start;
ifp->if_watchdog = sbsh_watchdog;
ifp->if_init = sbsh_init;
ifp->if_baudrate = 4600000;
ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN);
ifq_set_ready(&ifp->if_snd);
ether_ifattach(ifp, sc->arpcom.ac_enaddr, NULL);
ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->irq_res));
error = bus_setup_intr(dev, sc->irq_res, INTR_MPSAFE,
sbsh_intr, sc, &sc->intr_hand,
ifp->if_serializer);
if (error) {
ether_ifdetach(ifp);
kprintf("sbsh%d: couldn't set up irq\n", unit);
goto fail;
}
return(0);
fail:
sbsh_detach(dev);
return (error);
}
static int
digi_pci_attach(device_t dev)
{
struct digi_softc *sc;
u_int32_t device_id;
#ifdef DIGI_INTERRUPT
int retVal = 0;
#endif
sc = device_get_softc(dev);
KASSERT(sc, ("digi%d: softc not allocated in digi_pci_attach\n",
device_get_unit(dev)));
bzero(sc, sizeof(*sc));
sc->dev = dev;
sc->res.unit = device_get_unit(dev);
device_id = pci_get_devid(dev);
switch (device_id >> 16) {
case PCI_DEVICE_EPC:
sc->name = "Digiboard PCI EPC/X ASIC";
sc->res.mrid = 0x10;
sc->model = PCIEPCX;
sc->module = "EPCX_PCI";
break;
case PCI_DEVICE_XEM:
sc->name = "Digiboard PCI PC/Xem ASIC";
sc->res.mrid = 0x10;
sc->model = PCXEM;
sc->module = "Xem";
break;
case PCI_DEVICE_XR:
sc->name = "Digiboard PCI PC/Xr ASIC";
sc->res.mrid = 0x10;
sc->model = PCIXR;
sc->module = "Xr";
break;
case PCI_DEVICE_CX:
sc->name = "Digiboard PCI C/X ASIC";
sc->res.mrid = 0x10;
sc->model = PCCX;
sc->module = "CX_PCI";
break;
case PCI_DEVICE_XRJ:
sc->name = "Digiboard PCI PC/Xr PLX";
sc->res.mrid = 0x18;
sc->model = PCIXR;
sc->module = "Xr";
break;
case PCI_DEVICE_EPCJ:
sc->name = "Digiboard PCI EPC/X PLX";
sc->res.mrid = 0x18;
sc->model = PCIEPCX;
sc->module = "EPCX_PCI";
break;
case PCI_DEVICE_920_4: /* Digi PCI4r 920 */
sc->name = "Digiboard PCI4r 920";
sc->res.mrid = 0x10;
sc->model = PCIXR;
sc->module = "Xr";
break;
case PCI_DEVICE_920_8: /* Digi PCI8r 920 */
sc->name = "Digiboard PCI8r 920";
sc->res.mrid = 0x10;
sc->model = PCIXR;
sc->module = "Xr";
break;
case PCI_DEVICE_920_2: /* Digi PCI2r 920 */
sc->name = "Digiboard PCI2r 920";
sc->res.mrid = 0x10;
sc->model = PCIXR;
sc->module = "Xr";
break;
default:
device_printf(dev, "Unknown device id = %08x\n", device_id);
return (ENXIO);
}
pci_write_config(dev, 0x40, 0, 4);
pci_write_config(dev, 0x46, 0, 4);
sc->res.mem = bus_alloc_resource(dev, SYS_RES_MEMORY, &sc->res.mrid,
0, ~0, 1, RF_ACTIVE);
#ifdef DIGI_INTERRUPT
sc->res.irqrid = 0;
sc->res.irq = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->res.irqrid,
0, ~0, 1, RF_SHAREABLE | RF_ACTIVE);
if (sc->res.irq == NULL) {
device_printf(dev, "couldn't map interrupt\n");
return (ENXIO);
}
retVal = bus_setup_intr(dev, sc->res.irq, INTR_MPSAFE, digiintr, sc,
&sc->res.irqHandler, NULL);
#else
DLOG(DIGIDB_IRQ, (sc->dev, "Interrupt support compiled out\n"));
#endif
sc->vmem = rman_get_virtual(sc->res.mem);
sc->pmem = vtophys(sc->vmem);
sc->pcibus = 1;
sc->win_size = 0x200000;
sc->win_bits = 21;
sc->csigs = &digi_normal_signals;
sc->status = DIGI_STATUS_NOTINIT;
callout_init(&sc->callout);
callout_init(&sc->inttest);
sc->setwin = digi_pci_setwin;
sc->hidewin = digi_pci_hidewin;
sc->towin = digi_pci_towin;
PCIPORT = FEPRST;
return (digi_attach(sc));
}
