static int __devinit rtl8180_probe(struct pci_dev *pdev, const struct pci_device_id *id) { struct ieee80211_hw *dev; struct rtl8180_priv *priv; unsigned long mem_addr, mem_len; unsigned int io_addr, io_len; int err, i; struct eeprom_93cx6 eeprom; const char *chip_name, *rf_name = NULL; u32 reg; u16 eeprom_val; err = pci_enable_device(pdev); if (err) { printk(KERN_ERR "%s (rtl8180): Cannot enable new PCI device\n", pci_name(pdev)); return err; } err = pci_request_regions(pdev, KBUILD_MODNAME); if (err) { printk(KERN_ERR "%s (rtl8180): Cannot obtain PCI resources\n", pci_name(pdev)); return err; } io_addr = pci_resource_start(pdev, 0); io_len = pci_resource_len(pdev, 0); mem_addr = pci_resource_start(pdev, 1); mem_len = pci_resource_len(pdev, 1); if (mem_len < sizeof(struct rtl818x_csr) || io_len < sizeof(struct rtl818x_csr)) { printk(KERN_ERR "%s (rtl8180): Too short PCI resources\n", pci_name(pdev)); err = -ENOMEM; goto err_free_reg; } if ((err = pci_set_dma_mask(pdev, 0xFFFFFF00ULL)) || (err = pci_set_consistent_dma_mask(pdev, 0xFFFFFF00ULL))) { printk(KERN_ERR "%s (rtl8180): No suitable DMA available\n", pci_name(pdev)); goto err_free_reg; } pci_set_master(pdev); dev = ieee80211_alloc_hw(sizeof(*priv), &rtl8180_ops); if (!dev) { printk(KERN_ERR "%s (rtl8180): ieee80211 alloc failed\n", pci_name(pdev)); err = -ENOMEM; goto err_free_reg; } priv = dev->priv; priv->pdev = pdev; dev->max_rates = 2; SET_IEEE80211_DEV(dev, &pdev->dev); pci_set_drvdata(pdev, dev); priv->map = pci_iomap(pdev, 1, mem_len); if (!priv->map) priv->map = pci_iomap(pdev, 0, io_len); if (!priv->map) { printk(KERN_ERR "%s (rtl8180): Cannot map device memory\n", pci_name(pdev)); goto err_free_dev; } BUILD_BUG_ON(sizeof(priv->channels) != sizeof(rtl818x_channels)); BUILD_BUG_ON(sizeof(priv->rates) != sizeof(rtl818x_rates)); memcpy(priv->channels, rtl818x_channels, sizeof(rtl818x_channels)); memcpy(priv->rates, rtl818x_rates, sizeof(rtl818x_rates)); priv->band.band = IEEE80211_BAND_2GHZ; priv->band.channels = priv->channels; priv->band.n_channels = ARRAY_SIZE(rtl818x_channels); priv->band.bitrates = priv->rates; priv->band.n_bitrates = 4; dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band; dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | IEEE80211_HW_RX_INCLUDES_FCS | IEEE80211_HW_SIGNAL_UNSPEC; dev->queues = 1; dev->max_signal = 65; reg = rtl818x_ioread32(priv, &priv->map->TX_CONF); reg &= RTL818X_TX_CONF_HWVER_MASK; switch (reg) { case RTL818X_TX_CONF_R8180_ABCD: chip_name = "RTL8180"; break; case RTL818X_TX_CONF_R8180_F: chip_name = "RTL8180vF"; break; case RTL818X_TX_CONF_R8185_ABC: chip_name = "RTL8185"; break; case RTL818X_TX_CONF_R8185_D: chip_name = "RTL8185vD"; break; default: printk(KERN_ERR "%s (rtl8180): Unknown chip! (0x%x)\n", pci_name(pdev), reg >> 25); goto err_iounmap; } priv->r8185 = reg & RTL818X_TX_CONF_R8185_ABC; if (priv->r8185) { priv->band.n_bitrates = ARRAY_SIZE(rtl818x_rates); pci_try_set_mwi(pdev); } eeprom.data = dev; eeprom.register_read = rtl8180_eeprom_register_read; eeprom.register_write = rtl8180_eeprom_register_write; if (rtl818x_ioread32(priv, &priv->map->RX_CONF) & (1 << 6)) eeprom.width = PCI_EEPROM_WIDTH_93C66; else eeprom.width = PCI_EEPROM_WIDTH_93C46; rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_PROGRAM); rtl818x_ioread8(priv, &priv->map->EEPROM_CMD); udelay(10); eeprom_93cx6_read(&eeprom, 0x06, &eeprom_val); eeprom_val &= 0xFF; switch (eeprom_val) { case 1: rf_name = "Intersil"; break; case 2: rf_name = "RFMD"; break; case 3: priv->rf = &sa2400_rf_ops; break; case 4: priv->rf = &max2820_rf_ops; break; case 5: priv->rf = &grf5101_rf_ops; break; case 9: priv->rf = rtl8180_detect_rf(dev); break; case 10: rf_name = "RTL8255"; break; default: printk(KERN_ERR "%s (rtl8180): Unknown RF! (0x%x)\n", pci_name(pdev), eeprom_val); goto err_iounmap; } if (!priv->rf) { printk(KERN_ERR "%s (rtl8180): %s RF frontend not supported!\n", pci_name(pdev), rf_name); goto err_iounmap; } eeprom_93cx6_read(&eeprom, 0x17, &eeprom_val); priv->csthreshold = eeprom_val >> 8; if (!priv->r8185) { __le32 anaparam; eeprom_93cx6_multiread(&eeprom, 0xD, (__le16 *)&anaparam, 2); priv->anaparam = le32_to_cpu(anaparam); eeprom_93cx6_read(&eeprom, 0x19, &priv->rfparam); } eeprom_93cx6_multiread(&eeprom, 0x7, (__le16 *)dev->wiphy->perm_addr, 3); if (!is_valid_ether_addr(dev->wiphy->perm_addr)) { printk(KERN_WARNING "%s (rtl8180): Invalid hwaddr! Using" " randomly generated MAC addr\n", pci_name(pdev)); random_ether_addr(dev->wiphy->perm_addr); } /* CCK TX power */ for (i = 0; i < 14; i += 2) { u16 txpwr; eeprom_93cx6_read(&eeprom, 0x10 + (i >> 1), &txpwr); priv->channels[i].hw_value = txpwr & 0xFF; priv->channels[i + 1].hw_value = txpwr >> 8; } /* OFDM TX power */ if (priv->r8185) { for (i = 0; i < 14; i += 2) { u16 txpwr; eeprom_93cx6_read(&eeprom, 0x20 + (i >> 1), &txpwr); priv->channels[i].hw_value |= (txpwr & 0xFF) << 8; priv->channels[i + 1].hw_value |= txpwr & 0xFF00; } } rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL); spin_lock_init(&priv->lock); err = ieee80211_register_hw(dev); if (err) { printk(KERN_ERR "%s (rtl8180): Cannot register device\n", pci_name(pdev)); goto err_iounmap; } printk(KERN_INFO "%s: hwaddr %pM, %s + %s\n", wiphy_name(dev->wiphy), dev->wiphy->perm_addr, chip_name, priv->rf->name); return 0; err_iounmap: iounmap(priv->map); err_free_dev: pci_set_drvdata(pdev, NULL); ieee80211_free_hw(dev); err_free_reg: pci_release_regions(pdev); pci_disable_device(pdev); return err; }
static void sa2400_rf_init(struct ieee80211_hw *dev) { struct rtl8180_priv *priv = dev->priv; u32 anaparam, txconf; u8 firdac; int analogphy = priv->rfparam & RF_PARAM_ANALOGPHY; anaparam = priv->anaparam; anaparam &= ~(1 << ANAPARAM_TXDACOFF_SHIFT); anaparam &= ~ANAPARAM_PWR1_MASK; anaparam &= ~ANAPARAM_PWR0_MASK; if (analogphy) { anaparam |= SA2400_ANA_ANAPARAM_PWR1_ON << ANAPARAM_PWR1_SHIFT; firdac = 0; } else { anaparam |= (SA2400_DIG_ANAPARAM_PWR1_ON << ANAPARAM_PWR1_SHIFT); anaparam |= (SA2400_ANAPARAM_PWR0_ON << ANAPARAM_PWR0_SHIFT); firdac = 1 << SA2400_REG4_FIRDAC_SHIFT; } rtl8180_set_anaparam(priv, anaparam); write_sa2400(dev, 0, sa2400_chan[0]); write_sa2400(dev, 1, 0xbb50); write_sa2400(dev, 2, 0x80); write_sa2400(dev, 3, 0); write_sa2400(dev, 4, 0x19340 | firdac); write_sa2400(dev, 5, 0x1dfb | (SA2400_MAX_SENS - 54) << 15); write_sa2400(dev, 4, 0x19348 | firdac); /* calibrate VCO */ if (!analogphy) write_sa2400(dev, 4, 0x1938c); /*???*/ write_sa2400(dev, 4, 0x19340 | firdac); write_sa2400(dev, 0, sa2400_chan[0]); write_sa2400(dev, 1, 0xbb50); write_sa2400(dev, 2, 0x80); write_sa2400(dev, 3, 0); write_sa2400(dev, 4, 0x19344 | firdac); /* calibrate filter */ /* new from rtl8180 embedded driver (rtl8181 project) */ write_sa2400(dev, 6, 0x13ff | (1 << 23)); /* MANRX */ write_sa2400(dev, 8, 0); /* VCO */ if (analogphy) { rtl8180_set_anaparam(priv, anaparam | (1 << ANAPARAM_TXDACOFF_SHIFT)); txconf = rtl818x_ioread32(priv, &priv->map->TX_CONF); rtl818x_iowrite32(priv, &priv->map->TX_CONF, txconf | RTL818X_TX_CONF_LOOPBACK_CONT); write_sa2400(dev, 4, 0x19341); /* calibrates DC */ /* a 5us sleep is required here, * we rely on the 3ms delay introduced in write_sa2400 */ write_sa2400(dev, 4, 0x19345); /* a 20us sleep is required here, * we rely on the 3ms delay introduced in write_sa2400 */ rtl818x_iowrite32(priv, &priv->map->TX_CONF, txconf); rtl8180_set_anaparam(priv, anaparam); } /* end new code */ write_sa2400(dev, 4, 0x19341 | firdac); /* RTX MODE */ /* baseband configuration */ rtl8180_write_phy(dev, 0, 0x98); rtl8180_write_phy(dev, 3, 0x38); rtl8180_write_phy(dev, 4, 0xe0); rtl8180_write_phy(dev, 5, 0x90); rtl8180_write_phy(dev, 6, 0x1a); rtl8180_write_phy(dev, 7, 0x64); sa2400_write_phy_antenna(dev, 1); rtl8180_write_phy(dev, 0x11, 0x80); if (rtl818x_ioread8(priv, &priv->map->CONFIG2) & RTL818X_CONFIG2_ANTENNA_DIV) rtl8180_write_phy(dev, 0x12, 0xc7); /* enable ant diversity */ else rtl8180_write_phy(dev, 0x12, 0x47); /* disable ant diversity */ rtl8180_write_phy(dev, 0x13, 0x90 | priv->csthreshold); rtl8180_write_phy(dev, 0x19, 0x0); rtl8180_write_phy(dev, 0x1a, 0xa0); }
static int rtl8180_start(struct ieee80211_hw *dev) { struct rtl8180_priv *priv = dev->priv; int ret, i; u32 reg; ret = rtl8180_init_rx_ring(dev); if (ret) return ret; for (i = 0; i < 4; i++) if ((ret = rtl8180_init_tx_ring(dev, i, 16))) goto err_free_rings; ret = rtl8180_init_hw(dev); if (ret) goto err_free_rings; rtl818x_iowrite32(priv, &priv->map->RDSAR, priv->rx_ring_dma); rtl818x_iowrite32(priv, &priv->map->TBDA, priv->tx_ring[3].dma); rtl818x_iowrite32(priv, &priv->map->THPDA, priv->tx_ring[2].dma); rtl818x_iowrite32(priv, &priv->map->TNPDA, priv->tx_ring[1].dma); rtl818x_iowrite32(priv, &priv->map->TLPDA, priv->tx_ring[0].dma); ret = request_irq(priv->pdev->irq, &rtl8180_interrupt, IRQF_SHARED, KBUILD_MODNAME, dev); if (ret) { printk(KERN_ERR "%s: failed to register IRQ handler\n", wiphy_name(dev->wiphy)); goto err_free_rings; } rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF); rtl818x_iowrite32(priv, &priv->map->MAR[0], ~0); rtl818x_iowrite32(priv, &priv->map->MAR[1], ~0); reg = RTL818X_RX_CONF_ONLYERLPKT | RTL818X_RX_CONF_RX_AUTORESETPHY | RTL818X_RX_CONF_MGMT | RTL818X_RX_CONF_DATA | (7 << 8 /* MAX RX DMA */) | RTL818X_RX_CONF_BROADCAST | RTL818X_RX_CONF_NICMAC; if (priv->r8185) reg |= RTL818X_RX_CONF_CSDM1 | RTL818X_RX_CONF_CSDM2; else { reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE1) ? RTL818X_RX_CONF_CSDM1 : 0; reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE2) ? RTL818X_RX_CONF_CSDM2 : 0; } priv->rx_conf = reg; rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg); if (priv->r8185) { reg = rtl818x_ioread8(priv, &priv->map->CW_CONF); reg &= ~RTL818X_CW_CONF_PERPACKET_CW_SHIFT; reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT; rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg); reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL); reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT; reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT; reg |= RTL818X_TX_AGC_CTL_FEEDBACK_ANT; rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg); /* disable early TX */ rtl818x_iowrite8(priv, (u8 __iomem *)priv->map + 0xec, 0x3f); } reg = rtl818x_ioread32(priv, &priv->map->TX_CONF); reg |= (6 << 21 /* MAX TX DMA */) | RTL818X_TX_CONF_NO_ICV; if (priv->r8185) reg &= ~RTL818X_TX_CONF_PROBE_DTS; else reg &= ~RTL818X_TX_CONF_HW_SEQNUM; /* different meaning, same value on both rtl8185 and rtl8180 */ reg &= ~RTL818X_TX_CONF_SAT_HWPLCP; rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg); reg = rtl818x_ioread8(priv, &priv->map->CMD); reg |= RTL818X_CMD_RX_ENABLE; reg |= RTL818X_CMD_TX_ENABLE; rtl818x_iowrite8(priv, &priv->map->CMD, reg); priv->mode = NL80211_IFTYPE_MONITOR; return 0; err_free_rings: rtl8180_free_rx_ring(dev); for (i = 0; i < 4; i++) if (priv->tx_ring[i].desc) rtl8180_free_tx_ring(dev, i); return ret; }
static int rtl818x_start(struct net80211_device *dev) { struct rtl818x_priv *priv = dev->priv; int ret; u32 reg; ret = rtl818x_init_rx_ring(dev); if (ret) return ret; ret = rtl818x_init_tx_ring(dev); if (ret) goto err_free_rings; ret = rtl818x_init_hw(dev); if (ret) goto err_free_rings; rtl818x_set_hwaddr(dev, dev->netdev->ll_addr); rtl818x_iowrite32(priv, &priv->map->RDSAR, priv->rx_ring_dma); rtl818x_iowrite32(priv, &priv->map->TNPDA, priv->tx_ring_dma); rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0); rtl818x_iowrite32(priv, &priv->map->MAR[0], ~0); rtl818x_iowrite32(priv, &priv->map->MAR[1], ~0); reg = RTL818X_RX_CONF_ONLYERLPKT | RTL818X_RX_CONF_RX_AUTORESETPHY | RTL818X_RX_CONF_MGMT | RTL818X_RX_CONF_DATA | (7 << 8 /* MAX RX DMA */) | RTL818X_RX_CONF_BROADCAST | RTL818X_RX_CONF_NICMAC; if (priv->r8185) reg |= RTL818X_RX_CONF_CSDM1 | RTL818X_RX_CONF_CSDM2; else { reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE1) ? RTL818X_RX_CONF_CSDM1 : 0; reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE2) ? RTL818X_RX_CONF_CSDM2 : 0; } priv->rx_conf = reg; rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg); if (priv->r8185) { reg = rtl818x_ioread8(priv, &priv->map->CW_CONF); reg &= ~RTL818X_CW_CONF_PERPACKET_CW_SHIFT; reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT; rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg); reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL); reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT; reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT; reg |= RTL818X_TX_AGC_CTL_FEEDBACK_ANT; rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg); /* disable early TX */ rtl818x_iowrite8(priv, (u8 *)priv->map + 0xec, 0x3f); } reg = rtl818x_ioread32(priv, &priv->map->TX_CONF); reg |= (6 << 21 /* MAX TX DMA */) | RTL818X_TX_CONF_NO_ICV; if (priv->r8185) reg &= ~RTL818X_TX_CONF_PROBE_DTS; else reg &= ~RTL818X_TX_CONF_HW_SEQNUM; /* different meaning, same value on both rtl8185 and rtl8180 */ reg &= ~RTL818X_TX_CONF_SAT_HWPLCP; rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg); reg = rtl818x_ioread8(priv, &priv->map->CMD); reg |= RTL818X_CMD_RX_ENABLE; reg |= RTL818X_CMD_TX_ENABLE; rtl818x_iowrite8(priv, &priv->map->CMD, reg); DBG("%s rtl818x: started\n", dev->netdev->name); return 0; err_free_rings: rtl818x_free_rx_ring(dev); if (priv->tx_ring) rtl818x_free_tx_ring(dev); DBG("%s rtl818x: failed to start\n", dev->netdev->name); return ret; }