/* Perform a hardware rate measurement for a given clock.
FOR DEBUG USE ONLY: Measurements take ~15 ms! */
signed soc_clk_measure_rate(unsigned id)
{
struct clk_local *t = &soc_clk_local_tbl[id];
unsigned long flags;
uint32_t regval, prph_web_reg_old;
uint64_t raw_count_short, raw_count_full;
signed ret;
if (t->test_vector == 0)
return -EPERM;
spin_lock_irqsave(&local_clock_reg_lock, flags);
/* Program test vector. */
if (t->test_vector <= 0xFF) {
/* Select CLK_TEST_2 */
writel(0x4D40, CLK_TEST_BASE_REG);
writel(t->test_vector, CLK_TEST_2_BASE_REG);
} else
writel(t->test_vector, CLK_TEST_BASE_REG);
/* Enable TCXO4 clock branch and root. */
prph_web_reg_old = readl(PRPH_WEB_NS_BASE_REG);
regval = prph_web_reg_old | B(9) | B(11);
local_src_enable(TCXO);
writel(regval, PRPH_WEB_NS_BASE_REG);
/*
* The ring oscillator counter will not reset if the measured clock
* is not running. To detect this, run a short measurement before
* the full measurement. If the raw results of the two are the same
* then the clock must be off.
*/
/* Run a short measurement. (~1 ms) */
raw_count_short = run_measurement(0x1000);
/* Run a full measurement. (~14 ms) */
raw_count_full = run_measurement(0x10000);
/* Disable TCXO4 clock branch and root. */
writel(prph_web_reg_old, PRPH_WEB_NS_BASE_REG);
local_src_disable(TCXO);
/* Return 0 if the clock is off. */
if (raw_count_full == raw_count_short)
ret = 0;
else {
/* Compute rate in Hz. */
raw_count_full = ((raw_count_full * 10) + 15) * 4800000;
do_div(raw_count_full, ((0x10000 * 10) + 35));
ret = (signed)raw_count_full;
}
spin_unlock_irqrestore(&local_clock_reg_lock, flags);
return ret;
}
/* Perform a hardware rate measurement for a given clock.
FOR DEBUG USE ONLY: Measurements take ~15 ms! */
static unsigned long measure_clk_get_rate(struct clk *c)
{
uint32_t pdm_reg_backup, ringosc_reg_backup;
uint64_t raw_count_short, raw_count_full;
struct measure_clk *clk = to_measure_clk(c);
unsigned ret;
ret = clk_enable(&cxo_clk.c);
if (ret) {
dprintf(CRITICAL, "CXO clock failed to enable. Can't measure\n");
return 0;
}
/* Enable CXO/4 and RINGOSC branch and root. */
pdm_reg_backup = readl_relaxed(PDM_CLK_NS_REG);
ringosc_reg_backup = readl_relaxed(RINGOSC_NS_REG);
writel_relaxed(0x2898, PDM_CLK_NS_REG);
writel_relaxed(0xA00, RINGOSC_NS_REG);
/*
* The ring oscillator counter will not reset if the measured clock
* is not running. To detect this, run a short measurement before
* the full measurement. If the raw results of the two are the same
* then the clock must be off.
*/
/* Run a short measurement. (~1 ms) */
raw_count_short = run_measurement(0x1000);
/* Run a full measurement. (~14 ms) */
raw_count_full = run_measurement(clk->sample_ticks);
writel_relaxed(ringosc_reg_backup, RINGOSC_NS_REG);
writel_relaxed(pdm_reg_backup, PDM_CLK_NS_REG);
/* Return 0 if the clock is off. */
if (raw_count_full == raw_count_short)
ret = 0;
else {
/* Compute rate in Hz. */
raw_count_full = ((raw_count_full * 10) + 15) * 4800000;
raw_count_full /= ((clk->sample_ticks * 10) + 35);
ret = (raw_count_full * clk->multiplier);
}
/* Route dbg_hs_clk to PLLTEST. 300mV single-ended amplitude. */
writel_relaxed(0x38F8, PLLTEST_PAD_CFG_REG);
clk_disable(&cxo_clk.c);
return ret;
}
static void
run (void *cls, char *const *args, const char *cfgfile,
const struct GNUNET_CONFIGURATION_Handle *cfg)
{
unsigned long long p1_quota_in = 10000;
unsigned long long p1_quota_out = 10000;
unsigned long long p2_quota_in = 10000;
unsigned long long p2_quota_out = 10000;
if (NULL != strstr (test_name, "asymmetric"))
{
GNUNET_log (GNUNET_ERROR_TYPE_DEBUG,
"Running asymmetric test with sending peer unlimited, receiving peer (in/out): %llu/%llu b/s \n",
p2_quota_in, p2_quota_out);
p1_quota_out = 1024 * 1024 * 1024;
p1_quota_in = 1024 * 1024 * 1024;
}
else
{
GNUNET_log (GNUNET_ERROR_TYPE_DEBUG,
"Running symmetric test with (in/out) %llu/%llu b/s \n",
p2_quota_in, p2_quota_out);
}
run_measurement (p1_quota_in, p1_quota_out, p2_quota_in, p2_quota_out);
}
