static int s35390a_set_alarm(struct i2c_client *client, struct rtc_wkalrm *alm)
{
struct s35390a *s35390a = i2c_get_clientdata(client);
char buf[3], sts = 0;
int err, i;
dev_dbg(&client->dev, "%s: alm is secs=%d, mins=%d, hours=%d mday=%d, "\
"mon=%d, year=%d, wday=%d\n", __func__, alm->time.tm_sec,
alm->time.tm_min, alm->time.tm_hour, alm->time.tm_mday,
alm->time.tm_mon, alm->time.tm_year, alm->time.tm_wday);
/* disable interrupt */
err = s35390a_set_reg(s35390a, S35390A_CMD_STATUS2, &sts, sizeof(sts));
if (err < 0)
return err;
/* clear pending interrupt, if any */
err = s35390a_get_reg(s35390a, S35390A_CMD_STATUS1, &sts, sizeof(sts));
if (err < 0)
return err;
if (alm->enabled)
sts = S35390A_INT2_MODE_ALARM;
else
sts = S35390A_INT2_MODE_NOINTR;
/* This chip expects the bits of each byte to be in reverse order */
sts = bitrev8(sts);
/* set interupt mode*/
err = s35390a_set_reg(s35390a, S35390A_CMD_STATUS2, &sts, sizeof(sts));
if (err < 0)
return err;
if (alm->time.tm_wday != -1)
buf[S35390A_ALRM_BYTE_WDAY] = bin2bcd(alm->time.tm_wday) | 0x80;
buf[S35390A_ALRM_BYTE_HOURS] = s35390a_hr2reg(s35390a,
alm->time.tm_hour) | 0x80;
buf[S35390A_ALRM_BYTE_MINS] = bin2bcd(alm->time.tm_min) | 0x80;
if (alm->time.tm_hour >= 12)
buf[S35390A_ALRM_BYTE_HOURS] |= 0x40;
for (i = 0; i < 3; ++i)
buf[i] = bitrev8(buf[i]);
err = s35390a_set_reg(s35390a, S35390A_CMD_INT2_REG1, buf,
sizeof(buf));
return err;
}
static int s35390a_alarm_irq_enable(struct i2c_client *client, unsigned enabled)
{
struct s35390a *s35390a = i2c_get_clientdata(client);
struct rtc_wkalrm *alm;
char buf[3], sts;
int err, i;
err = s35390a_get_reg(s35390a, S35390A_CMD_STATUS2, &sts, sizeof(sts));
if (err) {
dev_err(&client->dev, "%s: failed to read STS2 reg\n", __func__);
return err;
}
/* This chip returns the bits of each byte in reverse order */
sts = bitrev8(sts);
sts &= ~S35390A_INT1_MODE_MASK;
if (enabled)
sts |= S35390A_INT1_MODE_ALARM;
else
sts |= S35390A_INT1_MODE_NOINTR;
/* This chip returns the bits of each byte in reverse order */
sts = bitrev8(sts);
err = s35390a_set_reg(s35390a, S35390A_CMD_STATUS2, &sts, sizeof(sts));
if (err) {
dev_err(&client->dev, "%s: failed to set STS2 reg\n", __func__);
return err;
}
alm = &s35390a->alarm;
if (alm->time.tm_wday != -1)
buf[S35390A_ALRM_BYTE_WDAY] = bin2bcd(alm->time.tm_wday) | 0x80;
buf[S35390A_ALRM_BYTE_HOURS] = s35390a_hr2reg(s35390a,
alm->time.tm_hour) | 0x80;
buf[S35390A_ALRM_BYTE_MINS] = bin2bcd(alm->time.tm_min) | 0x80;
if (alm->time.tm_hour >= 12)
buf[S35390A_ALRM_BYTE_HOURS] |= 0x40;
/* This chip expects the bits of each byte to be in reverse order */
for (i = 0; i < 3; ++i)
buf[i] = bitrev8(buf[i]);
return s35390a_set_reg(s35390a, S35390A_CMD_INT1_REG1, buf, sizeof(buf));
}
/**
* @brief Set S35390A Alarm Interrupt settings, using INT2
* @param enable[in] : Alarm Interrupt enable (0 disable/1 enable).
* @param pending[in] : Alarm Interrupt pending (0 not pending/1 pending).
* @param time[in] : Alarm time value.
*/
static int s35390a_set_alarm(unsigned char enable, unsigned char pending, struct rtc_time *alarm)
{
unsigned char time[4] = {0};
unsigned char reg = 0x40; /*use INT2: 0x40 use INT1: 0x04;*/
unsigned char tmp = 0;
unsigned char weekDayEn = 0x80;
int ret = 0;
if(alarm->tm_hour >= 12){
tmp = 0x40;
}
DEBUG0("Set alarm %d-%d-%d-%d-%d-%d\n", alarm->tm_year+1900, alarm->tm_mon, alarm->tm_mday, alarm->tm_hour, alarm->tm_min, alarm->tm_sec);
alarm->tm_wday = day_of_week(alarm->tm_year+1900, alarm->tm_mon, alarm->tm_mday);
time[0] = bin2bcd(alarm->tm_wday) | weekDayEn;/*0x80 will make weekDay enable*/
time[1] = bin2bcd(alarm->tm_hour) | 0x80;
time[1] = time[1] |tmp;/*must set am/pm whether 12 or 24*/
time[2] = bin2bcd(alarm->tm_min) | 0x80;
//DEBUG0("Set alarm[0x%x][0x%x][0x%x]\n", time[0], time[1], time[2]);
/**/
ret = s35390a_get_reg(EXT_RTC_STS_REG2, ®, 1);
if(ret != SP_OK)
return ret;
if(enable == 1){
reg &= 0x0f;
reg |= 0x40;
ret = s35390a_set_reg(EXT_RTC_STS_REG2, ®, 1);
}else{
reg &= 0x0f;
ret = s35390a_set_reg(EXT_RTC_STS_REG2, ®, 1);
}
if(ret != SP_OK)
return ret;
ret = s35390a_set_reg(EXT_RTC_INT_REG2, time, 3);
if(ret != SP_OK)
return ret;
ret = s35390a_get_reg(EXT_RTC_STS_REG2, ®, 1);
if(ret != SP_OK)
return ret;
//DEBUG0("enable = %d, REG = 0x%x \n", enable, reg);
return ret;
}
static int s35390a_set_datetime(struct i2c_client *client, struct rtc_time *tm)
{
struct s35390a *s35390a = i2c_get_clientdata(client);
int i, err;
char buf[7];
dev_dbg(&client->dev, "%s: tm is secs=%d, mins=%d, hours=%d mday=%d, "
"mon=%d, year=%d, wday=%d\n", __func__, tm->tm_sec,
tm->tm_min, tm->tm_hour, tm->tm_mday, tm->tm_mon, tm->tm_year,
tm->tm_wday);
buf[S35390A_BYTE_YEAR] = bin2bcd(tm->tm_year - 100);
buf[S35390A_BYTE_MONTH] = bin2bcd(tm->tm_mon + 1);
buf[S35390A_BYTE_DAY] = bin2bcd(tm->tm_mday);
buf[S35390A_BYTE_WDAY] = bin2bcd(tm->tm_wday);
buf[S35390A_BYTE_HOURS] = s35390a_hr2reg(s35390a, tm->tm_hour);
buf[S35390A_BYTE_MINS] = bin2bcd(tm->tm_min);
buf[S35390A_BYTE_SECS] = bin2bcd(tm->tm_sec);
/* This chip expects the bits of each byte to be in reverse order */
for (i = 0; i < 7; ++i)
buf[i] = bitrev8(buf[i]);
err = s35390a_set_reg(s35390a, S35390A_CMD_TIME1, buf, sizeof(buf));
return err;
}
static int s35390a_clear_alarm_int(void)
{
unsigned char sts = 0;
unsigned char reg = 0x00;
int ret = 0;
ret = s35390a_get_reg(EXT_RTC_STS_REG2,®,1);
if(ret != SP_OK)
return ret;
reg &= 0x0f;
ret = s35390a_set_reg(EXT_RTC_STS_REG2,®,1);
if(ret != SP_OK)
return ret;
ret = s35390a_get_reg(EXT_RTC_STS_REG1,&sts,1);
if(ret != SP_OK)
return ret;
if ((sts&0x20)==0x20) { /*INT1:(sts&0x10)==0x10; INT2:(sts&0x20)==0x20 */
DEBUG0("External RTC alarm INT clear OK\n ");
return SP_OK;
}
return SP_FAIL;
}
static int s35390a_set_adjust(unsigned char adj_data)
{
unsigned char reg1, reg2 = 0;
int retryCount = 10;
int ret;
/* Set External RTC EXT_RTC_ADJ_REG */
reg1 = adj_data;
while ( retryCount-- > 0 ) {
/* write */
ret = s35390a_set_reg( EXT_RTC_ADJ_REG, ®1, 1 );
if ( SP_OK == ret ) {
break;
}
}
if ( SP_FAIL == ret ) {
return SP_FAIL;
}
retryCount = 10;
while ( retryCount-- > 0 ) {
/* read back */
s35390a_get_reg(EXT_RTC_ADJ_REG, ®2, 1);
if ( reg1 == reg2 )
break;
}
return retryCount == 0 ? SP_FAIL : SP_OK;
}
/**
*@brief Set int1 output frequency
*/
static int s35390a_int1_output_freq(unsigned int frequency)
{
unsigned char sts_reg2, int_reg1;
s35390a_get_reg(EXT_RTC_STS_REG2, &sts_reg2, 1);
sts_reg2 &= 0xf0;
sts_reg2 |= 0x01;
s35390a_set_reg(EXT_RTC_STS_REG2, &sts_reg2, 1);
if(frequency == 16)
int_reg1 = 0x08;/*Out put 16HZ to INT1*/
else
int_reg1 = 0x10;/*Out put 8HZ to INT1*/
s35390a_set_reg(EXT_RTC_INT_REG1, &int_reg1, 1);
s35390a_get_reg(EXT_RTC_STS_REG2, &sts_reg2, 1);
s35390a_set_reg(EXT_RTC_INT_REG1, &int_reg1, 1);
DIAG_VERB("output_frequency: sts_reg2, int_reg1 = 0x%x, 0x%x \n", sts_reg2, int_reg1);
return SP_OK;
}
static int s35390a_freq_irq_enable(struct i2c_client *client, unsigned enabled)
{
struct s35390a *s35390a = i2c_get_clientdata(client);
char buf[1];
int err;
err = s35390a_get_reg(s35390a, S35390A_CMD_STATUS2, buf, sizeof(buf));
if (err) {
dev_err(&client->dev, "%s: failed to read STS2 reg\n", __func__);
return err;
}
/* This chip returns the bits of each byte in reverse order */
buf[0] = bitrev8(buf[0]);
buf[0] &= ~S35390A_INT1_MODE_MASK;
if (enabled)
buf[0] |= S35390A_INT1_MODE_FREQ;
else
buf[0] |= S35390A_INT1_MODE_NOINTR;
/* This chip returns the bits of each byte in reverse order */
buf[0] = bitrev8(buf[0]);
err = s35390a_set_reg(s35390a, S35390A_CMD_STATUS2, buf, sizeof(buf));
if (err) {
dev_err(&client->dev, "%s: failed to set STS2 reg\n", __func__);
return err;
}
if (enabled) {
buf[0] = s35390a->rtc->irq_freq;
buf[0] = bitrev8(buf[0]);
err = s35390a_set_reg(s35390a, S35390A_CMD_INT1_REG1, buf,
sizeof(buf));
}
return err;
}
static int s35390a_disable_test_mode(struct s35390a *s35390a)
{
char buf[1];
if (s35390a_get_reg(s35390a, S35390A_CMD_STATUS2, buf, sizeof(buf)) < 0)
return -EIO;
if (!(buf[0] & S35390A_FLAG_TEST))
return 0;
buf[0] &= ~S35390A_FLAG_TEST;
return s35390a_set_reg(s35390a, S35390A_CMD_STATUS2, buf, sizeof(buf));
}
static int s35390a_reset(struct s35390a *s35390a)
{
char buf[1];
if (s35390a_get_reg(s35390a, S35390A_CMD_STATUS1, buf, sizeof(buf)) < 0)
return -EIO;
if (!(buf[0] & (S35390A_FLAG_POC | S35390A_FLAG_BLD)))
return 0;
buf[0] |= (S35390A_FLAG_RESET | S35390A_FLAG_24H);
buf[0] &= 0xf0;
return s35390a_set_reg(s35390a, S35390A_CMD_STATUS1, buf, sizeof(buf));
}
static int gp_ext_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
unsigned char i = 0;
unsigned char time[7];
int ret = 0;
DEBUG0("[%s]: Enter!\n", __FUNCTION__);
DEBUG0("Y,M,D = %d, %d, %d \n", tm->tm_year, tm->tm_mon, tm->tm_mday);
if(!gp_ext_rtc_info){
return (-EPERM);
}
/*Check year*/
if(tm->tm_year >= 1900)
tm->tm_year -= 1900;
if(tm->tm_year < 100) /*Base on 2000*/
return (-EPERM);
tm->tm_mon += 1; /*upper layer:0~11; s35390a: 1~12*/
time[0] = tm->tm_year-100; /*UI base on 1900,but external base on 2000*/
time[1] = tm->tm_mon;
time[2] = tm->tm_mday;
tm->tm_wday = day_of_week(tm->tm_year+1900, tm->tm_mon, tm->tm_mday);
time[3] = tm->tm_wday;
time[4] = tm->tm_hour;
time[5] = tm->tm_min;
time[6] = tm->tm_sec;
//DEBUG0("To Reg:y[%d] m[%d] d[%d] h[%d] m[%d] s[%d]\n",time[0],time[1],time[2],time[4],time[5],time[6]);
for (i=0;i<7;i++) {
time[i] = bin2bcd(time[i]);
}
spin_lock_irq(&gp_ext_rtc_info->lock);
ret = s35390a_set_reg(EXT_RTC_TIME_REG1, time, 7);/*read real time*/
if(ret != SP_OK)
ret = (-EIO);
spin_unlock_irq(&gp_ext_rtc_info->lock);
return ret;
}
/**
*@brief Check started or not
*/
static int s35390a_check_started(unsigned char *pReg)
{
unsigned char reg1_sts;
unsigned char reg2_sts;
int ret = 0;
int retry = 10;
/*unsigned char tmp = 0;*/
ret = s35390a_get_reg(EXT_RTC_STS_REG1, ®1_sts,1);
if( ret != SP_OK ) {
*pReg = 0;
return ret;
}
if(((reg1_sts&0x80)==0x80)||((reg1_sts&0x40)==0x40)){ /*poc or boc is 1*/
DIAG_INFO("\nExternal RTC first start up!\n\n");
while(1) {
/*Ïò׎̬ŒÄŽæÆ÷1µÄBIT0ÐŽÈë1œøÐÐreset*/
reg1_sts = reg1_sts|0x01;
s35390a_set_reg(EXT_RTC_STS_REG1, ®1_sts, 1);
#if 0
/*×ÔÓɌĎæÆ÷£¬Öµ¿É×ÔÓÉÉ趚£¬¿ÉÓÃΪRTC reliableµÄÅбð*/
tmp = 0xa5;
halExtRtcRegWrite(EXT_RTC_FREE_REG,&tmp,1);
#endif
s35390a_get_reg(EXT_RTC_STS_REG2,®2_sts, 1);
if ((reg2_sts&0x80)==0){/*TEST bit is 0*/
ret = SP_OK;
break;
}
if( retry < 0 ) {
ret = SP_FAIL;
break;
}
else {
retry--;
}
}
}
*pReg = reg1_sts;
return ret;
}
/**
*@brief Set alarm interrupt
*/
static int s35390a_set_alarm_int(unsigned char enable)
{
unsigned char int_reg2 = 0;
int ret = 0;
/*int2 for alarm */
ret = s35390a_get_reg(EXT_RTC_STS_REG2, &int_reg2, 1);
if(ret != SP_OK)
return ret;
if(enable == 1){
int_reg2 &= 0x0f;
int_reg2 |= 0x40;
}
else{
int_reg2 &= 0x0f;
}
return s35390a_set_reg(EXT_RTC_STS_REG2, &int_reg2, 1); /*set sts_reg2*/
}
/**
*@brief Set time format
*/
static int s35390a_set_12or24_format(unsigned char format)
{
unsigned char reg1_sts;
int ret;
ret = s35390a_get_reg(EXT_RTC_STS_REG1,®1_sts,1);
if( ret != SP_OK ) {
return ret;
}
if (format == 0) {
/* 12 hours */
reg1_sts = reg1_sts&0xfd;
} else {
/* 24 hours */
reg1_sts = reg1_sts|0x02;
}
return s35390a_set_reg(EXT_RTC_STS_REG1, ®1_sts, 1); /*set sts_reg1*/
}
static int s35390a_update_irq_enable(struct i2c_client *client, unsigned enabled)
{
struct s35390a *s35390a = i2c_get_clientdata(client);
char buf[1];
if (s35390a_get_reg(s35390a, S35390A_CMD_STATUS2, buf, sizeof(buf)) < 0)
return -EIO;
/* This chip returns the bits of each byte in reverse order */
buf[0] = bitrev8(buf[0]);
buf[0] &= ~S35390A_INT1_MODE_MASK;
if (enabled)
buf[0] |= S35390A_INT1_MODE_PMIN_EDG;
else
buf[0] |= S35390A_INT1_MODE_NOINTR;
/* This chip returns the bits of each byte in reverse order */
buf[0] = bitrev8(buf[0]);
return s35390a_set_reg(s35390a, S35390A_CMD_STATUS2, buf, sizeof(buf));
}
