/* * reset the cpu by setting up the watchdog timer and let him time out */ void reset_cpu(ulong ignored) { struct s3c24x0_watchdog *watchdog; #ifdef CONFIG_TRAB extern void disable_vfd(void); disable_vfd(); #endif watchdog = s3c24x0_get_base_watchdog(); /* Disable watchdog */ writel(0x0000, &watchdog->WTCON); /* Initialize watchdog timer count register */ writel(0x0001, &watchdog->WTCNT); /* Enable watchdog timer; assert reset at timer timeout */ writel(0x0021, &watchdog->WTCON); while (1) /* loop forever and wait for reset to happen */; /*NOTREACHED*/ }
void Timer_StartEx(void) { struct s3c24x0_watchdog * const wdtregs = s3c24x0_get_base_watchdog(); wdtregs->WTCON=((get_PCLK()/1000000-1)<<8)|(0<<3)|(1<<2); // 16us wdtregs->WTDAT=0xffff; wdtregs->WTCNT=0xffff; // 1/16/(65+1),interrupt enable,reset disable,watchdog enable wdtregs->WTCON=((get_PCLK()/1000000-1)<<8)|(0<<3)|(1<<2)|(0<<0)|(1<<5); }
unsigned int Timer_StopEx(void) { int count; struct s3c24x0_watchdog * const wdtregs = s3c24x0_get_base_watchdog(); struct s3c24x0_interrupt * const intregs = s3c24x0_get_base_interrupt(); wdtregs->WTCON=((get_PCLK()/1000000-1)<<8); intregs->INTMSK|=BIT_WDT_AC97; //BIT_WDT; intregs->INTSUBMSK |= (1<<13); count=(0xffff-wdtregs->WTCNT)+(intCount*0xffff); return ((unsigned int)count*16/1000000); }
int do_wd (cmd_tbl_t *cmdtp, int flag, int argc,char* const argv[]) { unsigned long reset = 0; unsigned long wtcnt= 0; unsigned long wtdat= 0; unsigned long enable = 0; struct s3c24x0_interrupt * intregs = s3c24x0_get_base_interrupt(); struct s3c24x0_watchdog * dogregs = s3c24x0_get_base_watchdog(); if(argc>1) enable = simple_strtoul(argv[1], NULL, 16); if(argc>2) reset = simple_strtoul(argv[2], NULL, 16); if(argc>3) wtdat = simple_strtoul(argv[3], NULL, 16); if(argc>4) wtcnt = simple_strtoul(argv[4], NULL, 16); printf("watchdog cmd: enable = %ld, reset=%ld, wtdat=0x%lx, wtcnt=0x%lx\r\n", enable, reset ,wtdat, wtcnt); if(enable) { intregs->srcpnd |= ISR_BIT(ISR_WDT_OFT); intregs->intpnd |= ISR_BIT(ISR_WDT_OFT); intregs->subsrcpnd |= (1<<13); //subsrcpnd for wdt intregs->intmsk&=~(ISR_BIT(ISR_WDT_OFT) /*BIT_WDT*/); intregs->intsubmsk&= ~(1<<13); dogregs->wtdat = wtdat; dogregs->wtcnt = wtcnt; if(reset) dogregs->wtcon |=(1<<0); dogregs->wtcon |= 0xff00; dogregs->wtcon |=(1<<5)|(1<<2); } else { dogregs->wtcon &=~(1<<5); intregs->srcpnd |= ISR_BIT(ISR_WDT_OFT); intregs->intpnd |= ISR_BIT(ISR_WDT_OFT); intregs->subsrcpnd |= (1<<13); //subsrcpnd for wdt intregs->intmsk|=ISR_BIT(ISR_WDT_OFT); /*BIT_WDT*/ intregs->intsubmsk|= (1<<13); } return 0; }
/* * reset the cpu by setting up the watchdog timer and let him time out */ void reset_cpu(ulong ignored) { struct s3c24x0_watchdog *watchdog; watchdog = s3c24x0_get_base_watchdog(); /* Disable watchdog */ writel(0x0000, &watchdog->wtcon); /* Initialize watchdog timer count register */ writel(0x0001, &watchdog->wtcnt); /* Enable watchdog timer; assert reset at timer timeout */ writel(0x0021, &watchdog->wtcon); while (1) /* loop forever and wait for reset to happen */; /*NOTREACHED*/ }