static void exynos4_cpu_prepare(void)
{
void __iomem *inform0, *inform1;
if (trustzone_on()) {
inform0 = S5P_VA_SYSRAM_NS + 0x8;
inform1 = S5P_VA_SYSRAM_NS + 0xC;
} else {
inform0 = S5P_INFORM0;
inform1 = S5P_INFORM1;
}
if (exynos4_sleep_gpio_set)
exynos4_sleep_gpio_set();
/* Set value of power down register for sleep mode */
exynos4_sys_powerdown_conf(SYS_SLEEP);
__raw_writel(S5P_CHECK_SLEEP, inform1);
/* ensure at least INFORM0 has the resume address */
__raw_writel(virt_to_phys(s3c_cpu_resume), inform0);
/* Before enter central sequence mode, clock src register have to set */
s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc));
if (soc_is_exynos4210())
s3c_pm_do_restore_core(exynos4210_set_clksrc, ARRAY_SIZE(exynos4210_set_clksrc));
}
static void exynos_pm_resume(void)
{
u32 cpuid = read_cpuid_part();
if (exynos_pm_central_resume())
goto early_wakeup;
/* For release retention */
exynos_pm_release_retention();
if (pm_data->extra_save)
s3c_pm_do_restore_core(pm_data->extra_save,
pm_data->num_extra_save);
s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
if (cpuid == ARM_CPU_PART_CORTEX_A9)
scu_enable(S5P_VA_SCU);
if (call_firmware_op(resume) == -ENOSYS
&& cpuid == ARM_CPU_PART_CORTEX_A9)
exynos_cpu_restore_register();
early_wakeup:
/* Clear SLEEP mode set in INFORM1 */
pmu_raw_writel(0x0, S5P_INFORM1);
exynos_set_delayed_reset_assertion(true);
}
static void exynos4_cpu_prepare(void)
{
if (exynos4_sleep_gpio_table_set)
exynos4_sleep_gpio_table_set();
/* Set value of power down register for sleep mode */
exynos4_sys_powerdown_conf(SYS_SLEEP);
__raw_writel(S5P_CHECK_SLEEP, REG_INFORM1);
/* ensure at least INFORM0 has the resume address */
__raw_writel(virt_to_phys(s3c_cpu_resume), REG_INFORM0);
/* Before enter central sequence mode, clock src register have to set */
#ifdef CONFIG_CACHE_L2X0
/* Disable the full line of zero */
disable_cache_foz();
#endif
s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc));
if (soc_is_exynos4210())
s3c_pm_do_restore_core(exynos4210_set_clksrc, ARRAY_SIZE(exynos4210_set_clksrc));
}
static int s5pv310_pm_resume(struct sys_device *dev)
{
unsigned int tmp;
/* check either sleep wakeup or early wake */
tmp = __raw_readl(S5P_WAKEUP_STAT);
/* clear for next wakeup */
__raw_writel(0x0, S5P_WAKEUP_STAT);
if (tmp & (0x1 << 31)) {
printk(KERN_DEBUG "Wakeup from sleep, 0x%08x\n", tmp);
/* For release retention */
#ifdef CONFIG_CPU_S5PV310_EVT1
__raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
#endif
__raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
__raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
__raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
__raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
__raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
__raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
s3c_pm_do_restore_core(s5pv310_core_save,
ARRAY_SIZE(s5pv310_core_save));
#ifndef CONFIG_CPU_S5PV310_EVT1
tmp = __raw_readl(S5PV310_INT_CSTAT);
tmp |= (S5PV310_INT_TICK_EN | S5PV310_INT_EN);
__raw_writel(tmp, S5PV310_INT_CSTAT);
#endif
/* Clear External Interrupt Pending */
#if 0
/* Do not clear external interrupt: we lost it */
__raw_writel(0xFFFFFFFF, S5P_EINT_PEND(0));
__raw_writel(0xFFFFFFFF, S5P_EINT_PEND(1));
__raw_writel(0xFFFFFFFF, S5P_EINT_PEND(2));
__raw_writel(0xFFFFFFFF, S5P_EINT_PEND(3));
#endif
s5pv310_scu_enable(S5P_VA_SCU);
#ifdef CONFIG_CACHE_L2X0
s5p_l2x0_cache_init();
#endif
} else {
printk(KERN_DEBUG "Early_wake up!. 0x%08x\n", tmp);
s3c_pm_do_restore_core(s5pv310_core_save,
ARRAY_SIZE(s5pv310_core_save));
}
return 0;
}
void s5pv310_cpu_suspend(void)
{
unsigned long tmp;
/*
* Before enter central sequence mode, clock src register have to set
*/
s3c_pm_do_restore_core(s5pv310_set_clksrc,
ARRAY_SIZE(s5pv310_set_clksrc));
#ifndef CONFIG_CPU_S5PV310_EVT1
/*
* Setting PMU spare 1 register to inform wakeup from sleep mode
*/
tmp = __raw_readl(S5P_PMU_SPARE1);
tmp |= ((1 << 31) | (1 << 0) | (1 << 4));
__raw_writel(tmp, S5P_PMU_SPARE1);
#endif
/*
* Setting Central Sequence Register for power down mode
*/
tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
tmp &= ~(S5P_CENTRAL_LOWPWR_CFG);
__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
/* issue the standby signal into the pm unit. */
cpu_do_idle();
tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
tmp |= (S5P_CENTRAL_LOWPWR_CFG);
__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
}
static int exynos3_pd_lcd0_clk_enable_on(struct exynos_pm_domain *domain)
{
unsigned int tmp;
DEBUG_PRINT_INFO("%s pre power on\n", "LCD");
s3c_pm_do_restore_core(exynos_pd_lcd0_clk_save,
ARRAY_SIZE(exynos_pd_lcd0_clk_save));
tmp = __raw_readl(EXYNOS3_CLKSRC_MASK_LCD);
tmp |= ((0x1 << 12)|(0x1));
__raw_writel(tmp, EXYNOS3_CLKSRC_MASK_LCD);
tmp = __raw_readl(EXYNOS3_CLKGATE_BUS_LCD);
tmp |= ((0x7F << 14)|(0x3 << 9)|(0x1F << 3)|(0x1));
__raw_writel(tmp, EXYNOS3_CLKGATE_BUS_LCD);
tmp = __raw_readl(EXYNOS3_CLKGATE_SCLK_LCD);
tmp |= ((0x3 << 3)|(0x3));
__raw_writel(tmp, EXYNOS3_CLKGATE_SCLK_LCD);
tmp = __raw_readl(EXYNOS3_CLKGATE_IP_LCD);
tmp |= ((0x3F << 2)|(0x1));
__raw_writel(tmp, EXYNOS3_CLKGATE_IP_LCD);
return 0;
}
static void exynos5_pm_prepare(void)
{
unsigned int tmp;
if (exynos5_sleep_gpio_table_set)
exynos5_sleep_gpio_table_set();
if (samsung_rev() < EXYNOS5250_REV_1_0) {
/* Disable USE_RETENTION of JPEG_MEM_OPTION */
tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION);
tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
__raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
}
if (samsung_rev() >= EXYNOS5250_REV_1_0) {
tmp = __raw_readl(EXYNOS5_ARM_L2_OPTION);
tmp &= ~(1 << 4);
__raw_writel(tmp, EXYNOS5_ARM_L2_OPTION);
}
/* Set value of power down register for sleep mode */
exynos5_sys_powerdown_conf(SYS_SLEEP);
__raw_writel(S5P_CHECK_SLEEP, REG_INFORM1);
/* ensure at least INFORM0 has the resume address */
__raw_writel(virt_to_phys(s3c_cpu_resume), REG_INFORM0);
if (exynos4_is_c2c_use()) {
tmp = __raw_readl(EXYNOS5_INTRAM_MEM_OPTION);
tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
__raw_writel(tmp, EXYNOS5_INTRAM_MEM_OPTION);
}
s3c_pm_do_restore_core(exynos5_set_clksrc, ARRAY_SIZE(exynos5_set_clksrc));
}
static int exynos3_pd_cam_clk_enable_on(struct exynos_pm_domain *domain)
{
unsigned int tmp;
DEBUG_PRINT_INFO("%s pre power on\n", "CAM");
s3c_pm_do_restore_core(exynos_pd_cam_clk_save,
ARRAY_SIZE(exynos_pd_cam_clk_save));
tmp = __raw_readl(EXYNOS3_CLKSRC_MASK_CAM);
tmp |= ((0x1 << 20)|(0x1));
__raw_writel(tmp, EXYNOS3_CLKSRC_MASK_CAM);
tmp = __raw_readl(EXYNOS3_CLKGATE_BUS_CAM0);
tmp |= ((0x3 << 29)|(0x1 << 27)|(0xF << 22)|(0x7 << 18)|(0x3 << 14)|(0x7 << 10)|(0xF << 5)|(0x7));
__raw_writel(tmp, EXYNOS3_CLKGATE_BUS_CAM0);
tmp = __raw_readl(EXYNOS3_CLKGATE_BUS_CAM1);
tmp |= ((0xF << 10)|(0x7));
__raw_writel(tmp, EXYNOS3_CLKGATE_BUS_CAM1);
tmp = __raw_readl(EXYNOS3_CLKGATE_SCLK_CAM);
tmp |= (0x1 << 8);
__raw_writel(tmp, EXYNOS3_CLKGATE_SCLK_CAM);
tmp = __raw_readl(EXYNOS3_CLKGATE_IP_CAM);
tmp |= ((0xF << 16)|(0xF << 11)|(0xF << 6)|(0x7));
__raw_writel(tmp, EXYNOS3_CLKGATE_IP_CAM);
return 0;
}
void s5pv310_cpu_suspend(void)
{
unsigned long tmp;
/* emmc power off delay
* 0x10020988 => 0: 300ms, 1: 6ms
*/
__raw_writel(1, S5P_PMU(0x0988));
/*
* Before enter central sequence mode, clock src register have to set
*/
s3c_pm_do_restore_core(s5pv310_set_clksrc,
ARRAY_SIZE(s5pv310_set_clksrc));
/*
* Setting Central Sequence Register for power down mode
*/
tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
tmp &= ~(S5P_CENTRAL_LOWPWR_CFG);
__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
/* issue the standby signal into the pm unit. */
cpu_do_idle();
tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
tmp |= (S5P_CENTRAL_LOWPWR_CFG);
__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
}
void s3c_pm_restore_core(void)
{
s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
s3c_pm_do_restore(sromc_save, ARRAY_SIZE(sromc_save));
s3c_pm_do_restore(gpio_save_ext, ARRAY_SIZE(gpio_save_ext));
s3c_pm_do_restore(gpio_save_gpio_int, ARRAY_SIZE(gpio_save_gpio_int));
s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
}
static void exynos4210_clock_resume(void)
{
unsigned int tmp;
s3c_pm_do_restore_core(exynos4210_epll_save, ARRAY_SIZE(exynos4210_epll_save));
s3c_pm_do_restore_core(exynos4210_vpll_save, ARRAY_SIZE(exynos4210_vpll_save));
/* waiting epll & vpll locking time */
do {
tmp = __raw_readl(EXYNOS4_EPLL_CON0);
} while (!(tmp & 0x1 << EXYNOS4_EPLLCON0_LOCKED_SHIFT));
do {
tmp = __raw_readl(EXYNOS4_VPLL_CON0);
} while (!(tmp & 0x1 << EXYNOS4_VPLLCON0_LOCKED_SHIFT));
s3c_pm_do_restore_core(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
}
static void s5pv310_cpu_prepare(void)
{
s3c_pm_do_save(s5pv310_core_save, ARRAY_SIZE(s5pv310_core_save));
/* Set value of power down register for sleep mode */
s3c_pm_do_restore_core(s5pv310_sleep, ARRAY_SIZE(s5pv310_sleep));
__raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
/* ensure at least INFORM0 has the resume address */
__raw_writel(virt_to_phys(s3c_cpu_resume), S5P_INFORM0);
}
static void exynos4212_clock_resume(void)
{
unsigned int tmp;
s3c_pm_do_restore_core(exynos4212_vpll_save, ARRAY_SIZE(exynos4212_vpll_save));
#if (defined(CONFIG_MACH_M0) && defined(CONFIG_TARGET_LOCALE_EUR)) || \
((defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_M0)) && \
defined(CONFIG_TARGET_LOCALE_KOR))
s3c_pm_do_restore_core(exynos4212_epll_save, ARRAY_SIZE(exynos4212_epll_save));
#endif
/* waiting epll & vpll locking time */
do {
tmp = __raw_readl(EXYNOS4_EPLL_CON0);
} while (!(tmp & 0x1 << EXYNOS4_EPLLCON0_LOCKED_SHIFT));
do {
tmp = __raw_readl(EXYNOS4_VPLL_CON0);
} while (!(tmp & 0x1 << EXYNOS4_VPLLCON0_LOCKED_SHIFT));
s3c_pm_do_restore_core(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
}
static int s5pv310_pm_resume(struct sys_device *dev)
{
unsigned int tmp;
/* check either sleep wakeup or early wake */
tmp = __raw_readl(S5P_WAKEUP_STAT);
/* clear for next wakeup */
__raw_writel(0x0, S5P_WAKEUP_STAT);
if (tmp & (0x1 << 31)) {
printk(KERN_DEBUG "Wakeup from sleep, 0x%08x\n", tmp);
/* For release retention */
__raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
__raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
__raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
__raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
__raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
__raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
__raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
s3c_pm_do_restore_core(s5pv310_core_save,
ARRAY_SIZE(s5pv310_core_save));
s5pv310_scu_enable(S5P_VA_SCU);
#ifdef CONFIG_CACHE_L2X0
s5p_l2x0_cache_init();
#endif
} else {
printk(KERN_DEBUG "Early_wake up!. 0x%08x\n", tmp);
s3c_pm_do_restore_core(s5pv310_core_save,
ARRAY_SIZE(s5pv310_core_save));
}
return 0;
}
static int exynos3_pd_isp_clk_enable_on(struct exynos_pm_domain *domain)
{
unsigned int tmp;
DEBUG_PRINT_INFO("%s pre power on : restore clock and masking\n", "ISP");
s3c_pm_do_restore_core(exynos_pd_isp_clk_save,
ARRAY_SIZE(exynos_pd_isp_clk_save));
tmp = __raw_readl(EXYNOS3_CLKSRC_MASK_ISP);
tmp |= ((0x1 << 12)|(0x1 << 8)|(0x1 << 4));
__raw_writel(tmp, EXYNOS3_CLKSRC_MASK_ISP);
tmp = __raw_readl(EXYNOS3_CLKGATE_SCLK_TOP_ISP);
tmp |= (0xF << 1);
__raw_writel(tmp, EXYNOS3_CLKGATE_SCLK_TOP_ISP);
return 0;
}
static int exynos3_pd_g3d_clk_enable_on(struct exynos_pm_domain *domain)
{
unsigned int tmp;
DEBUG_PRINT_INFO("%s pre power on\n", "G3D");
s3c_pm_do_restore_core(exynos_pd_g3d_clk_save,
ARRAY_SIZE(exynos_pd_g3d_clk_save));
tmp = __raw_readl(EXYNOS3_CLKGATE_BUS_G3D);
tmp |= ((0x1 << 18)|(0x1 << 16)|(0x7 << 3));
__raw_writel(tmp, EXYNOS3_CLKGATE_BUS_G3D);
tmp = __raw_readl(EXYNOS3_CLKGATE_IP_G3D);
tmp |= 0xF;
__raw_writel(tmp, EXYNOS3_CLKGATE_IP_G3D);
return 0;
}
static void exynos5420_pm_resume(void)
{
unsigned long tmp;
/* Restore the CPU0 low power state register */
tmp = pmu_raw_readl(EXYNOS5_ARM_CORE0_SYS_PWR_REG);
pmu_raw_writel(tmp | S5P_CORE_LOCAL_PWR_EN,
EXYNOS5_ARM_CORE0_SYS_PWR_REG);
/* Restore the sysram cpu state register */
__raw_writel(exynos5420_cpu_state,
sysram_base_addr + EXYNOS5420_CPU_STATE);
pmu_raw_writel(EXYNOS5420_USE_STANDBY_WFI_ALL,
S5P_CENTRAL_SEQ_OPTION);
if (exynos_pm_central_resume())
goto early_wakeup;
/* For release retention */
exynos_pm_release_retention();
pmu_raw_writel(exynos_pmu_spare3, S5P_PMU_SPARE3);
s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
early_wakeup:
tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1);
tmp &= ~EXYNOS5420_UFS;
pmu_raw_writel(tmp, EXYNOS5420_SFR_AXI_CGDIS1);
tmp = pmu_raw_readl(EXYNOS5420_FSYS2_OPTION);
tmp &= ~EXYNOS5420_EMULATION;
pmu_raw_writel(tmp, EXYNOS5420_FSYS2_OPTION);
tmp = pmu_raw_readl(EXYNOS5420_PSGEN_OPTION);
tmp &= ~EXYNOS5420_EMULATION;
pmu_raw_writel(tmp, EXYNOS5420_PSGEN_OPTION);
/* Clear SLEEP mode set in INFORM1 */
pmu_raw_writel(0x0, S5P_INFORM1);
}
static int exynos3_pd_mfc_clk_enable_on(struct exynos_pm_domain *domain)
{
unsigned int tmp;
DEBUG_PRINT_INFO("%s pre power on\n", "MFC");
s3c_pm_do_restore_core(exynos_pd_mfc_clk_save,
ARRAY_SIZE(exynos_pd_mfc_clk_save));
tmp = __raw_readl(EXYNOS3_CLKGATE_BUS_MFC);
tmp |= ((0x1 << 19)|(0x7 << 15)|(0x1 << 6)|(0x1 << 4)|(0x3 << 1));
__raw_writel(tmp, EXYNOS3_CLKGATE_BUS_MFC);
tmp = __raw_readl(EXYNOS3_CLKGATE_IP_MFC);
tmp |= ((0x1 << 5)|(0x1 << 3)|(0x3));
__raw_writel(tmp, EXYNOS3_CLKGATE_IP_MFC);
return 0;
}
static void exynos4_pm_resume(void)
{
unsigned long tmp;
void __iomem *inform1;
/* If PMU failed while entering sleep mode, WFI will be
* ignored by PMU and then exiting cpu_do_idle().
* S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
* in this situation.
*/
tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
tmp |= S5P_CENTRAL_LOWPWR_CFG;
__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
/* No need to perform below restore code */
pr_info("%s: early_wakeup\n", __func__);
goto early_wakeup;
}
/* For release retention */
__raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
__raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
__raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
__raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
__raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
__raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
__raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
s3c_pm_do_restore(exynos4_regs_save, ARRAY_SIZE(exynos4_regs_save));
if (soc_is_exynos4210())
s3c_pm_do_restore(exynos4210_regs_save,
ARRAY_SIZE(exynos4210_regs_save));
else
s3c_pm_do_restore(exynos4x12_regs_save,
ARRAY_SIZE(exynos4x12_regs_save));
if (!exynos4_is_c2c_use())
s3c_pm_do_restore_core(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
else {
if (!soc_is_exynos4210()) {
/* Gating CLK_SSS */
tmp = __raw_readl(EXYNOS4_CLKGATE_IP_DMC);
tmp &= ~(0x1 << 4);
__raw_writel(tmp, EXYNOS4_CLKGATE_IP_DMC);
}
}
tmp = __raw_readl(S5P_WAKEUP_STAT);
if (WARN_ON(!tmp) && soc_is_exynos4412()) {
__raw_writel(__raw_readl(S5P_EINT_PEND(0)), S5P_EINT_PEND(0));
__raw_writel(__raw_readl(S5P_EINT_PEND(1)), S5P_EINT_PEND(1));
__raw_writel(__raw_readl(S5P_EINT_PEND(2)), S5P_EINT_PEND(2));
__raw_writel(__raw_readl(S5P_EINT_PEND(3)), S5P_EINT_PEND(3));
__raw_writel(0x01010001, S5P_ARM_CORE_OPTION(0));
__raw_writel(0x00000001, S5P_ARM_CORE_OPTION(1));
__raw_writel(0x00000001, S5P_ARM_CORE_OPTION(2));
__raw_writel(0x00000001, S5P_ARM_CORE_OPTION(3));
}
#ifdef CONFIG_HAVE_ARM_SCU
scu_enable(S5P_VA_SCU);
#endif
#ifdef CONFIG_CACHE_L2X0
if (trustzone_on()) {
/*
* Restore for Outer cache
*/
exynos_smc(SMC_CMD_L2X0SETUP1, exynos4_l2cc_save[0].val,
exynos4_l2cc_save[1].val,
exynos4_l2cc_save[2].val);
exynos_smc(SMC_CMD_L2X0SETUP2,
L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
0x7C470001, 0xC200FFFF);
exynos_smc(SMC_CMD_L2X0INVALL, 0, 0, 0);
exynos_smc(SMC_CMD_L2X0CTRL, 1, 0, 0);
} else {
s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
outer_inv_all();
/* enable L2X0*/
writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL);
}
#endif
early_wakeup:
if (!soc_is_exynos4210())
exynos4_reset_assert_ctrl(1);
#ifdef CONFIG_CACHE_L2X0
/* Enable the full line of zero */
enable_cache_foz();
#endif
if (trustzone_on()) {
inform1 = S5P_VA_SYSRAM_NS + 0xC;
} else {
inform1 = S5P_INFORM1;
}
/* Clear Check mode */
__raw_writel(0x0, inform1);
return;
}
static void exynos5_pm_resume(void)
{
unsigned long tmp, srctmp;
u32 timeout;
/* If PMU failed while entering sleep mode, WFI will be
* ignored by PMU and then exiting cpu_do_idle().
* EXYNOS5_CENTRAL_SEQ_CONFIGURATION bit will not be set
* automatically in this situation.
*/
tmp = __raw_readl(EXYNOS5_CENTRAL_SEQ_CONFIGURATION);
if (!(tmp & EXYNOS5_CENTRAL_LOWPWR_CFG)) {
tmp |= EXYNOS5_CENTRAL_LOWPWR_CFG;
__raw_writel(tmp, EXYNOS5_CENTRAL_SEQ_CONFIGURATION);
/* No need to perform below restore code */
goto early_wakeup;
}
if (isp_pwr_off) {
srctmp = __raw_readl(EXYNOS5_CLKSRC_TOP3);
/*
* To ISP power domain off,
* first, ISP_ARM power domain be off.
*/
if (!(__raw_readl(EXYNOS5_ISP_ARM_STATUS) & 0x1)) {
/* Disable ISP_ARM */
timeout = __raw_readl(EXYNOS5_ISP_ARM_OPTION);
timeout &= ~EXYNOS5_ISP_ARM_ENABLE;
__raw_writel(timeout, EXYNOS5_ISP_ARM_OPTION);
/* ISP_ARM power off */
__raw_writel(0x0, EXYNOS5_ISP_ARM_CONFIGURATION);
timeout = 1000;
while (__raw_readl(EXYNOS5_ISP_ARM_STATUS) & 0x1) {
if (timeout == 0) {
printk(KERN_ERR "ISP_ARM power domain can not off\n");
return;
}
timeout--;
udelay(1);
}
/* CMU_RESET_ISP_ARM off */
__raw_writel(0x0, EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG);
}
__raw_writel(0x0, EXYNOS5_ISP_CONFIGURATION);
/* Wait max 1ms */
timeout = 1000;
while (__raw_readl(EXYNOS5_ISP_CONFIGURATION + 0x4) & S5P_INT_LOCAL_PWR_EN) {
if (timeout == 0) {
printk(KERN_ERR "Power domain ISP disable failed.\n");
return;
}
timeout--;
udelay(1);
}
__raw_writel(srctmp, EXYNOS5_CLKSRC_TOP3);
isp_pwr_off = false;
}
/* For release retention */
__raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_MAU_OPTION);
__raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_GPIO_OPTION);
__raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_UART_OPTION);
__raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_MMCA_OPTION);
__raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_MMCB_OPTION);
__raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_EBIA_OPTION);
__raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_EBIB_OPTION);
__raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_SPI_OPTION);
s3c_pm_do_restore_core(exynos5_core_save, ARRAY_SIZE(exynos5_core_save));
early_wakeup:
__raw_writel(0x0, REG_INFORM1);
}
void s3c_pm_restore_core(void)
{
s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
s3c_pm_do_restore(sromc_save, ARRAY_SIZE(sromc_save));
}
static void exynos4_pm_resume(void)
{
unsigned long tmp;
/* If PMU failed while entering sleep mode, WFI will be
* ignored by PMU and then exiting cpu_do_idle().
* S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
* in this situation.
*/
tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
tmp |= S5P_CENTRAL_LOWPWR_CFG;
__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
/* No need to perform below restore code */
goto early_wakeup;
}
/* For release retention */
__raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
__raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
__raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
__raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
__raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
__raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
__raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
if (!exynos4_is_c2c_use())
s3c_pm_do_restore_core(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
else {
if (!soc_is_exynos4210()) {
/* Gating CLK_SSS */
tmp = __raw_readl(EXYNOS4_CLKGATE_IP_DMC);
tmp &= ~(0x1 << 4);
__raw_writel(tmp, EXYNOS4_CLKGATE_IP_DMC);
}
}
exynos4_scu_enable(S5P_VA_SCU);
#ifdef CONFIG_CACHE_L2X0
#ifdef CONFIG_ARM_TRUSTZONE
/*
* Restore for Outer cache
*/
exynos_smc(SMC_CMD_L2X0SETUP1, exynos4_l2cc_save[0].val,
exynos4_l2cc_save[1].val,
exynos4_l2cc_save[2].val);
exynos_smc(SMC_CMD_L2X0SETUP2,
L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
0x7C470001, 0xC200FFFF);
exynos_smc(SMC_CMD_L2X0INVALL, 0, 0, 0);
exynos_smc(SMC_CMD_L2X0CTRL, 1, 0, 0);
#else
s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
outer_inv_all();
/* enable L2X0*/
writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL);
#endif
#endif
early_wakeup:
if (!soc_is_exynos4210())
exynos4_reset_assert_ctrl(1);
#ifdef CONFIG_CACHE_L2X0
/* Enable the full line of zero */
enable_cache_foz();
#endif
/* Clear Check mode */
__raw_writel(0x0, REG_INFORM1);
return;
}
static void exynos4210_clock_resume(void)
{
s3c_pm_do_restore_core(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
}
static void exynos5_pm_resume(void)
{
unsigned long tmp, srctmp;
u32 timeout;
if (samsung_rev() >= EXYNOS5250_REV_1_0)
exynos4_reset_assert_ctrl(1);
/* If PMU failed while entering sleep mode, WFI will be
* ignored by PMU and then exiting cpu_do_idle().
* EXYNOS5_CENTRAL_SEQ_CONFIGURATION bit will not be set
* automatically in this situation.
*/
tmp = __raw_readl(EXYNOS5_CENTRAL_SEQ_CONFIGURATION);
if (!(tmp & EXYNOS5_CENTRAL_LOWPWR_CFG)) {
tmp |= EXYNOS5_CENTRAL_LOWPWR_CFG;
__raw_writel(tmp, EXYNOS5_CENTRAL_SEQ_CONFIGURATION);
/* No need to perform below restore code */
goto early_wakeup;
}
if ((samsung_rev() < EXYNOS5250_REV_1_0) && isp_pwr_off) {
srctmp = __raw_readl(EXYNOS5_CLKSRC_TOP3);
/*
* To ISP power domain off,
* first, ISP_ARM power domain be off.
*/
if ((__raw_readl(EXYNOS5_ISP_ARM_STATUS) & 0x1)) {
/* Disable ISP_ARM */
timeout = __raw_readl(EXYNOS5_ISP_ARM_OPTION);
timeout &= ~EXYNOS5_ISP_ARM_ENABLE;
__raw_writel(timeout, EXYNOS5_ISP_ARM_OPTION);
/* ISP_ARM power off */
__raw_writel(0x0, EXYNOS5_ISP_ARM_CONFIGURATION);
timeout = 1000;
while (__raw_readl(EXYNOS5_ISP_ARM_STATUS) & 0x1) {
if (timeout == 0) {
printk(KERN_ERR "ISP_ARM power domain can not off\n");
return;
}
timeout--;
udelay(1);
}
/* CMU_RESET_ISP_ARM off */
__raw_writel(0x0, EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG);
}
__raw_writel(0x0, EXYNOS5_ISP_CONFIGURATION);
/* Wait max 1ms */
timeout = 1000;
while (__raw_readl(EXYNOS5_ISP_STATUS) & S5P_INT_LOCAL_PWR_EN) {
if (timeout == 0) {
printk(KERN_ERR "Power domain ISP disable failed.\n");
return;
}
timeout--;
udelay(1);
}
__raw_writel(srctmp, EXYNOS5_CLKSRC_TOP3);
isp_pwr_off = false;
}
/* For release retention */
__raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_MAU_OPTION);
__raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_GPIO_OPTION);
__raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_UART_OPTION);
__raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_MMCA_OPTION);
__raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_MMCB_OPTION);
__raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_EBIA_OPTION);
__raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_EBIB_OPTION);
__raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_SPI_OPTION);
/* For Retention release on GPV block */
__raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_OPTION);
/* Disable CPU_nIRQ[0:1] */
tmp = __raw_readl(S5P_VA_COMBINER_BASE + 0x54);
tmp |= ((0x1 << 8) | (0x1 << 0));
__raw_writel(tmp, S5P_VA_COMBINER_BASE + 0x54);
s3c_pm_do_restore(exynos5_regs_save, ARRAY_SIZE(exynos5_regs_save));
s3c_pm_do_restore_core(exynos5_core_save, ARRAY_SIZE(exynos5_core_save));
#ifdef CONFIG_EXYNOS5_SETUP_BTS
if (soc_is_exynos5250())
exynos5250_setup_bts();
#endif
early_wakeup:
__raw_writel(0x0, REG_INFORM1);
}
void s3c2410wdt_restore(void)
{
s3c_pm_do_restore_core(wdt_save, ARRAY_SIZE(wdt_save));
}
static void exynos5_asv_resume(void)
{
s3c_pm_do_restore_core(exynos5_abb_save,
ARRAY_SIZE(exynos5_abb_save));
}
static void exynos4_pm_resume(void)
{
unsigned long tmp;
/* If PMU failed while entering sleep mode, WFI will be
* ignored by PMU and then exiting cpu_do_idle().
* S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
* in this situation.
*/
tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
tmp |= S5P_CENTRAL_LOWPWR_CFG;
__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
/* No need to perform below restore code */
pr_info("%s: early_wakeup\n", __func__);
goto early_wakeup;
}
/* For release retention */
__raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
__raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
__raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
__raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
__raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
__raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
__raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
s3c_pm_do_restore(exynos4_regs_save, ARRAY_SIZE(exynos4_regs_save));
if (soc_is_exynos4210())
s3c_pm_do_restore(exynos4210_regs_save,
ARRAY_SIZE(exynos4210_regs_save));
else
s3c_pm_do_restore(exynos4x12_regs_save,
ARRAY_SIZE(exynos4x12_regs_save));
#if defined(CONFIG_MACH_M0_CTC)
{
if (max7693_muic_cp_usb_state()) {
if (system_rev < 11) {
gpio_direction_output(GPIO_USB_BOOT_EN, 1);
} else if (system_rev == 11) {
gpio_direction_output(GPIO_USB_BOOT_EN, 1);
gpio_direction_output(GPIO_USB_BOOT_EN_REV06, 1);
} else {
gpio_direction_output(GPIO_USB_BOOT_EN_REV06, 1);
}
}
}
#endif
CHECK_POINT;
if (!exynos4_is_c2c_use())
s3c_pm_do_restore_core(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
else {
if (!soc_is_exynos4210()) {
/* Gating CLK_SSS */
tmp = __raw_readl(EXYNOS4_CLKGATE_IP_DMC);
tmp &= ~(0x1 << 4);
__raw_writel(tmp, EXYNOS4_CLKGATE_IP_DMC);
}
}
/* For the suspend-again to check the value */
s3c_suspend_wakeup_stat = __raw_readl(S5P_WAKEUP_STAT);
CHECK_POINT;
scu_enable(S5P_VA_SCU);
CHECK_POINT;
#ifdef CONFIG_CACHE_L2X0
#ifdef CONFIG_ARM_TRUSTZONE
/*
* Restore for Outer cache
*/
exynos_smc(SMC_CMD_L2X0SETUP1, exynos4_l2cc_save[0].val,
exynos4_l2cc_save[1].val,
exynos4_l2cc_save[2].val);
CHECK_POINT;
exynos_smc(SMC_CMD_L2X0SETUP2,
L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
0x7C470001, 0xC200FFFF);
CHECK_POINT;
exynos_smc(SMC_CMD_L2X0INVALL, 0, 0, 0);
CHECK_POINT;
exynos_smc(SMC_CMD_L2X0CTRL, 1, 0, 0);
#else
s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
outer_inv_all();
/* enable L2X0*/
writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL);
#endif
/* Enable the full line of zero */
enable_cache_foz();
#endif
CHECK_POINT;
early_wakeup:
if (!soc_is_exynos4210())
exynos4_reset_assert_ctrl(1);
CHECK_POINT;
/* Clear Check mode */
__raw_writel(0x0, REG_INFORM1);
return;
}
