void c_main(void) {
sark_cpu_state(CPU_STATE_RUN);
// Register each of the components
register_connection_generators();
register_param_generators();
// Get the addresses of the regions
log_info("Starting To Build Delays");
address_t core_address = data_specification_get_data_address();
address_t delay_params_address = data_specification_get_region(
DELAY_PARAMS, core_address);
address_t params_address = data_specification_get_region(
EXPANDER_REGION, core_address);
log_info("\tReading SDRAM delay params at 0x%08x,"
" expander params at 0x%08x",
delay_params_address, params_address);
// Run the expander
if (!read_sdram_data(
(address_t) delay_params_address, (address_t) params_address)) {
log_info("!!! Error reading SDRAM data !!!");
rt_error(RTE_ABORT);
}
log_info("Finished On Machine Delays!");
}
uint spin1_start (sync_bool sync)
{
sark_cpu_state (CPU_STATE_RUN);
// Initialise hardware
configure_communications_controller();
configure_dma_controller();
configure_timer1 (timer_tick);
configure_vic();
#if (API_WARN == TRUE) || (API_DIAGNOSTICS == TRUE)
warnings = NO_ERROR;
dfull = 0;
fullq = 0;
pfull = 0;
#if USE_WRITE_BUFFER == TRUE
wberrors = 0;
#endif
#endif
// synchronise with other application cores
if (sync == SYNC_WAIT)
event_wait ();
// initialise counter and ticks for simulation
// 32-bit, periodic counter, interrupts enabled
if (timer_tick)
tc[T1_CONTROL] = 0xe2;
ticks = 0;
run = 1;
// simulate!
dispatch ();
// simulation finished - clean up before returning to c_main
clean_up ();
// re-enable interrupts for sark
// only CPU_INT enabled in the VIC
spin1_int_enable ();
// provide diagnostics data to application
#if (API_DIAGNOSTICS == TRUE)
diagnostics.exit_code = exit_val;
diagnostics.warnings = warnings;
diagnostics.total_mc_packets = rtr[RTR_DGC0] + rtr[RTR_DGC1];
diagnostics.dumped_mc_packets = rtr[RTR_DGC8];
diagnostics.discarded_mc_packets = thrown;
diagnostics.dma_transfers = dma_id - 1;
diagnostics.dma_bursts = dma[DMA_STAT0];
diagnostics.dma_queue_full = dfull;
diagnostics.task_queue_full = fullq;
diagnostics.tx_packet_queue_full = pfull;
#if USE_WRITE_BUFFER == TRUE
diagnostics.writeBack_errors = wberrors;
#endif
#endif
// report problems if requested!
#if (API_DEBUG == TRUE) || (API_WARN == TRUE)
// avoid sending output at the same time as other chips!
io_delay (10000 * my_chip);
#if API_DEBUG == TRUE // report debug information
report_debug();
#endif
#if API_WARN == TRUE // report warnings
report_warns ();
#endif
#endif
return exit_val;
}
