static void saturn_instruction_81(saturn_state *cpustate) { int reg, adr; switch(reg=READ_OP(cpustate)) { case 0: case 1: case 2: case 3: saturn_rotate_nibble_left_w(cpustate, A+reg); break; // aslc w case 4: case 5: case 6: case 7: saturn_rotate_nibble_right_w(cpustate, A+(reg&3)); break; // asrc w case 8: switch(adr=READ_OP(cpustate)) { case 0: switch (reg=READ_OP(cpustate)) { case 0: case 1: case 2: case 3: saturn_add_const(cpustate, A+reg, cpustate->p, 1, READ_OP(cpustate)+1); break; case 8: case 9: case 0xa: case 0xb: saturn_sub_const(cpustate, A+(reg&3), cpustate->p, 1, READ_OP(cpustate)+1); break; default: saturn_invalid5( cpustate, 8, 1, 8, adr, reg ); break; } break; case 1: switch (reg=READ_OP(cpustate)) { case 0: case 1: case 2: case 3: saturn_add_const(cpustate, A+reg, 0, cpustate->p+1, READ_OP(cpustate)+1); break; case 8: case 9: case 0xa: case 0xb: saturn_sub_const(cpustate, A+(reg&3), 0, cpustate->p+1, READ_OP(cpustate)+1); break; default: saturn_invalid5( cpustate, 8, 1, 8, adr, reg ); break; } break; case 2: case 3: case 4: case 5: case 6: case 7: case 0xf: switch (reg=READ_OP(cpustate)) { case 0: case 1: case 2: case 3: saturn_add_const(cpustate, A+reg, adr_af_begin[adr], adr_af_count[adr], READ_OP(cpustate)+1); break; case 8: case 9: case 0xa: case 0xb: saturn_sub_const(cpustate, A+(reg&3), adr_af_begin[adr], adr_af_count[adr], READ_OP(cpustate)+1); break; default: saturn_invalid5( cpustate, 8, 1, 8, adr, reg ); break; } break; default: saturn_invalid4( cpustate, 8, 1, 8, adr ); break; } break; case 9: switch(adr=READ_OP(cpustate)) { case 0: switch(reg=READ_OP(cpustate)){ case 0: case 1: case 2: case 3: saturn_shift_right(cpustate, A+reg,cpustate->p,1); break; // asrb p default: saturn_invalid5( cpustate, 8, 1, 9, adr, reg ); break; } break; case 1: switch(reg=READ_OP(cpustate)){ case 0: case 1: case 2: case 3: saturn_shift_right(cpustate, A+reg, 0,cpustate->p+1); break; // asrb wp default: saturn_invalid5( cpustate, 8, 1, 9, adr, reg ); break; } break; case 2: case 3: case 4: case 5: case 6: case 7: case 0xf: switch(reg=READ_OP(cpustate)){ case 0: case 1: case 2: case 3: saturn_shift_right(cpustate, A+reg, adr_af_begin[adr], adr_af_count[adr]); break; // asrb xs default: saturn_invalid5( cpustate, 8, 1, 9, adr, reg ); break; } break; default: saturn_invalid4( cpustate, 8, 1, 9, adr ); break; } break; case 0xa: saturn_instruction_81a(cpustate); break; case 0xb: switch(adr=READ_OP(cpustate)) { case 2: saturn_load_pc(cpustate, A);break; case 3: saturn_load_pc(cpustate, C);break; case 4: saturn_store_pc(cpustate, A);break; case 5: saturn_store_pc(cpustate, C);break; case 6: saturn_exchange_pc(cpustate, A);break; case 7: saturn_exchange_pc(cpustate, C);break; default: saturn_invalid4( cpustate, 8, 1, reg, adr ); break; } break; case 0xc: case 0xd: case 0xe: case 0xf: saturn_shift_right(cpustate, A+(reg&3), BEGIN_W, COUNT_W); break; // asrb w } }
static void saturn_instruction_81(void) { int reg, adr; switch(reg=READ_OP()) { case 0: case 1: case 2: case 3: saturn_rotate_nibble_left_w(A+reg); break; /* aslc w */ case 4: case 5: case 6: case 7: saturn_rotate_nibble_right_w(A+(reg&3)); break; /* asrc w */ case 8: switch(adr=READ_OP()) { case 0: switch (reg=READ_OP()) { case 0: case 1: case 2: case 3: saturn_add_const(A+reg, saturn.p, 1, READ_OP()+1); break; case 8: case 9: case 0xa: case 0xb: saturn_sub_const(A+reg, saturn.p, 1, READ_OP()+1); break; } break; case 1: switch (reg=READ_OP()) { case 0: case 1: case 2: case 3: saturn_add_const(A+reg, 1, saturn.p+1, READ_OP()+1); break; case 8: case 9: case 0xa: case 0xb: saturn_sub_const(A+reg, 1, saturn.p+1, READ_OP()+1); break; } break; case 2: case 3: case 4: case 5: case 6: case 7: case 0xf: switch (reg=READ_OP()) { case 0: case 1: case 2: case 3: saturn_add_const(A+reg, adr_af_begin[adr], adr_af_count[adr], READ_OP()+1); break; case 8: case 9: case 0xa: case 0xb: saturn_sub_const(A+reg, adr_af_begin[adr], adr_af_count[adr], READ_OP()+1); break; } break; } break; case 9: switch(adr=READ_OP()) { case 0: switch(reg=READ_OP()){ case 0: case 1: case 2: case 3: saturn_shift_right(A+reg,saturn.p,1); break; /* asrb p */ } break; case 1: switch(reg=READ_OP()){ case 0: case 1: case 2: case 3: saturn_shift_right(A+reg, 0,saturn.p+1); break; /* asrb wp */ } break; case 2: /*case 3:*/ case 4: case 5: case 6:/* case 7:*/case 0xf: switch(reg=READ_OP()){ case 0: case 1: case 2: case 3: saturn_shift_right(A+reg, adr_af_begin[adr], adr_af_count[adr]); break; /* asrb xs */ } break; } break; case 0xa: saturn_instruction_81a(); break; case 0xb: switch(READ_OP()) { case 2: saturn_load_pc(A);break; case 3: saturn_load_pc(C);break; case 4: saturn_store_pc(A);break; case 5: saturn_store_pc(C);break; case 6: saturn_exchange_pc(A);break; case 7: saturn_exchange_pc(C);break; } break; case 0xc: case 0xd: case 0xe: case 0xf: saturn_shift_right(A+(reg&3), BEGIN_W, COUNT_W); break; /* asrb w */ } }