void mt6575_sleep(u32 timeout, kal_bool en_deep_idle)
{
unsigned int topmisc, pdn0;
printf("enter mt6575_sleep, timeout = %d\n", timeout);
#if MT6575_SC_DEBUG
slp_dump_pm_regs();
#endif
pdn0 = DRV_Reg32(PERI_GLOBALCON_PDN0);
if (get_chip_eco_ver() == CHIP_E1) {
/* power on UART0/1/2/3 to workaround handshake mode issue */
DRV_WriteReg32(PERI_GLOBALCON_PDN0, pdn0 & ~(0xf << 24));
}
/* keep CA9 clock when entering WFI mode in sleep */
topmisc = DRV_Reg32(TOP_MISC);
DRV_WriteReg32(TOP_MISC, topmisc & ~(1U << 0));
if (get_chip_eco_ver() != CHIP_E1) {
if (en_deep_idle) {
DRV_WriteReg32(TOPCKGEN_CON3, DRV_Reg32(TOPCKGEN_CON3) & 0x7FFF);
DRV_WriteReg32(MDPLL_CON0, DRV_Reg32(MDPLL_CON0) | 0x1);
}
}
rtc_writeif_lock();
sc_go_to_sleep(timeout, en_deep_idle);
rtc_writeif_unlock();
if (get_chip_eco_ver() != CHIP_E1) {
if (en_deep_idle) {
DRV_WriteReg32(MDPLL_CON0, DRV_Reg32(MDPLL_CON0) & 0xFFFE);
udelay(20);
DRV_WriteReg32(TOPCKGEN_CON3, DRV_Reg32(TOPCKGEN_CON3) | 0x8000);
}
}
/* restore TOP_MISC (and PERI_GLOBALCON_PDN0) */
DRV_WriteReg32(TOP_MISC, topmisc);
if (get_chip_eco_ver() == CHIP_E1)
DRV_WriteReg32(PERI_GLOBALCON_PDN0, pdn0);
return 0;
}
static int slp_suspend_ops_enter(suspend_state_t state)
{
u32 topmisc;
unsigned int pwrlevel;
/* legacy log */
aee_sram_printk("_Chip_pm_enter\n");
slp_xinfo("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\n");
slp_xinfo("_Chip_pm_enter @@@@@@@@@@@@@@@@@@@@@@\n");
slp_xinfo(" @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\n");
if (slp_dump_gpio)
gpio_dump_regs();
/* keep CA9 clock frequency when WFI to sleep */
topmisc = slp_read32(TOP_MISC);
slp_write32(TOP_MISC, topmisc & ~(1U << 0));
slp_write_sync();
if (slp_dump_regs)
slp_dump_pm_regs();
rtc_disable_writeif();
pwrlevel = slp_pwr_level;
if ((pwrlevel != 0) && (slp_read32(0xf0009024) & 0x8000)) {
slp_xerror("!!! WILL NOT POWER DOWN CPUSYS DUE TO CPU1 ON !!!\n");
pwrlevel = 0;
}
slp_wake_reason = sc_go_to_sleep(pwrlevel);
rtc_enable_writeif();
/* restore TOP_MISC */
slp_write32(TOP_MISC, topmisc);
slp_write_sync();
return 0;
}
