void
ka680_steal_pages()
{
/*
* Get the soft and hard memory error vectors now.
*/
scb_vecalloc(0x54, ka680_softmem, NULL, 0, NULL);
scb_vecalloc(0x60, ka680_hardmem, NULL, 0, NULL);
/* Turn on caches (to speed up execution a bit) */
ka680_cache_enable();
}
void
vsaudio_attach(struct device *parent, struct device *self, void *aux)
{
struct vsbus_attach_args *va = aux;
struct vsaudio_softc *sc = (struct vsaudio_softc *)self;
if (bus_space_map(va->va_iot, va->va_paddr, AM7930_DREG_SIZE << 2, 0,
&sc->sc_bh) != 0) {
printf(": can't map registers\n");
return;
}
sc->sc_bt = va->va_iot;
/*
* Set up glue for MI code early; we use some of it here.
*/
sc->sc_am7930.sc_glue = &vsaudio_glue;
am7930_init(&sc->sc_am7930, AUDIOAMD_POLL_MODE);
scb_vecalloc(va->va_cvec, vsaudio_hwintr, sc, SCB_ISTACK,
&sc->sc_intrcnt);
sc->sc_cvec = va->va_cvec;
evcount_attach(&sc->sc_intrcnt, self->dv_xname, &sc->sc_cvec);
sc->sc_swintr = softintr_establish(IPL_SOFT, &vsaudio_swintr, sc);
printf("\n");
audio_attach_mi(&vsaudio_hw_if, sc, &sc->sc_am7930.sc_dev);
}
void
ka53_conf()
{
char *cpuname;
/* This initialises ISP, avoiding interrupt exceptions */
{volatile int *hej = (void *)mfpr(PR_ISP); *hej = *hej; hej[-1] = hej[-1];}
/* This vector (qbus related?) comes out of nowhere, ignore it for now */
scb_vecalloc(0x0, (void *)nullop, NULL, SCB_ISTACK, NULL);
cpmbx = (struct cpmbx *)vax_map_physmem(0x20140400, 1);
switch((vax_siedata >> 8) & 0xFF) {
case VAX_STYP_50:
cpuname = "KA50";
break;
case VAX_STYP_51:
cpuname = "KA51";
break;
case VAX_STYP_52:
cpuname = "KA52";
break;
case VAX_STYP_53:
cpuname = "KA53";
break;
default:
cpuname = "unknown NVAX";
}
printf("cpu0: %s, ucode rev %d\n", cpuname, vax_cpudata & 0xff);
}
static void
tcbus_intr_establish(device_t dv, void *cookie, int level,
int (*func)(void *), void *arg)
{
struct tcbus_softc * const sc = cookie;
scb_vecalloc(0x51, (void (*)(void *)) func, arg, SCB_ISTACK,
&sc->sc_ev);
}
/*
* hdc_attach() probes for all possible devices
*/
void
hdcattach(device_t parent, device_t self, void *aux)
{
struct vsbus_attach_args * const va = aux;
struct hdcsoftc * const sc = device_private(self);
struct hdc_attach_args ha;
int status, i;
aprint_normal("\n");
sc->sc_dev = self;
/*
* Get interrupt vector, enable instrumentation.
*/
scb_vecalloc(va->va_cvec, hdcintr, sc, SCB_ISTACK, &sc->sc_intrcnt);
evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, NULL,
device_xname(self), "intr");
sc->sc_regs = vax_map_physmem(va->va_paddr, 1);
sc->sc_dmabase = (void *)va->va_dmaaddr;
sc->sc_dmasize = va->va_dmasize;
sc->sc_intbit = va->va_maskno;
rd_dmasize = min(MAXPHYS, sc->sc_dmasize); /* Used in rd_minphys */
sc->sc_vd.vd_go = hdc_qstart;
sc->sc_vd.vd_arg = sc;
/*
* Reset controller.
*/
HDC_WCMD(DKC_CMD_RESET);
DELAY(1000);
status = HDC_RSTAT;
if (status != (DKC_ST_DONE|DKC_TC_SUCCESS)) {
aprint_error_dev(self, "RESET failed, status 0x%x\n", status);
return;
}
bufq_alloc(&sc->sc_q, "disksort", BUFQ_SORT_CYLINDER);
/*
* now probe for all possible hard drives
*/
for (i = 0; i < 4; i++) {
if (i == 2) /* Floppy, needs special handling */
continue;
HDC_WCMD(DKC_CMD_DRSELECT | i);
DELAY(1000);
status = HDC_RSTAT;
ha.ha_drive = i;
if ((status & DKC_ST_TERMCOD) == DKC_TC_SUCCESS)
config_found(self, (void *)&ha, hdcprint);
}
}
/*
* hdc_attach() probes for all possible devices
*/
void
hdcattach(struct device *parent, struct device *self, void *aux)
{
struct vsbus_attach_args *va = aux;
struct hdcsoftc *sc = (void *)self;
struct hdc_attach_args ha;
int status, i;
u = 0; /* !!! - GCC */
printf("\n");
/*
* Get interrupt vector, enable instrumentation.
*/
scb_vecalloc(va->va_cvec, hdcintr, sc, SCB_ISTACK, &sc->sc_intrcnt);
evcount_attach(&sc->sc_intrcnt, self->dv_xname, (void *)va->va_cvec);
sc->sc_regs = vax_map_physmem(va->va_paddr, 1);
sc->sc_dmabase = (caddr_t)va->va_dmaaddr;
sc->sc_dmasize = va->va_dmasize;
sc->sc_intbit = va->va_maskno;
hd_dmasize = min(MAXPHYS, sc->sc_dmasize); /* Used in hd_minphys */
sc->sc_vd.vd_go = hdc_qstart;
sc->sc_vd.vd_arg = sc;
/*
* Reset controller.
*/
HDC_WCMD(DKC_CMD_RESET);
DELAY(1000);
status = HDC_RSTAT;
if (status != (DKC_ST_DONE|DKC_TC_SUCCESS)) {
printf("%s: RESET failed, status 0x%x\n",
sc->sc_dev.dv_xname, status);
return;
}
/*
* now probe for all possible hard drives
*/
for (i = 0; i < 4; i++) {
if (i == 2) /* Floppy, needs special handling */
continue;
HDC_WCMD(DKC_CMD_DRSELECT | i);
DELAY(1000);
status = HDC_RSTAT;
ha.ha_drive = i;
if ((status & DKC_ST_TERMCOD) == DKC_TC_SUCCESS)
config_found(self, (void *)&ha, hdcprint);
}
}
void
ka49_conf()
{
printf("cpu0: KA49\n");
/* Why??? */
{ volatile int *hej = (void *)mfpr(PR_ISP); *hej = *hej; hej[-1] = hej[-1];}
/* This vector shows up during shutdown, ignore it for now. */
scb_vecalloc(0x0, (void *)nullop, NULL, SCB_ISTACK, NULL);
/*
* Setup parameters necessary to read time from clock chip.
*/
clk_adrshift = 1; /* Addressed at long's... */
clk_tweak = 2; /* ...and shift two */
clk_page = (short *)vax_map_physmem(0x25400000, 1);
}
/*
* Attach the found massbuss adapter. Setup its interrupt vectors,
* reset it and go searching for drives on it.
*/
void
mbaattach(device_t parent, device_t self, void *aux)
{
struct mba_softc * const sc = device_private(self);
struct sbi_attach_args * const sa = aux;
struct mba_attach_args ma;
int i, j;
aprint_normal("\n");
sc->sc_dev = self;
sc->sc_iot = sa->sa_iot;
sc->sc_ioh = sa->sa_ioh;
/*
* Set up interrupt vectors for this MBA.
*/
for (i = 0x14; i < 0x18; i++)
scb_vecalloc(vecnum(0, i, sa->sa_nexnum),
mbaintr, sc, SCB_ISTACK, &sc->sc_intrcnt);
evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, NULL,
device_xname(self), "intr");
STAILQ_INIT(&sc->sc_xfers);
MBA_WCSR(MBA_CR, MBACR_INIT); /* Reset adapter */
MBA_WCSR(MBA_CR, MBACR_IE); /* Enable interrupts */
for (i = 0; i < MAXMBADEV; i++) {
sc->sc_state = SC_AUTOCONF;
if ((MBA_RCSR(MUREG(i, MU_DS)) & MBADS_DPR) == 0)
continue;
/* We have a drive, ok. */
ma.ma_unit = i;
ma.ma_type = MBA_RCSR(MUREG(i, MU_DT)) & 0xf1ff;
for (j = 0; mbaunit[j].nr; j++)
if (mbaunit[j].nr == ma.ma_type)
break;
ma.ma_devtyp = mbaunit[j].devtyp;
ma.ma_name = mbaunit[j].name;
ma.ma_iot = sc->sc_iot;
ma.ma_ioh = sc->sc_ioh + MUREG(i, 0);
config_found(sc->sc_dev, &ma, mbaprint);
}
}
/*
* Interface exists: make available by filling in network interface
* record. System will initialize the interface when it is ready
* to accept packets.
*/
void
ze_mainbus_attach(device_t parent, device_t self, void *aux)
{
struct mainbus_attach_args * const ma = aux;
struct ze_softc * const sc = device_private(self);
const struct sgec_data * const sd = ze_find();
const uint32_t *ea;
size_t i;
int error;
sc->sc_dev = self;
/*
* Map in SGEC registers.
*/
sc->sc_dmat = ma->ma_dmat;
sc->sc_iot = ma->ma_iot;
sc->sc_intvec = sd->sd_intvec;
error = bus_space_map(sc->sc_iot, sd->sd_addr, PAGE_SIZE, 0,
&sc->sc_ioh);
if (error) {
aprint_error(": failed to map %#lx: %d\n", sd->sd_addr, error);
return;
}
/*
* Map in, read and release ethernet rom address.
*/
ea = (uint32_t *)vax_map_physmem(sd->sd_rom, 1);
for (i = 0; i < ETHER_ADDR_LEN; i++)
sc->sc_enaddr[i] = (ea[i] >> sd->sd_romshift) & 0377;
vax_unmap_physmem((vaddr_t)ea, 1);
scb_vecalloc(sc->sc_intvec, (void (*)(void *)) sgec_intr, sc,
SCB_ISTACK, &sc->sc_intrcnt);
sgec_attach(sc);
}
/*
* Attach this instance, and then all the sub-devices
*/
static void
asc_vsbus_attach(struct device *parent, struct device *self, void *aux)
{
struct vsbus_attach_args *va = aux;
struct asc_vsbus_softc *asc = (void *)self;
struct ncr53c9x_softc *sc = &asc->sc_ncr53c9x;
int error;
asc_attached = 1;
/*
* Set up glue for MI code early; we use some of it here.
*/
sc->sc_glue = &asc_vsbus_glue;
asc->sc_bst = va->va_iot;
asc->sc_dmat = va->va_dmat;
error = bus_space_map(asc->sc_bst, va->va_paddr - ASC_REG_NCR,
ASC_REG_END, 0, &asc->sc_bsh);
if (error) {
printf(": failed to map registers: error=%d\n", error);
return;
}
error = bus_space_subregion(asc->sc_bst, asc->sc_bsh, ASC_REG_NCR,
ASC_REG_END - ASC_REG_NCR, &asc->sc_ncrh);
if (error) {
printf(": failed to map ncr registers: error=%d\n", error);
return;
}
if (vax_boardtype == VAX_BTYP_46 || vax_boardtype == VAX_BTYP_48) {
error = bus_space_subregion(asc->sc_bst, asc->sc_bsh,
ASC_REG_KA46_ADR, sizeof(u_int32_t), &asc->sc_adrh);
if (error) {
printf(": failed to map adr register: error=%d\n",
error);
return;
}
error = bus_space_subregion(asc->sc_bst, asc->sc_bsh,
ASC_REG_KA46_DIR, sizeof(u_int32_t), &asc->sc_dirh);
if (error) {
printf(": failed to map dir register: error=%d\n",
error);
return;
}
} else {
/* This is a gross and disgusting kludge but it'll
* save a bunch of ugly code. Unlike the VS4000/60,
* the SCSI Address and direction registers are not
* near the SCSI NCR registers and are inside the
* block of general VAXstation registers. So we grab
* them from there and knowing the internals of the
* bus_space implementation, we cast to bus_space_handles.
*/
struct vsbus_softc *vsc = (struct vsbus_softc *) parent;
asc->sc_adrh = (bus_space_handle_t) (vsc->sc_vsregs + ASC_REG_KA49_ADR);
asc->sc_dirh = (bus_space_handle_t) (vsc->sc_vsregs + ASC_REG_KA49_DIR);
#if 0
printf("\n%s: adrh=0x%08lx dirh=0x%08lx", self->dv_xname,
asc->sc_adrh, asc->sc_dirh);
ncr53c9x_debug = NCR_SHOWDMA|NCR_SHOWINTS|NCR_SHOWCMDS|NCR_SHOWPHASE|NCR_SHOWSTART|NCR_SHOWMSGS;
#endif
}
error = bus_dmamap_create(asc->sc_dmat, ASC_MAXXFERSIZE, 1,
ASC_MAXXFERSIZE, 0, BUS_DMA_NOWAIT, &asc->sc_dmamap);
switch (vax_boardtype) {
#if defined(VAX46)
case VAX_BTYP_46:
sc->sc_id = (clk_page[0xbc/2] >> clk_tweak) & 7;
break;
#endif
default:
sc->sc_id = 6; /* XXX need to get this from VMB */
break;
}
sc->sc_freq = ASC_FREQUENCY;
/* gimme MHz */
sc->sc_freq /= 1000000;
scb_vecalloc(va->va_cvec, (void (*)(void *)) ncr53c9x_intr,
&asc->sc_ncr53c9x, SCB_ISTACK, &asc->sc_intrcnt);
asc->sc_cvec = va->va_cvec;
evcount_attach(&asc->sc_intrcnt, self->dv_xname,
(void *)&asc->sc_cvec, &evcount_intr);
/*
* XXX More of this should be in ncr53c9x_attach(), but
* XXX should we really poke around the chip that much in
* XXX the MI code? Think about this more...
*/
/*
* Set up static configuration info.
*/
sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB;
sc->sc_cfg2 = NCRCFG2_SCSI2;
sc->sc_cfg3 = 0;
sc->sc_rev = NCR_VARIANT_NCR53C94;
/*
* XXX minsync and maxxfer _should_ be set up in MI code,
* XXX but it appears to have some dependency on what sort
* XXX of DMA we're hooked up to, etc.
*/
/*
* This is the value used to start sync negotiations
* Note that the NCR register "SYNCTP" is programmed
* in "clocks per byte", and has a minimum value of 4.
* The SCSI period used in negotiation is one-fourth
* of the time (in nanoseconds) needed to transfer one byte.
* Since the chip's clock is given in MHz, we have the following
* formula: 4 * period = (1000 / freq) * 4
*/
sc->sc_minsync = (1000 / sc->sc_freq);
sc->sc_maxxfer = 64 * 1024;
/* Do the common parts of attachment. */
ncr53c9x_attach(sc, &asc_vsbus_ops, &asc_vsbus_dev);
}
void
crlattach(void)
{
scb_vecalloc(0xF0, crlintr, NULL, SCB_ISTACK, &crl_ev);
}
/*
* Move to machdep eventually
*/
void
uba_intr_establish(void *icookie, int vec, void (*ifunc)(void *iarg),
void *iarg, struct evcnt *ev)
{
scb_vecalloc(vec, ifunc, iarg, SCB_ISTACK, ev);
}
