static int
do_decrypt_part(scc_part_cipher_access* acc, uint8_t* local_black,
dma_addr_t black_phys)
{
int status;
uint32_t IV[4];
uint32_t* iv_ptr = (uint32_t*)&(acc->iv);
/* Build the IV */
IV[0] = iv_ptr[0];
IV[1] = iv_ptr[1];
IV[2] = 0;
IV[3] = 0;
/* Copy the black data from user's memory */
status = copy_from_user(local_black, acc->black_address, acc->size_bytes);
if (status == 0) {
/* Perform the black -> red decryption */
acc->scc_status = scc_decrypt_region(acc->virt_address, acc->red_offset,
acc->size_bytes, (void*)black_phys,
IV, SCC_CYPHER_MODE_CBC);
}
return status;
}
fsl_shw_return_t
do_scc_decrypt_region(fsl_shw_uco_t * user_ctx,
void *partition_base, uint32_t offset_bytes,
uint32_t byte_count, const uint8_t * black_data,
uint32_t * IV, fsl_shw_cypher_mode_t cypher_mode)
{
scc_return_t scc_ret;
fsl_shw_return_t retval = FSL_RETURN_ERROR_S;
#ifdef FSL_HAVE_SCC2
#ifdef DIAG_ADAPTOR
uint32_t *owner_32 = (uint32_t *) & (owner_id);
LOG_KDIAG_ARGS
("partition base: %p, offset: %i, count: %i, black data: %p\n",
partition_base, offset_bytes, byte_count, (void *)black_data);
#endif
(void)user_ctx;
/* The SCC2 DMA engine will be reading from the black ram, so we need to
* make sure that the data is pushed out of the cache. Note that the red
* ram is not an issue because it is mapped with the cache disabled.
*/
os_cache_flush_range(black_data, byte_count);
scc_ret =
scc_decrypt_region((uint32_t) partition_base, offset_bytes,
byte_count,
(uint8_t *) __virt_to_phys(black_data), IV,
cypher_mode);
if (scc_ret == SCC_RET_OK) {
retval = FSL_RETURN_OK_S;
} else {
retval = FSL_RETURN_ERROR_S;
}
#else
(void)scc_ret;
#endif /* FSL_HAVE_SCC2 */
return retval;
}