void emu_loop(bool reset) { if (reset) { emu_reset(); } exiting = false; #ifdef __EMSCRIPTEN__ emscripten_set_main_loop(emu_inner_loop, -1, 1); #else while (!exiting) { if (cpu_events & EVENT_RESET) { cpu_events = EVENT_NONE; gui_console_printf("CPU Reset triggered..."); emu_reset(); } if (cpu_events & EVENT_DEBUG_STEP) { cpu_events = EVENT_NONE; debugger(DBG_STEP, 0); } sched_process_pending_events(); if (cycle_count_delta < 0) { cpu_execute(); // execute instructions with available clock cycles } else { QThread::yieldCurrentThread(); } } emu_cleanup(); #endif }
// TODO : Make sure it works with the recent commits. void emu_inner_loop(void) { while (!exiting) { sched_process_pending_events(); if (cpu_events & EVENT_RESET) { gui_console_printf("CPU Reset triggered..."); emu_reset(); } if (cycle_count_delta < 0) { cpu_execute(); // execute instructions with available clock cycles } } }
static void emu_main_loop_inner(void) { if (!emulationPaused) { if (cpuEvents & EVENT_RESET) { gui_console_printf("[CEmu] Calculator reset triggered...\n"); cpu_reset(); cpuEvents &= ~EVENT_RESET; } #ifdef DEBUG_SUPPORT if (!cpu.halted && (cpuEvents & EVENT_DEBUG_STEP)) { cpuEvents &= ~EVENT_DEBUG_STEP; open_debugger(DBG_STEP, 0); } #endif if (!asic.shipModeEnabled) { sched_process_pending_events(); cpu_execute(); } else { gui_emu_sleep(50); } } else { gui_emu_sleep(50); } }
void emu_loop(bool reset) { #if OS_HAS_PAGEFAULT_HANDLER os_exception_frame_t seh_frame = { NULL, NULL }; os_faulthandler_arm(&seh_frame); #endif if(reset) { reset: emu_reset(); } gdbstub_reset(); addr_cache_flush(); flush_translations(); sched_update_next_event(0); exiting = false; // clang segfaults with that, for an iOS build :( #ifndef NO_SETJMP // Workaround for LLVM bug #18974 while(__builtin_setjmp(restart_after_exception)){}; #endif while (!exiting) { sched_process_pending_events(); while (!exiting && cycle_count_delta < 0) { if (cpu_events & EVENT_RESET) { gui_status_printf("Reset"); goto reset; } if (cpu_events & (EVENT_FIQ | EVENT_IRQ)) { // Align PC in case the interrupt occurred immediately after a jump if (arm.cpsr_low28 & 0x20) arm.reg[15] &= ~1; else arm.reg[15] &= ~3; if (cpu_events & EVENT_WAITING) arm.reg[15] += 4; // Skip over wait instruction arm.reg[15] += 4; cpu_exception((cpu_events & EVENT_FIQ) ? EX_FIQ : EX_IRQ); } cpu_events &= ~EVENT_WAITING; if (arm.cpsr_low28 & 0x20) cpu_thumb_loop(); else cpu_arm_loop(); } } #if OS_HAS_PAGEFAULT_HANDLER os_faulthandler_unarm(&seh_frame); #endif }