long int pcl_configure_clocks_osc0(pcl_freq_param_t *param)
{
// Supported main clock sources: PCL_MC_OSC0
// Supported synchronous clocks frequencies if OSC0 is the main clock source:
// (these obviously depend on the OSC0 frequency; we'll take 16MHz as an example)
// 16MHz, 8MHz, 4MHz, 2MHz, 1MHz, 500kHz, 250kHz, 125kHz, 62.5kHz.
// NOTE: by default, this implementation doesn't perform thorough checks on the
// input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.
unsigned long main_clock_freq;
#ifdef AVR32SFW_INPUT_CHECK
// Verify that fCPU >= fPBx
if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f))
return(-1);
#endif
main_clock_freq = param->osc0_f;
#ifdef AVR32SFW_INPUT_CHECK
// Verify that the target frequencies are reachable.
if((param->cpu_f > main_clock_freq) || (param->pba_f > main_clock_freq)
|| (param->pbb_f > main_clock_freq))
return(-1);
#endif
// Configure OSC0 in crystal mode, external crystal with a fcrystal Hz frequency.
scif_configure_osc_crystalmode(SCIF_OSC0, main_clock_freq);
// Enable the OSC0
scif_enable_osc(SCIF_OSC0, param->osc0_startup, true);
return(pcl_configure_synchronous_clocks(PM_CLK_SRC_OSC0, main_clock_freq, param));
}
long int pcl_switch_to_osc(pcl_osc_t osc, unsigned int fcrystal, unsigned int startup)
{
#ifndef AVR32_PM_VERSION_RESETVALUE
// Implementation for UC3A, UC3A3, UC3B parts.
if(PCL_OSC0 == osc)
{
// Configure OSC0 in crystal mode, external crystal with a FOSC0 Hz frequency,
// enable the OSC0, set the main clock source as being OSC0.
pm_switch_to_osc0(&AVR32_PM, fcrystal, startup);
}
else
{
return PCL_NOT_SUPPORTED;
}
#else
// Implementation for UC3C, UC3L parts.
#if AVR32_PM_VERSION_RESETVALUE < 0x400
return PCL_NOT_SUPPORTED;
#else
if(PCL_OSC0 == osc)
{
// Configure OSC0 in crystal mode, external crystal with a fcrystal Hz frequency.
scif_configure_osc_crystalmode(SCIF_OSC0, fcrystal);
// Enable the OSC0
scif_enable_osc(SCIF_OSC0, startup, true);
// Set the Flash wait state and the speed read mode (depending on the target CPU frequency).
#if (( defined (__GNUC__) && ( defined (__AVR32_UC3L016__) || defined (__AVR32_UC3L032__) || defined (__AVR32_UC3L064__))) \
||(defined (__ICCAVR32__) && (defined (__AT32UC3L016__) || defined (__AT32UC3L032__) || defined (__AT32UC3L064__) )))
flashcdw_set_flash_waitstate_and_readmode(fcrystal);
#elif ( defined (__GNUC__) && ( defined (__AVR32_UC3C064C__) || defined (__AVR32_UC3C0128C__) || defined (__AVR32_UC3C0256C__) || defined (__AVR32_UC3C0512CREVC__) || defined (__AVR32_UC3C164C__) || defined (__AVR32_UC3C1128C__) || defined (__AVR32_UC3C1256C__) || defined (__AVR32_UC3C1512CREVC__) || defined (__AVR32_UC3C264C__) || defined (__AVR32_UC3C2128C__) || defined (__AVR32_UC3C2256C__) || defined (__AVR32_UC3C2512CREVC__))) \
||( defined (__ICCAVR32__) && ( defined (__AT32UC3C064C__) || defined (__AT32UC3C0128C__) || defined (__AT32UC3C0256C__) || defined (__AT32UC3C0512C__) || defined (__AT32UC3C164C__) || defined (__AT32UC3C1128C__) || defined (__AT32UC3C1256C__) || defined (__AT32UC3C1512C__) || defined (__AT32UC3C264C__) || defined (__AT32UC3C2128C__) || defined (__AT32UC3C2256C__) || defined (__AT32UC3C2512C__)))
flashc_set_flash_waitstate_and_readmode(fcrystal);
#endif
// Set the main clock source as being OSC0.
pm_set_mclk_source(PM_CLK_SRC_OSC0);
}
else
{
return PCL_NOT_SUPPORTED;
}
#endif
#endif
return PASS;
}
/* \brief This is an example that shows:
* - how to configure OSC0
* - how to set the main clock to use OSC0 as input
* - how to configure a generic clock GCLK to use OSC0 as input
* - how to output a generic clock to a pin (GLCK_0_1 for EVK1100 or GCLK_2 for
* EVK1101 or GLCK_1_0 for EVK1104+UC3_A3_XPLAINED or GLCK_1_0 for STK600+RCUC3L0
or GLCK_0 for STK600+RCUC3D)
* - how to go into a sleep mode (while still maintaining GCLK output)
*
*/
int main(void)
{
volatile avr32_pm_t* pm = &AVR32_PM;
#if ( BOARD == STK600_RCUC3L0 ) || ( BOARD == UC3C_EK ) || (BOARD == STK600_RCUC3D)
// Note: for UC3 C, D and L series, the osc configurations are handled by the SCIF module
// and the synchronous clocks used to clock the main digital logic are handled
// by the PM module.
// 1) Configure OSC0 in crystal mode, external crystal with a FOSC0 Hz frequency.
scif_configure_osc_crystalmode(SCIF_OSC0, FOSC0);
// 2) Enable the OSC0
scif_enable_osc(SCIF_OSC0, OSC0_STARTUP, true);
// 3) Set the main clock source as being OSC0.
pm_set_mclk_source(PM_CLK_SRC_OSC0);
#else
// 1) Configure OSC0 in crystal mode, external crystal with a FOSC0 Hz frequency.
pm_enable_osc0_crystal(pm, FOSC0);
// 2) Enable the OSC0
pm_enable_clk0(pm, OSC0_STARTUP);
// 3) Set the main clock source as being OSC0.
pm_switch_to_clock(pm, AVR32_PM_MCSEL_OSC0);
#endif
// - Configure a generic clock GCLK to use OSC0 as input
// - Output that generic clock to a pin
local_enable_gclk_on_gpio(pm);
//*** Sleep mode
// If there is a chance that any PB write operations are incomplete, the CPU
// should perform a read operation from any register on the PB bus before
// executing the sleep instruction.
AVR32_INTC.ipr[0]; // Dummy read
// - Go into a sleep mode (while still maintaining GCLK output)
SLEEP(AVR32_PM_SMODE_FROZEN);
while (true);
}
static void clockfrequencies_configure(void)
{
#if UC3L
static scif_gclk_opt_t gc_dfllif_ref_opt = { SCIF_GCCTRL_SLOWCLOCK, 0, false };
static pcl_freq_param_t pcl_dfll_freq_param =
{
.main_clk_src = PCL_MC_DFLL0,
.cpu_f = EXAMPLE_MCUCLK_HZ,
.pba_f = EXAMPLE_MCUCLK_HZ,
.pbb_f = EXAMPLE_MCUCLK_HZ,
.dfll_f = EXAMPLE_FDFLL_HZ,
.pextra_params = &gc_dfllif_ref_opt
};
// Implementation for UC3L
// Note: on the AT32UC3L-EK board, there is no crystal/external clock connected
// to the OSC0 pinout XIN0/XOUT0. We shall then program the DFLL and switch the
// main clock source to the DFLL.
pcl_configure_clocks(&pcl_dfll_freq_param);
// Note: since it is dynamically computing the appropriate field values of the
// configuration registers from the parameters structure, this function is not
// optimal in terms of code size. For a code size optimal solution, it is better
// to create a new function from pcl_configure_clocks_dfll0() and modify it
// to use preprocessor computation from pre-defined target frequencies.
#elif UC3C
// Configure OSC0 in crystal mode, external crystal with a FOSC0 Hz frequency.
scif_configure_osc_crystalmode(SCIF_OSC0, FOSC0);
// Enable the OSC0
scif_enable_osc(SCIF_OSC0, OSC0_STARTUP, true);
// Set the main clock source as being OSC0.
pm_set_mclk_source(PM_CLK_SRC_OSC0);
scif_pll_opt_t opt;
// Setup PLL0 on Osc0, mul=7 ,no divisor, lockcount=16: (16Mhzx8)/2 = 64MHz output
opt.osc = SCIF_OSC0; // Sel Osc0 or Osc1
opt.lockcount = 16; // lockcount in main clock for the PLL wait lock
opt.div = 1; // DIV=1 in the formula
opt.mul = 7; // MUL=7 in the formula
opt.pll_div2 = 1; // pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value)
opt.pll_wbwdisable = 0; //pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode.
opt.pll_freq = 1; // Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz.
scif_pll_setup(SCIF_PLL0, &opt); // lockcount in main clock for the PLL wait lock
/* Enable PLL0 */
scif_pll_enable(SCIF_PLL0);
/* Wait for PLL0 locked */
scif_wait_for_pll_locked(SCIF_PLL0) ;
// Divide PLL0 output by 2 for CPU, HSB and PBx clocks = 32MHz
pm_set_clk_domain_div(PM_CLK_DOMAIN_0, (pm_divratio_t) 0); // CPU
pm_set_clk_domain_div(PM_CLK_DOMAIN_1, (pm_divratio_t) 0); // HSB
pm_set_clk_domain_div(PM_CLK_DOMAIN_3, (pm_divratio_t) 0); // PBB
pm_set_clk_domain_div(PM_CLK_DOMAIN_2, (pm_divratio_t) 0); // PBA
pm_set_clk_domain_div(PM_CLK_DOMAIN_4, (pm_divratio_t) 0); // PBC
/* Set the main clock source as being PLL0. */
pm_set_mclk_source(PM_CLK_SRC_PLL0);
#elif UC3D
// Configure OSC0 in crystal mode, external crystal with a FOSC0 Hz frequency.
scif_configure_osc_crystalmode(SCIF_OSC0, FOSC0);
// Enable the OSC0
scif_enable_osc(SCIF_OSC0, OSC0_STARTUP, true);
// Set the main clock source as being OSC0.
pm_set_mclk_source(PM_CLK_SRC_OSC0);
scif_pll_opt_t opt;
// Setup PLL0 on Osc0, mul=10 ,no divisor, lockcount=16: (12Mhzx11)/2 = 66MHz output
opt.osc = SCIF_OSC0; // Sel Osc0 or Osc1
opt.lockcount = 16; // lockcount in main clock for the PLL wait lock
opt.div = 1; // DIV=1 in the formula
opt.mul = 10; // MUL=10 in the formula
opt.pll_div2 = 1; // pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value)
opt.pll_wbwdisable = 0; // pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode.
opt.pll_freq = 1; // Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz.
scif_pll_setup(SCIF_PLL0, &opt); // lockcount in main clock for the PLL wait lock
/* Enable PLL0 */
scif_pll_enable(SCIF_PLL0);
/* Wait for PLL0 locked */
scif_wait_for_pll_locked(SCIF_PLL0) ;
// Divide PLL0 output by 2 for CPU, HSB and PBx clocks = 33MHz
pm_set_clk_domain_div(PM_CLK_DOMAIN_0, (pm_divratio_t) 0); // CPU
pm_set_clk_domain_div(PM_CLK_DOMAIN_1, (pm_divratio_t) 0); // HSB
pm_set_clk_domain_div(PM_CLK_DOMAIN_3, (pm_divratio_t) 0); // PBB
pm_set_clk_domain_div(PM_CLK_DOMAIN_2, (pm_divratio_t) 0); // PBA
/* Set the main clock source as being PLL0. */
pm_set_mclk_source(PM_CLK_SRC_PLL0);
#else // UC3A and UC3B series
// Switch the main clock source to Osc0.
pm_switch_to_osc0(&AVR32_PM, FOSC0, OSC0_STARTUP);
// Setup PLL0 on Osc0, mul=10 ,no divisor, lockcount=16: 12Mhzx11 = 132MHz output
pm_pll_setup(&AVR32_PM, 0, // pll.
10, // mul.
1, // div.
0, // osc.
16); // lockcount.
// PLL output VCO frequency is 132MHz.
// We divide it by 2 with the pll_div2=1 to get a main clock at 66MHz.
pm_pll_set_option(&AVR32_PM, 0, // pll.
1, // pll_freq.
1, // pll_div2.
0); // pll_wbwdisable.
// Enable the PLL.
pm_pll_enable(&AVR32_PM, 0);
// Wait until the PLL output is stable.
pm_wait_for_pll0_locked(&AVR32_PM);
// Configure each clock domain to use the main clock divided by 2
// => fCPU = fPBA = fPBB = 33MHz.
pm_cksel(&AVR32_PM,
1, // pbadiv.
0, // pbasel.
1, // pbbdiv.
0, // pbbsel.
1, // hsbdiv=cpudiv
0); // hsbsel=cpusel
// Switch the main clock source to PLL0.
pm_switch_to_clock(&AVR32_PM, AVR32_PM_MCCTRL_MCSEL_PLL0);
#endif
}
static long int pcl_configure_clocks_uc3c(pcl_freq_param_t *param)
{
#define PM_MAX_MUL ((1 << AVR32_SCIF_PLLMUL_SIZE) - 1)
#define AVR32_PM_PBA_MAX_FREQ 66000000
#define AVR32_PM_PLL_VCO_RANGE0_MAX_FREQ 240000000
#define AVR32_PM_PLL_VCO_RANGE0_MIN_FREQ 160000000
// Implementation for UC3C parts.
// Supported frequencies:
// Fosc0 mul div PLL div2_en cpu_f pba_f Comment
// 12 15 1 192 1 12 12
// 12 9 3 40 1 20 20 PLL out of spec
// 12 15 1 192 1 24 12
// 12 9 1 120 1 30 15
// 12 9 3 40 0 40 20 PLL out of spec
// 12 15 1 192 1 48 12
// 12 15 1 192 1 48 24
// 12 8 1 108 1 54 27
// 12 9 1 120 1 60 15
// 12 9 1 120 1 60 30
// 12 10 1 132 1 66 16.5
//
unsigned long in_cpu_f = param->cpu_f;
unsigned long in_osc0_f = param->osc0_f;
unsigned long mul, div, div2_en = 0, div2_cpu = 0, div2_pba = 0;
unsigned long pll_freq, rest;
Bool b_div2_pba, b_div2_cpu;
// Configure OSC0 in crystal mode, external crystal with a FOSC0 Hz frequency.
scif_configure_osc_crystalmode(SCIF_OSC0, in_osc0_f);
// Enable the OSC0
scif_enable_osc(SCIF_OSC0, param->osc0_startup, true);
// Set the main clock source as being OSC0.
pm_set_mclk_source(PM_CLK_SRC_OSC0);
// Start with CPU freq config
if (in_cpu_f == in_osc0_f)
{
param->cpu_f = in_osc0_f;
param->pba_f = in_osc0_f;
return PASS;
}
else if (in_cpu_f < in_osc0_f)
{
// TBD
}
rest = in_cpu_f % in_osc0_f;
for (div = 1; div < 32; div++)
{
if ((div * rest) % in_osc0_f == 0)
break;
}
if (div == 32)
return FAIL;
mul = (in_cpu_f * div) / in_osc0_f;
if (mul > PM_MAX_MUL)
return FAIL;
// export 2power from PLL div to div2_cpu
while (!(div % 2))
{
div /= 2;
div2_cpu++;
}
// Here we know the mul and div parameter of the PLL config.
// . Check out if the PLL has a valid in_cpu_f.
// . Try to have for the PLL frequency (VCO output) the highest possible value
// to reduce jitter.
while (in_osc0_f * 2 * mul / div < AVR32_PM_PLL_VCO_RANGE0_MAX_FREQ)
{
if (2 * mul > PM_MAX_MUL)
break;
mul *= 2;
div2_cpu++;
}
if (div2_cpu != 0)
{
div2_cpu--;
div2_en = 1;
}
pll_freq = in_osc0_f * mul / (div * (1 << div2_en));
// Update real CPU Frequency
param->cpu_f = pll_freq / (1 << div2_cpu);
mul--;
scif_pll_opt_t opt;
opt.osc = SCIF_OSC0, // Sel Osc0 or Osc1
opt.lockcount = 16, // lockcount in main clock for the PLL wait lock
opt.div = div, // DIV=1 in the formula
opt.mul = mul, // MUL=7 in the formula
opt.pll_div2 = div2_en, // pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value)
opt.pll_wbwdisable = 0, //pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode.
opt.pll_freq = (pll_freq < AVR32_PM_PLL_VCO_RANGE0_MIN_FREQ) ? 1 : 0, // Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz.
scif_pll_setup(SCIF_PLL0, opt); // lockcount in main clock for the PLL wait lock
/* Enable PLL0 */
scif_pll_enable(SCIF_PLL0);
/* Wait for PLL0 locked */
scif_wait_for_pll_locked(SCIF_PLL0) ;
rest = pll_freq;
while (rest > AVR32_PM_PBA_MAX_FREQ ||
rest != param->pba_f)
{
div2_pba++;
rest = pll_freq / (1 << div2_pba);
if (rest < param->pba_f)
break;
}
// Update real PBA Frequency
param->pba_f = pll_freq / (1 << div2_pba);
if (div2_cpu)
{
b_div2_cpu = TRUE;
div2_cpu--;
}
else
b_div2_cpu = FALSE;
if (div2_pba)
{
b_div2_pba = TRUE;
div2_pba--;
}
else
b_div2_pba = FALSE;
if (b_div2_cpu == TRUE )
{
pm_set_clk_domain_div(PM_CLK_DOMAIN_0, (pm_divratio_t) div2_cpu); // CPU
pm_set_clk_domain_div(PM_CLK_DOMAIN_1, (pm_divratio_t) div2_cpu); // HSB
pm_set_clk_domain_div(PM_CLK_DOMAIN_3, (pm_divratio_t) div2_cpu); // PBB
}
if (b_div2_pba == TRUE )
{
pm_set_clk_domain_div(PM_CLK_DOMAIN_2, (pm_divratio_t) div2_pba); // PBA
pm_set_clk_domain_div(PM_CLK_DOMAIN_4, (pm_divratio_t) div2_pba); // PBC
}
// Set Flashc Wait State
flashc_set_flash_waitstate_and_readmode(param->cpu_f);
// Set the main clock source as being PLL0.
pm_set_mclk_source(PM_CLK_SRC_PLL0);
return PASS;
}
/**
* \brief Detects extern OSC frequency and initialize system clocks on it
*/
void sysclk_auto_init(void)
{
int mul;
// Switch to OSC ISP
// Set max startup time to make sure any crystal will be supported
// We cannot use a TC to measure this OSC frequency
// because the master clock must be faster than the clock selected by the TC
// Configure OSC0 in crystal mode, external crystal with a fcrystal Hz frequency.
// Replace "scif_configure_osc_crystalmode(SCIF_OSC0, 16000000)" by
// inline routine to safe code (160B)
{
u_avr32_scif_oscctrl0_t u_avr32_scif_oscctrl0 = {AVR32_SCIF.oscctrl0};
// Modify : Configure the oscillator mode to crystal and set the gain according to the
// crystal frequency.
u_avr32_scif_oscctrl0.OSCCTRL0.mode = SCIF_OSC_MODE_2PIN_CRYSTAL;
u_avr32_scif_oscctrl0.OSCCTRL0.gain =
(16000000 < 900000) ? AVR32_SCIF_OSCCTRL0_GAIN_G0 :
(16000000 < 3000000) ? AVR32_SCIF_OSCCTRL0_GAIN_G1 :
(16000000 < 8000000) ? AVR32_SCIF_OSCCTRL0_GAIN_G2 :
AVR32_SCIF_OSCCTRL0_GAIN_G3;
AVR32_ENTER_CRITICAL_REGION( );
// Unlock the write-protected OSCCTRL0 register
SCIF_UNLOCK(AVR32_SCIF_OSCCTRL0);
// Write Back
AVR32_SCIF.oscctrl0 = u_avr32_scif_oscctrl0.oscctrl0;
AVR32_LEAVE_CRITICAL_REGION( );
}
// Enable the OSC0
scif_enable_osc(SCIF_OSC0, AVR32_SCIF_OSCCTRL0_STARTUP_16384_RCOSC, true);
pm_set_mclk_source(PM_CLK_SRC_OSC0);
// Initialize the AST with the internal RC oscillator
// AST will count at the frequency of 115KHz/2
if (!ast_init_counter(&AVR32_AST, AST_OSC_RC, 0, 0)) {
while (1);
}
// Enable the AST
ast_enable(&AVR32_AST);
// Detect the frequency
switch (freq_detect_start()) {
case 8000000:
mul = 11;
break;
case 16000000:
mul = 5;
break;
case 12000000:
default:
mul = 7;
break;
}
scif_pll_opt_t opt;
// Set PLL0 VCO @ 96 MHz
// Set PLL0 @ 48 MHz
opt.osc = SCIF_OSC0;
opt.lockcount = 63;
opt.div = 1;
opt.mul = mul;
opt.pll_div2 = 1;
opt.pll_wbwdisable = 0;
opt.pll_freq = 1;
// lockcount in main clock for the PLL wait lock
scif_pll0_setup((const scif_pll_opt_t *)&opt);
/* Enable PLL0 */
scif_pll0_enable();
/* Wait for PLL0 locked */
scif_wait_for_pll0_locked();
// Configure and start the RC120Mhz internal oscillator.
scif_start_rc120M();
// Since our target is to set the CPU&HSB frequency domains to 30MHz, we must
// set one wait-state and enable the High-speed read mode on the flash controller.
flashcdw_set_flash_waitstate_and_readmode(30000000UL);
// Set the CPU clock domain to 30MHz (by applying a division ratio = 4).
pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_CPU, PM_CKSEL_DIVRATIO_4);
// Set the PBA clock domain to 30MHz (by applying a division ratio = 4).
pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_PBA, PM_CKSEL_DIVRATIO_4);
// Set the PBB clock domain to 30MHz (by applying a division ratio = 4).
pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_PBB, PM_CKSEL_DIVRATIO_4);
// Set the main clock source to be DFLL0.
pm_set_mclk_source(PM_CLK_SRC_RC120M);
}
/*! \brief This is an example demonstrating the SPI mode of USART IP
* functionalities using the USART driver.
*/
int main(void)
{
#if BOARD == STK600_RCUC3D
// Configure OSC0 in crystal mode, external crystal with a FOSC0 Hz frequency.
scif_configure_osc_crystalmode(SCIF_OSC0, FOSC0);
// Enable the OSC0
scif_enable_osc(SCIF_OSC0, OSC0_STARTUP, true);
// Set the main clock source as being OSC0.
pm_set_mclk_source(PM_CLK_SRC_OSC0);
#else
// Switch main clock to external oscillator 0 (crystal).
pm_switch_to_osc0(&AVR32_PM, FOSC0, OSC0_STARTUP);
#endif
static const gpio_map_t USART_GPIO_MAP =
{
{EXAMPLE_USART_RX_PIN, EXAMPLE_USART_RX_FUNCTION},
{EXAMPLE_USART_TX_PIN, EXAMPLE_USART_TX_FUNCTION}
};
static const usart_options_t USART_OPTIONS =
{
.baudrate = 57600,
.charlength = 8,
.paritytype = USART_NO_PARITY,
.stopbits = USART_1_STOPBIT,
.channelmode = USART_NORMAL_CHMODE
};
// Assign GPIO to USART.
gpio_enable_module(USART_GPIO_MAP,
sizeof(USART_GPIO_MAP) / sizeof(USART_GPIO_MAP[0]));
// Initialize USART in RS232 mode.
usart_init_rs232(EXAMPLE_USART, &USART_OPTIONS, FOSC0);
static const gpio_map_t USART_SPI_GPIO_MAP =
{
{EXAMPLE_USART_SPI_SCK_PIN, EXAMPLE_USART_SPI_SCK_FUNCTION },
{EXAMPLE_USART_SPI_MISO_PIN, EXAMPLE_USART_SPI_MISO_FUNCTION},
{EXAMPLE_USART_SPI_MOSI_PIN, EXAMPLE_USART_SPI_MOSI_FUNCTION},
{EXAMPLE_USART_SPI_NSS_PIN, EXAMPLE_USART_SPI_NSS_FUNCTION }
};
static const usart_spi_options_t USART_SPI_OPTIONS =
{
.baudrate = 60000,
.charlength = 8,
.spimode = 0,
.channelmode = USART_NORMAL_CHMODE
};
// Assign GPIO to SPI.
gpio_enable_module(USART_SPI_GPIO_MAP,
sizeof(USART_SPI_GPIO_MAP) / sizeof(USART_SPI_GPIO_MAP[0]));
// Initialize USART in SPI mode.
usart_init_spi_master(EXAMPLE_USART_SPI, &USART_SPI_OPTIONS, FOSC0);
// Show startup message
usart_write_line(EXAMPLE_USART, "Basic write in USART SPI Mode (press enter)\r\n");
// Press enter to continue.
while (usart_get_echo_line(EXAMPLE_USART) == USART_FAILURE); // Get and echo characters until end of line.
usart_write_line(EXAMPLE_USART, "Writing SPI test pattern.\r\n");
while (true)
{
usart_spi_selectChip(EXAMPLE_USART_SPI);
usart_putchar(EXAMPLE_USART_SPI, 0x55);
usart_putchar(EXAMPLE_USART_SPI, 0xAA);
usart_spi_unselectChip(EXAMPLE_USART_SPI);
}
}
/**
* \brief Detects extern OSC frequency and initialize system clocks on it
*/
void sysclk_auto_init(void)
{
int mul;
// Switch to OSC ISP
// Set max startup time to make sure any crystal will be supported
// We cannot use a TC to measure this OSC frequency
// because the master clock must be faster than the clock selected by the TC
// Configure OSC0 in crystal mode, external crystal with a fcrystal Hz frequency.
// Replace "scif_configure_osc_crystalmode(SCIF_OSC0, 16000000)" by
// inline routine to safe code (160B)
{
typedef union
{
unsigned long oscctrl[2];
avr32_scif_oscctrl_t OSCCTRL[2];
} u_avr32_scif_oscctrl_t;
u_avr32_scif_oscctrl_t u_avr32_scif_oscctrl;
// Read Register
u_avr32_scif_oscctrl.OSCCTRL[SCIF_OSC0] = AVR32_SCIF.OSCCTRL[SCIF_OSC0] ;
// Modify : Configure the oscillator mode to crystal and set the gain according to the
// crystal frequency.
u_avr32_scif_oscctrl.OSCCTRL[SCIF_OSC0].mode = SCIF_OSC_MODE_2PIN_CRYSTAL;
u_avr32_scif_oscctrl.OSCCTRL[SCIF_OSC0].gain =
(16000000 < 900000) ? AVR32_SCIF_OSCCTRL0_GAIN_G0 :
(16000000 < 3000000) ? AVR32_SCIF_OSCCTRL0_GAIN_G1 :
(16000000 < 8000000) ? AVR32_SCIF_OSCCTRL0_GAIN_G2 :
AVR32_SCIF_OSCCTRL0_GAIN_G3;
AVR32_ENTER_CRITICAL_REGION( );
// Unlock the write-protected OSCCTRL0 register
SCIF_UNLOCK(AVR32_SCIF_OSCCTRL);
// Write Back
AVR32_SCIF.OSCCTRL[SCIF_OSC0] = u_avr32_scif_oscctrl.OSCCTRL[SCIF_OSC0];
AVR32_LEAVE_CRITICAL_REGION( );
}
// Enable the OSC0
scif_enable_osc(SCIF_OSC0, AVR32_SCIF_OSCCTRL0_STARTUP_16384_RCOSC, true);
flashc_set_flash_waitstate_and_readmode(16000000);
pm_set_mclk_source(PM_CLK_SRC_OSC0);
// Initialize the AST with the internal RC oscillator
// AST will count at the frequency of 115KHz/2
if (!ast_init_counter(&AVR32_AST, AST_OSC_RC, 0, 0)) {
while (1);
}
// Enable the AST
ast_enable(&AVR32_AST);
// Detect the frequency
switch (freq_detect_start()) {
case 8000000:
mul = 5;
break;
case 16000000:
mul = 2;
break;
case 12000000:
default:
mul = 3;
break;
}
scif_pll_opt_t opt;
// Set PLL0 VCO @ 96 MHz
// Set PLL0 @ 48 MHz
opt.osc = SCIF_OSC0;
opt.lockcount = 63;
opt.div = 0;
opt.mul = mul;
opt.pll_div2 = 1;
opt.pll_wbwdisable = 0;
opt.pll_freq = 1;
// lockcount in main clock for the PLL wait lock
scif_pll_setup(SCIF_PLL0, &opt);
/* Enable PLL0 */
scif_pll_enable(SCIF_PLL0);
/* Wait for PLL0 locked */
scif_wait_for_pll_locked(SCIF_PLL0);
// Use 1 flash wait state
flashc_set_wait_state(1);
// Switch the main clock to PLL0
pm_set_mclk_source(PM_CLK_SRC_PLL0);
// fCPU: 48 MHz // USBC request a CPU clock >25MHz
// fPBA: 48 MHz
// fHSB: 48 MHz
// fPBB: 48 MHz must be the same that CPU
// fPBC: 48 MHz
pm_disable_clk_domain_div(PM_CLK_DOMAIN_0); // CPU
pm_disable_clk_domain_div(PM_CLK_DOMAIN_1); // HSB
pm_disable_clk_domain_div(PM_CLK_DOMAIN_2); // PBA
pm_disable_clk_domain_div(PM_CLK_DOMAIN_3); // PBB
pm_disable_clk_domain_div(PM_CLK_DOMAIN_4); // PBC
// Use 0 flash wait state
flashc_set_wait_state(1);
}
/* \brief Start PLL0, switch main clock to PLL0 output.
*
*
*/
static void local_start_highfreq_clock(void)
{
#if BOARD == STK600_RCUC3L0 || BOARD == UC3L_EK
scif_dfll_openloop_conf_t dfllconfig = {EXAMPLE_DFLL_FINE_FDFLL96, EXAMPLE_DFLL_COARSE_FDFLL96};
// Configure and start the DFLL0 in open loop mode to generate a frequency of 96MHz.
scif_dfll0_openloop_start(&dfllconfig);
// Since our target is to set the CPU&HSB frequency domains to 48MHz, we must
// set one wait-state and enable the High-speed read mode on the flash controller.
flashcdw_set_flash_waitstate_and_readmode(EXAMPLE_CPUCLK_HZ);
// Set the CPU clock domain to 48MHz (by applying a division ratio = 2).
pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_CPU, PM_CKSEL_DIVRATIO_2);
// Set the PBA clock domain to 24MHz (by applying a division ratio = 4).
pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_PBA, PM_CKSEL_DIVRATIO_4);
// Set the PBB clock domain to 48MHz (by applying a division ratio = 2).
pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_PBB, PM_CKSEL_DIVRATIO_2);
// Set the main clock source to be DFLL0.
pm_set_mclk_source(PM_CLK_SRC_DFLL0);
#elif BOARD == UC3C_EK || BOARD == STK600_RCUC3D
scif_pll_opt_t opt;
// Configure OSC0 in crystal mode, external crystal with a FOSC0 Hz frequency.
scif_configure_osc_crystalmode(SCIF_OSC0, FOSC0);
// Enable the OSC0
scif_enable_osc(SCIF_OSC0, OSC0_STARTUP, true);
// Set the main clock source as being OSC0.
pm_set_mclk_source(PM_CLK_SRC_OSC0);
opt.osc = SCIF_OSC0; // Sel Osc0 or Osc1
opt.lockcount = 16; // lockcount in main clock for the PLL wait lock
opt.div = 1; // DIV=1 in the formula
opt.mul = 5; // MUL=6 in the formula
opt.pll_div2 = 1; // pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value)
opt.pll_wbwdisable = 0; //pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode.
opt.pll_freq = 1; // Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz.
scif_pll_setup(SCIF_PLL0, &opt); // lockcount in main clock for the PLL wait lock
/* Enable PLL0 */
scif_pll_enable(SCIF_PLL0);
/* Wait for PLL0 locked */
scif_wait_for_pll_locked(SCIF_PLL0) ;
/* Divide PBA clock by 2 from main clock (PBA clock = 48MHz/2 = 24MHz).
Peripheral Bus A clock divisor enable = 1
Peripheral Bus A select = 0
Peripheral Bus B clock divisor enable = 0
Peripheral Bus B select = 0
High Speed Bus clock divisor enable = 0
High Speed Bus select = 0
*/
pm_set_clk_domain_div(PM_CLK_DOMAIN_2, (pm_divratio_t) 0); // PBA
// Set one wait-state (WS) for flash controller. 0 WS access is up to 30MHz for HSB/CPU clock.
// As we want to have 48MHz on HSB/CPU clock, we need to set 1 WS on flash controller.
#if UC3D
flashcdw_set_wait_state(1);
#else
flashc_set_wait_state(1);
#endif
// Set the main clock source as being PLL0.
pm_set_mclk_source(PM_CLK_SRC_PLL0);
#else
volatile avr32_pm_t* pm = &AVR32_PM;
/* \note All calculations here suppose that the Osc0 frequency is 12MHz. */
pm_switch_to_osc0(pm, FOSC0, OSC0_STARTUP); // Switch main clock to Osc0.
/* Setup PLL0 on Osc0, mul=7 ,no divisor, lockcount=16, ie. 12Mhzx8 = 96MHz output */
/*void pm_pll_setup(volatile avr32_pm_t* pm,
unsigned int pll,
unsigned int mul,
unsigned int div,
unsigned int osc,
unsigned int lockcount) {
*/
pm_pll_setup(pm,
0, // use PLL0
7, // MUL=7 in the formula
1, // DIV=1 in the formula
0, // Sel Osc0/PLL0 or Osc1/PLL1
16); // lockcount in main clock for the PLL wait lock
/*
This function will set a PLL option.
*pm Base address of the Power Manager (i.e. &AVR32_PM)
pll PLL number 0
pll_freq Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz.
pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value)
pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode.
*/
/* PLL output VCO frequency is 96MHz. We divide it by 2 with the pll_div2=1. This enable to get later main clock to 48MHz */
pm_pll_set_option(pm, 0, 1, 1, 0);
/* Enable PLL0 */
/*
void pm_pll_enable(volatile avr32_pm_t* pm,
unsigned int pll) {
*/
pm_pll_enable(pm,0);
/* Wait for PLL0 locked */
pm_wait_for_pll0_locked(pm) ;
/* Divide PBA clock by 2 from main clock (PBA clock = 48MHz/2 = 24MHz).
Peripheral Bus A clock divisor enable = 1
Peripheral Bus A select = 0
Peripheral Bus B clock divisor enable = 0
Peripheral Bus B select = 0
High Speed Bus clock divisor enable = 0
High Speed Bus select = 0
*/
pm_cksel(pm, 1, 0, 0, 0, 0, 0);
// Set one wait-state (WS) for flash controller. 0 WS access is up to 30MHz for HSB/CPU clock.
// As we want to have 48MHz on HSB/CPU clock, we need to set 1 WS on flash controller.
flashc_set_wait_state(1);
pm_switch_to_clock(pm, AVR32_PM_MCSEL_PLL0); /* Switch main clock to 48MHz */
#endif
}
/**
* \brief Detects extern OSC frequency and initialize system clocks on it
*/
void sysclk_auto_init(void)
{
int mul;
// Switch to OSC ISP
// Set max startup time to make sure any crystal will be supported
// We cannot use a TC to measure this OSC frequency
// because the master clock must be faster than the clock selected by the TC
// Configure OSC0 in crystal mode, external crystal
// with a fcrystal Hz frequency.
scif_configure_osc_crystalmode(SCIF_OSC0, 12000000);
// Enable the OSC0
scif_enable_osc(SCIF_OSC0, AVR32_SCIF_OSCCTRL0_STARTUP_16384_RCOSC,
true);
flashcdw_set_flash_waitstate_and_readmode(12000000);
pm_set_mclk_source(PM_CLK_SRC_OSC0);
// Initialize the AST with the internal RC oscillator
// AST will count at the frequency of 115KHz/2
if (!ast_init_counter(&AVR32_AST, AST_OSC_RC, 0, 0)) {
while (1);
}
// Enable the AST
ast_enable(&AVR32_AST);
// Detect the frequency
switch (freq_detect_start()) {
case 8000000:
mul = 5;
break;
case 16000000:
mul = 2;
break;
case 12000000:
default:
mul = 3;
break;
}
scif_pll_opt_t opt;
// Set PLL0 VCO @ 96 MHz
// Set PLL0 @ 48 MHz
opt.osc = SCIF_OSC0;
opt.lockcount = 63;
opt.div = 0;
opt.mul = mul;
opt.pll_div2 = 1;
opt.pll_wbwdisable = 0;
opt.pll_freq = 1;
// lockcount in main clock for the PLL wait lock
scif_pll_setup(SCIF_PLL0, &opt);
/* Enable PLL0 */
scif_pll_enable(SCIF_PLL0);
/* Wait for PLL0 locked */
scif_wait_for_pll_locked(SCIF_PLL0);
// Use 1 flash wait state
flashcdw_set_wait_state(1);
// Switch the main clock to PLL0
pm_set_mclk_source(PM_CLK_SRC_PLL0);
// fCPU: 48 MHz // USBC request a CPU clock >25MHz
// fHSB: 48 MHz
// fPBA: 48 MHz
// fPBB: 48 MHz
pm_disable_clk_domain_div(PM_CLK_DOMAIN_0); // CPU
pm_disable_clk_domain_div(PM_CLK_DOMAIN_1); // HSB
pm_disable_clk_domain_div(PM_CLK_DOMAIN_2); // PBA
pm_disable_clk_domain_div(PM_CLK_DOMAIN_3); // PBB
// Use 0 flash wait state
flashcdw_set_wait_state(1);
}
