static int __init msm_cpu_prepare(unsigned int cpu) { u64 mpidr_el1 = cpu_logical_map(cpu); if (scm_is_mc_boot_available()) { if (mpidr_el1 & ~MPIDR_HWID_BITMASK) { pr_err("CPU%d:Failed to set boot address\n", cpu); return -ENOSYS; } if (scm_set_boot_addr_mc(virt_to_phys(secondary_holding_pen), BIT(MPIDR_AFFINITY_LEVEL(mpidr_el1, 0)), BIT(MPIDR_AFFINITY_LEVEL(mpidr_el1, 1)), BIT(MPIDR_AFFINITY_LEVEL(mpidr_el1, 2)), SCM_FLAG_COLDBOOT_MC)) { pr_warn("CPU%d:Failed to set boot address\n", cpu); return -ENOSYS; } } else { if (scm_set_boot_addr(virt_to_phys(secondary_holding_pen), cold_boot_flags[cpu])) { pr_warn("Failed to set CPU %u boot address\n", cpu); return -ENOSYS; } } /* Mark CPU0 cold boot flag as done */ if (per_cpu(cold_boot_done, 0) == false) per_cpu(cold_boot_done, 0) = true; return 0; }
static void __init msm_platform_smp_prepare_cpus(unsigned int max_cpus) { int cpu, map; unsigned int flags = 0; if (scm_is_mc_boot_available()) return msm_platform_smp_prepare_cpus_mc(max_cpus); for_each_present_cpu(cpu) { map = cpu_logical_map(cpu); if (map > ARRAY_SIZE(cold_boot_flags)) { set_cpu_present(cpu, false); __WARN(); continue; } flags |= cold_boot_flags[map]; } #ifdef CONFIG_HTC_DEBUG_FOOTPRINT init_cpu_debug_counter_for_cold_boot(); #endif if (scm_set_boot_addr(virt_to_phys(msm_secondary_startup), flags)) pr_warn("Failed to set CPU boot address\n"); }
int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) { int ret; int flag = 0; unsigned long timeout; pr_debug("Starting secondary CPU %d\n", cpu); preset_lpj = loops_per_jiffy; if (cpu > 0 && cpu < ARRAY_SIZE(cold_boot_flags)) flag = cold_boot_flags[cpu]; else __WARN(); if (per_cpu(cold_boot_done, cpu) == false) { init_cpu_debug_counter_for_cold_boot(); ret = scm_set_boot_addr((void *) virt_to_phys(msm_secondary_startup), flag); if (ret == 0) release_secondary(cpu); else printk(KERN_DEBUG "Failed to set secondary core boot " "address\n"); per_cpu(cold_boot_done, cpu) = true; } spin_lock(&boot_lock); /* * The secondary processor is waiting to be released from * the holding pen - release it, then wait for it to flag * that it has been released by resetting pen_release. * * Note that "pen_release" is the hardware CPU ID, whereas * "cpu" is Linux's internal ID. */ write_pen_release(cpu_logical_map(cpu)); gic_raise_softirq(cpumask_of(cpu), 1); timeout = jiffies + (1 * HZ); while (time_before(jiffies, timeout)) { smp_rmb(); if (pen_release == -1) break; udelay(10); } spin_unlock(&boot_lock); return pen_release != -1 ? -ENOSYS : 0; }
/* Executed by primary CPU, brings other CPUs out of reset. Called at boot as well as when a CPU is coming out of shutdown induced by echo 0 > /sys/devices/.../cpuX. */ int boot_secondary(unsigned int cpu, struct task_struct *idle) { static int cold_boot_done; int cnt = 0; int ret; pr_debug("Starting secondary CPU %d\n", cpu); /* Set preset_lpj to avoid subsequent lpj recalculations */ preset_lpj = loops_per_jiffy; if (cold_boot_done == false) { ret = scm_set_boot_addr((void *) virt_to_phys(msm_secondary_startup), SCM_FLAG_COLDBOOT_CPU1); if (ret == 0) { void *sc1_base_ptr; sc1_base_ptr = ioremap_nocache(0x00902000, SZ_4K*2); if (sc1_base_ptr) { writel(0x0, sc1_base_ptr+0x15A0); dmb(); writel(0x0, sc1_base_ptr+0xD80); writel(0x3, sc1_base_ptr+0xE64); dsb(); iounmap(sc1_base_ptr); } } else printk(KERN_DEBUG "Failed to set secondary core boot " "address\n"); cold_boot_done = true; } pen_release = cpu; dmac_flush_range((void *)&pen_release, (void *)(&pen_release + sizeof(pen_release))); __asm__("sev"); dsb(); /* Use smp_cross_call() to send a soft interrupt to wake up * the other core. */ smp_cross_call(cpumask_of(cpu)); while (pen_release != 0xFFFFFFFF) { dmac_inv_range((void *)&pen_release, (void *)(&pen_release+sizeof(pen_release))); usleep(500); if (cnt++ >= 10) break; } return 0; }
static int __init msm_pm_tz_boot_init(void) { int flag = 0; if (num_possible_cpus() == 1) flag = SCM_FLAG_WARMBOOT_CPU0; else if (num_possible_cpus() == 2) flag = SCM_FLAG_WARMBOOT_CPU0 | SCM_FLAG_WARMBOOT_CPU1; else __WARN(); return scm_set_boot_addr((void *)virt_to_phys(msm_pm_boot_entry), flag); }
int boot_secondary(unsigned int cpu, struct task_struct *idle) { int ret; int flag = 0; unsigned long timeout; pr_debug("Starting secondary CPU %d\n", cpu); preset_lpj = loops_per_jiffy; if (cpu > 0 && cpu < ARRAY_SIZE(cold_boot_flags)) flag = cold_boot_flags[cpu]; else __WARN(); if (per_cpu(cold_boot_done, cpu) == false) { ret = scm_set_boot_addr((void *) virt_to_phys(msm_secondary_startup), flag); if (ret == 0) release_secondary(cpu); else printk(KERN_DEBUG "Failed to set secondary core boot " "address\n"); per_cpu(cold_boot_done, cpu) = true; init_cpu_debug_counter_for_cold_boot(); } spin_lock(&boot_lock); pen_release = cpu_logical_map(cpu); __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); gic_raise_softirq(cpumask_of(cpu), 1); timeout = jiffies + (1 * HZ); while (time_before(jiffies, timeout)) { smp_rmb(); if (pen_release == -1) break; dmac_inv_range((void *)&pen_release, (void *)(&pen_release+sizeof(pen_release))); udelay(10); } spin_unlock(&boot_lock); return pen_release != -1 ? -ENOSYS : 0; }
/* Executed by primary CPU, brings other CPUs out of reset. Called at boot as well as when a CPU is coming out of shutdown induced by echo 0 > /sys/devices/.../cpuX. */ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) { int cnt = 0; int ret; int flag = 0; pr_debug("Starting secondary CPU %d\n", cpu); /* Set preset_lpj to avoid subsequent lpj recalculations */ preset_lpj = loops_per_jiffy; if (cpu > 0 && cpu < ARRAY_SIZE(cold_boot_flags)) flag = cold_boot_flags[cpu]; else __WARN(); if (per_cpu(cold_boot_done, cpu) == false) { ret = scm_set_boot_addr((void *) virt_to_phys(msm_secondary_startup), flag); if (ret == 0) release_secondary(cpu); else printk(KERN_DEBUG "Failed to set secondary core boot " "address\n"); per_cpu(cold_boot_done, cpu) = true; } pen_release = cpu; dmac_flush_range((void *)&pen_release, (void *)(&pen_release + sizeof(pen_release))); __asm__("sev"); mb(); /* Use smp_cross_call() to send a soft interrupt to wake up * the other core. */ gic_raise_softirq(cpumask_of(cpu), 1); while (pen_release != 0xFFFFFFFF) { dmac_inv_range((void *)&pen_release, (void *)(&pen_release+sizeof(pen_release))); usleep(500); if (cnt++ >= 10) break; } return 0; }
static __cpuinit void prepare_cold_cpu(unsigned int cpu) { int ret; ret = scm_set_boot_addr(virt_to_phys(msm_secondary_startup), SCM_FLAG_COLDBOOT_CPU1); if (ret == 0) { void *sc1_base_ptr; sc1_base_ptr = ioremap_nocache(0x00902000, SZ_4K*2); if (sc1_base_ptr) { writel(0, sc1_base_ptr + VDD_SC1_ARRAY_CLAMP_GFS_CTL); writel(0, sc1_base_ptr + SCSS_CPU1CORE_RESET); writel(3, sc1_base_ptr + SCSS_DBG_STATUS_CORE_PWRDUP); iounmap(sc1_base_ptr); } } else printk(KERN_DEBUG "Failed to set secondary core boot " "address\n"); }
static void __init msm_platform_smp_prepare_cpus(unsigned int max_cpus) { int cpu, map; unsigned int flags = 0; for_each_present_cpu(cpu) { map = cpu_logical_map(cpu); if (map > ARRAY_SIZE(cold_boot_flags)) { set_cpu_present(cpu, false); __WARN(); continue; } flags |= cold_boot_flags[map]; } if (scm_set_boot_addr(virt_to_phys(msm_secondary_startup), flags)) pr_warn("Failed to set CPU boot address\n"); }
/* Executed by primary CPU, brings other CPUs out of reset. Called at boot as well as when a CPU is coming out of shutdown induced by echo 0 > /sys/devices/.../cpuX. */ int boot_secondary(unsigned int cpu, struct task_struct *idle) { static int cold_boot_done; int ret; printk(KERN_DEBUG "Starting secondary CPU %d\n", cpu); if (cold_boot_done == false) { ret = scm_set_boot_addr((void *) virt_to_phys(msm_secondary_startup), SCM_FLAG_COLDBOOT_CPU1); if (ret == 0) { void *sc1_base_ptr; sc1_base_ptr = ioremap_nocache(0x00902000, SZ_4K*2); if (sc1_base_ptr) { writel(0x0, sc1_base_ptr+0x15A0); writel(0x0, sc1_base_ptr+0xD80); writel(0x3, sc1_base_ptr+0xE64); iounmap(sc1_base_ptr); } } else printk(KERN_DEBUG "Failed to set secondary core boot " "address\n"); cold_boot_done = true; } pen_release = cpu; dmac_flush_range((void *)&pen_release, (void *)(&pen_release + sizeof(pen_release))); __asm__("sev"); dsb(); /* Use smp_cross_call() to send a soft interrupt to wake up * the other core. */ smp_cross_call(cpumask_of(cpu)); return 0; }
static int msm_pm_tz_boot_init(void) { phys_addr_t warmboot_addr = virt_to_phys(msm_pm_boot_entry); if (scm_is_mc_boot_available()) { return scm_set_warm_boot_addr_mc_for_all(warmboot_addr); } else { unsigned int flag = 0; if (num_possible_cpus() == 1) flag = SCM_FLAG_WARMBOOT_CPU0; else if (num_possible_cpus() == 2) flag = SCM_FLAG_WARMBOOT_CPU0 | SCM_FLAG_WARMBOOT_CPU1; else if (num_possible_cpus() == 4) flag = SCM_FLAG_WARMBOOT_CPU0 | SCM_FLAG_WARMBOOT_CPU1 | SCM_FLAG_WARMBOOT_CPU2 | SCM_FLAG_WARMBOOT_CPU3; else __WARN(); return scm_set_boot_addr(virt_to_phys(msm_pm_boot_entry), flag); } }
static void __init msm_platform_smp_prepare_cpus(unsigned int max_cpus) { int cpu, map; unsigned int flags = 0; if (scm_is_mc_boot_available()) return msm_platform_smp_prepare_cpus_mc(max_cpus); for_each_present_cpu(cpu) { map = cpu_logical_map(cpu); if (map >= ARRAY_SIZE(cold_boot_flags)) { set_cpu_present(cpu, false); __WARN(); continue; } flags |= cold_boot_flags[map]; } if (scm_set_boot_addr(virt_to_phys(msm_secondary_startup), flags)) pr_warn("Failed to set CPU boot address\n"); /* Mark CPU0 cold boot flag as done */ per_cpu(cold_boot_done, 0) = true; }
int boot_secondary(unsigned int cpu, struct task_struct *idle) { int ret; int flag = 0; unsigned long timeout; pr_debug("Starting secondary CPU %d\n", cpu); /* Set preset_lpj to avoid subsequent lpj recalculations */ preset_lpj = loops_per_jiffy; if (cpu > 0 && cpu < ARRAY_SIZE(cold_boot_flags)) flag = cold_boot_flags[cpu]; else __WARN(); if (per_cpu(cold_boot_done, cpu) == false) { ret = scm_set_boot_addr((void *) virt_to_phys(msm_secondary_startup), flag); if (ret == 0) release_secondary(cpu); else printk(KERN_DEBUG "Failed to set secondary core boot " "address\n"); per_cpu(cold_boot_done, cpu) = true; init_cpu_debug_counter_for_cold_boot(); } /* * set synchronisation state between this boot processor * and the secondary one */ spin_lock(&boot_lock); /* * The secondary processor is waiting to be released from * the holding pen - release it, then wait for it to flag * that it has been released by resetting pen_release. * * Note that "pen_release" is the hardware CPU ID, whereas * "cpu" is Linux's internal ID. */ pen_release = cpu_logical_map(cpu); __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); /* * Send the secondary CPU a soft interrupt, thereby causing * the boot monitor to read the system wide flags register, * and branch to the address found there. */ gic_raise_softirq(cpumask_of(cpu), 1); timeout = jiffies + (1 * HZ); while (time_before(jiffies, timeout)) { smp_rmb(); if (pen_release == -1) break; dmac_inv_range((void *)&pen_release, (void *)(&pen_release+sizeof(pen_release))); udelay(10); } /* * now the secondary core is starting up let it run its * calibrations, then wait for it to finish */ spin_unlock(&boot_lock); return pen_release != -1 ? -ENOSYS : 0; }