void fsl_serdes_init(void) { serdes1_prtcl_map = serdes_init(FSL_SRDS_1, CONFIG_SYS_FSL_CORENET_SERDES_ADDR, FSL_CORENET2_RCWSR4_SRDS1_PRTCL, FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT); serdes2_prtcl_map = serdes_init(FSL_SRDS_2, CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_2 * 0x1000, FSL_CORENET2_RCWSR4_SRDS2_PRTCL, FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT); #ifdef CONFIG_SYS_FSL_SRDS_3 serdes3_prtcl_map = serdes_init(FSL_SRDS_3, CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_3 * 0x1000, FSL_CORENET2_RCWSR4_SRDS3_PRTCL, FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT); #endif #ifdef CONFIG_SYS_FSL_SRDS_4 serdes4_prtcl_map = serdes_init(FSL_SRDS_4, CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_4 * 0x1000, FSL_CORENET2_RCWSR4_SRDS4_PRTCL, FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT); #endif }
void fsl_serdes_init(void) { #ifdef CONFIG_FSL_MC_ENET int i , j; for (i = XFI1, j = 1; i <= XFI8; i++, j++) xfi_dpmac[i] = j; for (i = SGMII1, j = 1; i <= SGMII16; i++, j++) sgmii_dpmac[i] = j; #endif #ifdef CONFIG_SYS_FSL_SRDS_1 serdes_init(FSL_SRDS_1, CONFIG_SYS_FSL_LSCH3_SERDES_ADDR, FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK, FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT, serdes1_prtcl_map); #endif #ifdef CONFIG_SYS_FSL_SRDS_2 serdes_init(FSL_SRDS_2, CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_2 * 0x10000, FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK, FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT, serdes2_prtcl_map); #endif }
void fsl_serdes_init(void) { #ifdef CONFIG_SYS_FSL_SRDS_1 serdes1_prtcl_map = serdes_init(FSL_SRDS_1, CONFIG_SYS_FSL_SERDES_ADDR, RCWSR4_SRDS1_PRTCL_MASK, RCWSR4_SRDS1_PRTCL_SHIFT); #endif #ifdef CONFIG_SYS_FSL_SRDS_2 serdes2_prtcl_map = serdes_init(FSL_SRDS_2, CONFIG_SYS_FSL_SERDES_ADDR + FSL_SRDS_2 * 0x1000, RCWSR4_SRDS2_PRTCL_MASK, RCWSR4_SRDS2_PRTCL_SHIFT); #endif }
void fsl_serdes_init(void) { #ifdef CONFIG_SYS_FSL_SRDS_1 serdes_init(FSL_SRDS_1, CONFIG_SYS_FSL_LSCH3_SERDES_ADDR, FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK, FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT, serdes1_prtcl_map); #endif #ifdef CONFIG_SYS_FSL_SRDS_2 serdes_init(FSL_SRDS_2, CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_2 * 0x10000, FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK, FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT, serdes2_prtcl_map); #endif }