STATIC_PREFIX void debug_write_reg(int argc, char * argv[])
{
unsigned reg;
unsigned val;
if(argc<3)
{
serial_puts("FAIL:Wrong write reg command\n");
return;
}
if(get_dword(argv[1],®)||get_dword(argv[2],&val))
{
serial_puts("FAIL:Wrong reg addr=");
serial_puts(argv[1]);
serial_puts(" or val=");
serial_puts(argv[2]);
serial_putc('\n');
return;
}
serial_puts("OK:Write ");
serial_put_hex(reg,32);
serial_putc('=');
serial_put_hex(val,32);
serial_putc('\n');
writel(val,reg);
}
void mmc_wakeup(void)
{
int stat;
stat = APB_Rd(MMC_LP_CTRL1);
serial_put_hex(stat,32);
f_serial_puts("MMC_LP_CTRL1\n");
wait_uart_empty();
stat = APB_Rd(MMC_CLK_CNTL);
serial_put_hex(stat,32);
f_serial_puts("MMC_CLK_CNTL\n");
wait_uart_empty();
do
{
stat = APB_Rd(UPCTL_STAT_ADDR);
stat &= 0x7;
if(stat == UPCTL_STAT_LOW_POWER) {
APB_Wr(UPCTL_SCTL_ADDR, SCTL_CMD_WAKEUP);
//while(stat != UPCTL_STAT_LOW_POWER);
}
else if(stat == UPCTL_STAT_INIT) {
APB_Wr(UPCTL_SCTL_ADDR, SCTL_CMD_CONFIG);
//while(stat != UPCTL_STAT_CONFIG);
}
else if(stat == UPCTL_STAT_CONFIG) {
APB_Wr(UPCTL_SCTL_ADDR, SCTL_CMD_GO);
//while(stat != UPCTL_STAT_ACCESS);
}
stat = APB_Rd(UPCTL_STAT_ADDR);
stat &= 0x7;
} while(stat != UPCTL_STAT_ACCESS);
}
void mmc_set_power_pin_parameter_4760(int power_pin,u8 off_level)
{
mmc_power_pin = power_pin;
serial_puts("\n power_pin==0X"); serial_put_hex(mmc_power_pin);
power_off_level = off_level;
serial_puts("\n power_pin_level==0X"); serial_put_hex(power_off_level);
}
unsigned int check_sdram(unsigned int saddr, unsigned int size)
{
#if 0
unsigned int addr,err = 0;
serial_puts("\nCheck SDRAM ... \n");
saddr += 0xa0000000;
size += saddr;
serial_put_hex(saddr);
serial_put_hex(size);
saddr &= 0xfffffffc; //must word align
for (addr = saddr; addr < size; addr += 4)
{
*(volatile unsigned int *)addr = addr;
if (*(volatile unsigned int *)addr != addr)
{
serial_put_hex(addr);
err = addr;
}
}
if (err)
serial_puts("Check SDRAM fail!\n");
else
serial_puts("Check SDRAM pass!\n");
return err;
#endif
}
STATIC_PREFIX void show_setting_addr(int argc, char * argv[])
{
#if 0
serial_puts("OK:ADDR=");
serial_put_hex((unsigned)&__ddr_setting,32);
serial_putc(' ');
serial_put_hex((unsigned)&__plls,32);
serial_putc('\n');
#endif
}
void print_key()
{
unsigned reg = 0xc8100000;
unsigned i,data;
for (i=0;i<0x750;i+=4) {
data = readl(reg+i);
serial_put_hex(reg+i,32);
f_serial_puts("=");
serial_put_hex(data,32);
f_serial_puts("\n");
}
}
static void efuse_dump(void){
int loo = 0;
for(loo=0; loo<512; loo++){
if(loo % 16 == 0){
serial_puts("\n");
serial_put_hex(loo, 12);
serial_puts(": ");
}
//efuse_read_byte(loo);
unsigned int tmp_data = efuse_read_byte(loo);
serial_put_hex(tmp_data, 8);
serial_puts(" ");
}
serial_puts("\n");
}
// ls
static file_header_t * get_file_header(char* buffer, int buffer_size, char* name)
{
file_header_t * header = NULL;
int i;
//find first empty header & last full header
for(i=0; i<(HEADER_SECTION_SIZE/sizeof(file_header_t)); i++)
{
file_header_t * header = (file_header_t *)(buffer + i * sizeof(file_header_t));
if (strcmp(header->name, name) == 0)
{
serial_put_hex(header->offset); serial_put_hex(header->size);
return header;
}
}
return NULL;
}
STATIC_PREFIX void debug_read_reg(int argc, char * argv[])
{
unsigned reg;
if(argc<2)
{
serial_puts("FAIL:Wrong read reg command\n");
return;
}
if(get_dword(argv[1],®))
{
serial_puts("FAIL:Wrong reg addr=");
serial_puts(argv[1]);
serial_putc('\n');
return;
}
serial_puts("OK:Read ");
serial_put_hex(reg,32);
serial_putc('=');
serial_put_hex(readl(reg),32);
serial_putc('\n');
}
void musb_platform_init(void)
{
// int i = 0;
// musb->b_dma_share_usb_irq = 1;
// musb->board_set_vbus = jz_musb_set_vbus;
// cpm_set_clock(CGU_OTGCLK, JZ_EXTAL);
#ifdef CONFIG_JZ4760 //jz4760b and jz4770 is not support this bit
/*Clear ECS bit of CPCCR,0:clock source is EXCLK,1:clock source is EXCLK/2*/
REG_CPM_CPCCR &= (~(CPM_CPCCR_ECS));
#endif
/*Clear all bits of USBCDR,0:OTG clock source is pin EXCLK,PLL0 output,divider = 1,12MHZ*/
REG_CPM_USBCDR = 0;
/*Set CE bit of CPCCR,it means frequence is changed immediately*/
REG_CPM_CPCCR |= CPM_CPCCR_CE;
udelay(3);
// cpm_start_clock(CGM_OTG);
/*Clear OTG bit of CLKGR0,0:device can be accessed*/
REG_CPM_CLKGR0 &= (~(CPM_CLKGR0_OTG));
#ifdef DEBUG
serial_puts_info("**************************MUSB REG INFO*******************************\n");
serial_puts_info("CPCCR : ");
serial_put_hex(REG_CPM_CPCCR);
serial_puts_info("USBCDR : ");
serial_put_hex(REG_CPM_USBCDR);
serial_puts_info("CPCCR : ");
serial_put_hex(REG_CPM_CPCCR);
serial_puts_info("CLKGR0 : ");
serial_put_hex(REG_CPM_CLKGR0);
#endif
jz_musb_init();
return;
}
static void tcu_dump_reg_hex(void)
{
TCSM_PCHAR('G');
serial_put_hex(tcu_readl(CH_TCSR(tcu_channel)));
serial_put_hex(tcu_readl(CH_TCNT(tcu_channel)));
serial_put_hex(tcu_readl(TCU_TER));
serial_put_hex(tcu_readl(TCU_TFR));
serial_put_hex(tcu_readl(TCU_TMR));
serial_put_hex(tcu_readl(TCU_TSR));
serial_put_hex(tcu_readl(TCU_TSTR));
TCSM_PCHAR('H');
}
int handler(void)
{
static volatile int i;
i++;
TCSM_PCHAR('h');
TCSM_PCHAR('a');
TCSM_PCHAR('n');
TCSM_PCHAR('d');
TCSM_PCHAR('l');
TCSM_PCHAR('e');
serial_put_hex(i);
xxx_memcopy(dst, src, 4*1024);
return 0;
}
static inline void jz_musb_init(void)
{
/* fil */
REG_CPM_USBVBFIL = 0x80;
#ifdef DEBUG
serial_puts_info("USBVBFIL : ");
serial_put_hex(REG_CPM_USBVBFIL);
#endif
/* rdt */
REG_CPM_USBRDT = 0x96;
/* rdt - filload_en */
REG_CPM_USBRDT |= (1 << 25);
#ifdef DEBUG
serial_puts_info("USBRDT : ");
serial_put_hex(REG_CPM_USBRDT);
#endif
/* TXRISETUNE & TXVREFTUNE. */
REG_CPM_USBPCR &= ~0x3f;
REG_CPM_USBPCR |= 0x35;
// if (is_host_enabled(musb)) {
// jz_musb_set_normal_mode();
// }else
jz_musb_set_device_only_mode();
jz_musb_phy_reset();
#ifdef DEBUG
serial_puts_info("USBPCR : ");
serial_put_hex(REG_CPM_USBPCR);
#endif
return;
}
static int mmc_found(unsigned int msc_clkrt_val)
{
int retries;
u8 *resp;
int ocr;
serial_puts("MMC card found!\n");
resp = mmc_cmd(1, 0x40ff8000, 0x3, MSC_CMDAT_RESPONSE_R3);
retries = 1000;
while (retries-- && resp && !(resp[4] & 0x80)) {
resp = mmc_cmd(1, 0x40300000, 0x3, MSC_CMDAT_RESPONSE_R3);
ocr = (resp[4] << 24) | (resp[3] << 16) | (resp[2] << 8) | resp[1];
serial_puts(" ocr = ");
serial_put_hex(ocr);
sd_mdelay(10);
}
sd_mdelay(10);
if ((resp[4] & 0x80 )== 0x80)
serial_puts("MMC init ok\n");
else {
serial_puts("MMC init fail\n");
return -1;
}
if((resp[4] & 0x60 ) == 0x40)
highcap = 1;
else
highcap =0;
/* try to get card id */
resp = mmc_cmd(2, 0, 0x2, MSC_CMDAT_RESPONSE_R2);
serial_puts("CID=");
serial_dump_data(resp, 15);
resp = mmc_cmd(3, 0x10, 0x1, MSC_CMDAT_RESPONSE_R1);
REG_MSC_CLKRT = msc_clkrt_val; /* 16/1 MHz */
resp = mmc_cmd(7, 0x10, 0x1, MSC_CMDAT_RESPONSE_R1);
if(BUS_WIDTH == 2) {
resp = mmc_cmd(6, 0x3b70101, 0x441, MSC_CMDAT_RESPONSE_R1);
}
else if(BUS_WIDTH == 0) {
resp = mmc_cmd(6, 0x3b30001, 0x41, MSC_CMDAT_RESPONSE_R1);
}
return 0;
}
STATIC_PREFIX short retry_micron_handle(unsigned retry_cnt)
{
serial_puts("enter retry_cnt=0x");
serial_put_hex(retry_cnt,32);
serial_puts("\n");
writel(CE0 | CLE | 0xef,P_NAND_CMD);
writel(CE0 | IDLE,P_NAND_CMD);
writel(CE0 | ALE | 0x89,P_NAND_CMD);
writel(CE0 | IDLE,P_NAND_CMD);
writel(CE0 | DWR | (retry_cnt + 1),P_NAND_CMD);
writel(CE0 | IDLE,P_NAND_CMD);
writel(CE0 | DWR | 0,P_NAND_CMD);
writel(CE0 | IDLE,P_NAND_CMD);
writel(CE0 | DWR | 0,P_NAND_CMD);
writel(CE0 | IDLE,P_NAND_CMD);
writel(CE0 | DWR | 0,P_NAND_CMD);
writel(CE0 | IDLE,P_NAND_CMD);
return 0;
}
void ddr_data_training(void) {
int stat;
//start trainning.
// DDR PHY initialization
// UPCTL enter cfg mode.
MMC_Wr(UPCTL_SCTL_ADDR, 1); // init: 0, cfg: 1, go: 2, sleep: 3, wakeup: 4
//while ((MMC_Rd(UPCTL_STAT_ADDR) & 0x7 ) != 3 ) {}
MMC_Wr( PUB_DTAR_ADDR, (0xFc0 | (0xFFFF <<12) | (7 << 28))); //let training address is 0x9fffff00;
MMC_Wr( PUB_PIR_ADDR, 0x189);
//MMC_Wr( PUB_PIR_ADDR, 0x69); //no training
//DDR3_SDRAM_INIT_WAIT :
while( !(MMC_Rd(PUB_PGSR_ADDR & 1))) {}
//check data training result
//check ZQ calibraration status.
stat = MMC_Rd(PUB_ZQ0SR0_ADDR);
serial_put_hex(stat,32);
f_serial_puts(" PUB_ZQ0SR0\n");
stat = MMC_Rd(PUB_ZQ0SR1_ADDR);
serial_put_hex(stat,32);
f_serial_puts(" PUB_ZQ0SR1\n");
//check data training result.
stat = MMC_Rd(PUB_DX0GSR0_ADDR);
serial_put_hex(stat,32);
f_serial_puts(" PUB_DX0GSR0\n");
wait_uart_empty();
stat = MMC_Rd(PUB_DX1GSR0_ADDR);
serial_put_hex(stat,32);
f_serial_puts(" PUB_DX1GSR0\n");
wait_uart_empty();
stat = MMC_Rd(PUB_DX2GSR0_ADDR);
serial_put_hex(stat,32);
f_serial_puts(" PUB_DX2GSR0\n");
wait_uart_empty();
stat = MMC_Rd(PUB_DX3GSR0_ADDR);
serial_put_hex(stat,32);
f_serial_puts(" PUB_DX3GSR0\n");
wait_uart_empty();
dbg_out("d",9);
MMC_Wr(UPCTL_SCTL_ADDR, 2); // init: 0, cfg: 1, go: 2, sleep: 3, wakeup: 4
//while ((MMC_Rd(UPCTL_STAT_ADDR) & 0x7 ) != 3 ) {}
}
/**
* This functions delegates vendor ctrl request.
*/
void do_vendor_request( pcd_struct_t *_pcd, struct usb_ctrlrequest * ctrl)
{
int value =0;
u16 w_index = ctrl->wIndex;
u16 w_value = ctrl->wValue;
u16 w_length = ctrl->wLength;
switch (ctrl->bRequest) {
case AM_REQ_WRITE_MEM:
if (ctrl->bRequestType != (USB_DIR_OUT | USB_TYPE_VENDOR |
USB_RECIP_DEVICE))
break;
USB_DBG("--am req write memory\n");
value = (w_value << 16) + w_index;
USB_DBG("addr = 0x%08X, size = %d\n\n",value,w_length);
_pcd->buf = (char *)value; // copy to dst memory directly
_pcd->length = w_length;
break;
case AM_REQ_READ_MEM:
if (ctrl->bRequestType != (USB_DIR_IN | USB_TYPE_VENDOR |
USB_RECIP_DEVICE))
break;
value = (w_value << 16) + w_index;
usb_memcpy((char *)buff,(char*)value,w_length);
_pcd->buf = buff;
_pcd->length = w_length;
break;
case AM_REQ_READ_AUX:
if (ctrl->bRequestType != (USB_DIR_IN | USB_TYPE_VENDOR |
USB_RECIP_DEVICE))
break;
unsigned int data = 0;
value = (w_value << 16) + w_index;
//data = _lr(value);
*(unsigned int *)buff = data;
_pcd->buf = buff;
_pcd->length = w_length;
break;
case AM_REQ_FILL_MEM:
case AM_REQ_WRITE_AUX:
case AM_REQ_MODIFY_MEM:
if (ctrl->bRequestType != (USB_DIR_OUT | USB_TYPE_VENDOR |
USB_RECIP_DEVICE))
break;
_pcd->buf = buff;
_pcd->length = w_length;
break;
case AM_REQ_RUN_IN_ADDR:
if (ctrl->bRequestType != (USB_DIR_OUT | USB_TYPE_VENDOR |
USB_RECIP_DEVICE))
break;
value = (w_value << 16) + w_index;
USB_DBG("--am req run in addr %p\n\n",value);
_pcd->buf = buff;
_pcd->length = w_length;
break;
case AM_REQ_WR_LARGE_MEM:
value = 1;
case AM_REQ_RD_LARGE_MEM:
USB_DBG("--am req large %s mem \n\n",value?"write":"read");
_pcd->bulk_len = w_value; // block length
_pcd->bulk_num = w_index; // number of block
_pcd->buf = buff;
_pcd->length = w_length;
break;
case AM_REQ_IDENTIFY_HOST:
buff[0] = USB_ROM_VER_MAJOR;
buff[1] = USB_ROM_VER_MINOR;
buff[2] = USB_ROM_STAGE_MAJOR;
buff[3] = USB_ROM_STAGE_MINOR;
_pcd->buf = buff;
_pcd->length = w_length;
need_check_timeout = 0;
break;
case AM_REQ_TPL_CMD:
case AM_REQ_TPL_STAT:
serial_puts("w_length=");
serial_put_hex(w_length, 32);
_pcd->buf = buff;
_pcd->length = w_length;
break;
default:
USB_ERR("--unknown vendor req %02x.%02x v%04x i%04x l%u\n",
ctrl->bRequestType, ctrl->bRequest,
w_value, w_index, w_length);
break;
}
return;
}
void nand_boot(int nand_boot_select)
{
unsigned int offset, size;
void (*kernel)(int, char **, char *);
int i;
static u32 *param_addr = 0;
static u8 *tmpbuf = 0;
static u8 cmdline[256] = CFG_CMDLINE;
serial_puts_info("Enter nand_boot routine ...\n");
switch (nand_boot_select) {
case NORMAL_BOOT:
offset = CFG_BOOT_OFFS;
size = CFG_BOOT_SIZE;
#ifdef BOOTARGS_NORMAL
strcpy((char *)cmdline, BOOTARGS_NORMAL);
#endif
serial_puts_info("Normal boot ...\n");
break;
case RECOVERY_BOOT:
offset = CFG_RECOVERY_OFFS;
size = CFG_RECOVERY_SIZE;
#ifdef BOOTARGS_RECOVERY
strcpy((char *)cmdline, BOOTARGS_RECOVERY);
#endif
serial_puts_info("Recovery boot ...\n");
break;
#if defined(CONFIG_JZ4760_PT701_8)
case PRETEST_BOOT:
offset = CFG_PRETEST_OFFS;
size = CFG_PRETEST_SIZE;
serial_puts_info("Pretest boot ...\n");
break;
#endif
default:
serial_puts_info("Get nand boot select failed, defualt normal boot ...\n");
offset = CFG_BOOT_OFFS;
size = CFG_BOOT_SIZE;
break;
}
serial_puts_info("Load kernel from NAND ...\n");
/* Load kernel and ramdisk */
do_nand(offset,CFG_NAND_PAGE_SIZE,(u8 *)CFG_KERNEL_DST);
struct boot_img_hdr *bootimginfo;
int kernel_actual;
int ramdisk_actual;
unsigned int page_mask;
if(2048 < sizeof(struct boot_img_hdr)){
serial_puts_info("size too small");
}
bootimginfo = (struct boot_img_hdr *)CFG_KERNEL_DST;
page_mask = CFG_NAND_PAGE_SIZE - 1;
kernel_actual = (bootimginfo->kernel_size + page_mask) & (~page_mask);
ramdisk_actual = (bootimginfo->ramdisk_size + page_mask) & (~page_mask);
size = kernel_actual + ramdisk_actual + M; // ' + M' to make sure including the special data.
do_nand(offset + CFG_NAND_PAGE_SIZE,
size, (u8 *)(CFG_KERNEL_DST + CFG_NAND_PAGE_SIZE));
#ifdef CONFIG_SECURITY_ENABLE
// Special data is 4M from head.
if(data_verify((unsigned char *)CFG_KERNEL_DST, 4 * M, ENV_BOOTLOADER) < 0) {
serial_puts_spl("kernel verify failed, power off\n");
//powerdown();
while(1);
}
#endif
#if 0
serial_puts_info("CRC32 = 0x");
serial_put_hex(CRC_32(CFG_KERNEL_DST,2973696));
serial_put_hex(*((unsigned int *)(CFG_KERNEL_DST+0)));
serial_put_hex(*((unsigned int *)(CFG_KERNEL_DST+4)));
serial_put_hex(*((unsigned int *)(CFG_KERNEL_DST+8)));
serial_put_hex(*((unsigned int *)(CFG_KERNEL_DST+12)));
#endif
serial_puts_info("Prepare kernel parameters ...\n");
/* init kernel, ramdisk and prepare parameters */
if (init_boot_linux((unsigned char*)CFG_KERNEL_DST, size) == 0) {
serial_puts_info("Jump to kernel start Addr 0x");
dump_uint(CFG_KERNEL_DST);
serial_puts("\n\n");
kernel = (void (*)(int, char **, char *))CFG_KERNEL_DST;
flush_cache_all();
#if CONFIG_XBOOT_LOGO_FILE
//__lcd_display_off();
#endif
/* Jump to kernel image */
(*kernel)(2, (char **)(PARAM_BASE + 16), (char *)PARAM_BASE);
serial_puts_info("We should not come here ... \n");
} else
serial_puts_info("Magic number error,boot error...\n");
}
int mmc_init_4760(unsigned int msc_clkrt_val)
{
serial_puts("\n msc_clkrt_val==0X"); serial_put_hex(msc_clkrt_val);
return mmc_init(msc_clkrt_val);
}
STATIC_PREFIX
datum *
memTestDevice(volatile datum * baseAddress, unsigned long nBytes)
{
unsigned long offset;
unsigned long nWords = nBytes / sizeof(datum);
datum pattern;
datum antipattern;
serial_puts("Total Size");serial_put_dword(nBytes);
/*
* Fill memory with a known pattern.
*/
for (pattern = 1, offset = 0; offset < nWords; pattern++, offset++)
{
baseAddress[offset] = pattern;
#ifdef AML_DEBUG_ROM
if(((offset+1)&0x3ffff)==0)
{
serial_putc('\r');serial_put_hex((offset+1)<<2,32);
writel(0,P_WATCHDOG_RESET);
}
#endif
}
serial_puts(" Stage 1 finish\n");
// serial_putc('\n');
/*
* Check each location and invert it for the second pass.
*/
for (pattern = 1, offset = 0; offset < nWords; pattern++, offset++)
{
if (baseAddress[offset] != pattern)
{
return ((datum *) &baseAddress[offset]);
}
antipattern = ~pattern;
baseAddress[offset] = antipattern;
#ifdef AML_DEBUG_ROM
if(((offset+1)&0x3ffff)==0)
{
writel(0,P_WATCHDOG_RESET);
serial_putc('\r');serial_put_hex((offset+1)<<2,32);
}
#endif
}
serial_puts(" Stage 2 finish\n");
/*
* Check each location for the inverted pattern and zero it.
*/
for (pattern = 1, offset = 0; offset < nWords; pattern++, offset++)
{
antipattern = ~pattern;
if (baseAddress[offset] != antipattern)
{
return ((datum *) &baseAddress[offset]);
}
#ifdef AML_DEBUG_ROM
if(((offset+1)&0x3ffff)==0)
{
writel(0,P_WATCHDOG_RESET);
serial_putc('\r');serial_put_hex((offset+1)<<2,32);
}
#endif
}
#undef AML_DEBUG_ROM
serial_puts(" Stage 3 finish\n");
return (NULL);
} /* memTestDevice() */
int main(void)
{
unsigned cmd;
char c;
p_arc_pwr_op = &arc_pwr_op;
timer_init();
arc_pwr_register((struct arc_pwr_op *)p_arc_pwr_op);//init arc_pwr_op
arc_param->serial_disable=0;
serial_put_hex(readl(P_AO_RTI_STATUS_REG1),32);
writel(0,P_AO_RTI_STATUS_REG1);
f_serial_puts("sleep .......\n");
arc_param->serial_disable=0;
while(1){
cmd = readl(P_AO_RTI_STATUS_REG0);
if(cmd == 0)
{
delay_ms(10);
continue;
}
c = (char)cmd;
if(c == 't')
{
init_I2C();
// copy_reboot_code();
#ifdef CONFIG_MESON_TRUSTZONE
copy_reboot_code_temp(temp_arm_base, sizeof(temp_arm_base));
#endif
enter_power_down();
//test_arc_core();
break;
}
else if(c == 'q')
{
f_serial_puts(" - quit command loop\n");
writel(0,P_AO_RTI_STATUS_REG0);
break;
}
else
{
f_serial_puts(" - cmd no support (ARC)\n");
}
//command executed
writel(0,P_AO_RTI_STATUS_REG0);
}
// asm("SLEEP");
while(1){
// udelay__(600);
cmd = readl(P_AO_RTI_STATUS_REG1);
c = (char)cmd;
// f_serial_puts("REG2=");
// serial_put_hex(readl(P_AO_RTI_STATUS_REG2),32);
if(c == 0)
{
udelay__(6000);
cmd = readl(P_AO_RTI_STATUS_REG1);
c = (char)cmd;
if((c == 0)||(c!='r'))
{
#ifdef _UART_DEBUG_COMMUNICATION_
serial_put_hex(cmd,32);
f_serial_puts(" arm boot fail\n\n");
wait_uart_empty();
#endif
#if 0 //power down
cmd = readl(P_AO_GPIO_O_EN_N);
cmd &= ~(1<<6);
cmd &= ~(1<<22);
writel(cmd,P_AO_GPIO_O_EN_N);
#endif
}
} else if ( cmd == 1 )
{
serial_put_hex(cmd,32);
f_serial_puts(" ARM has started running\n");
wait_uart_empty();
} else if ( cmd == 2 )
{
serial_put_hex(cmd,32);
f_serial_puts(" Reenable SEC\n");
wait_uart_empty();
}
else if(c=='r')
{
f_serial_puts("arm boot succ\n");
wait_uart_empty();
asm(".long 0x003f236f"); //add sync instruction.
asm("flag 1");
asm("nop");
asm("nop");
asm("nop");
}
else
{
#ifdef _UART_DEBUG_COMMUNICATION_
serial_put_hex(cmd,32);
f_serial_puts(" arm unkonw state\n");
wait_uart_empty();
#endif
}
//cmd='f';
//writel(cmd,P_AO_RTI_STATUS_REG1);
}
return 0;
}
void enter_power_down()
{
int i;
unsigned int uboot_cmd_flag=readl(P_AO_RTI_STATUS_REG2);//u-boot suspend cmd flag
unsigned int vcin_state = 0;
int voltage = 0;
int axp_ocv = 0;
int wdt_flag;
// First, we disable all memory accesses.
f_serial_puts("step 1\n");
asm(".long 0x003f236f"); //add sync instruction.
store_restore_plls(0);
f_serial_puts("ddr self-refresh\n");
wait_uart_empty();
ddr_self_refresh();
f_serial_puts("CPU off...\n");
wait_uart_empty();
cpu_off();
f_serial_puts("CPU off done\n");
wait_uart_empty();
#ifdef CONFIG_CEC_WAKEUP
hdmi_cec_func_config = readl(P_AO_DEBUG_REG0);
f_serial_puts("CEC M8:uboot: P_AO_DEBUG_REG0:\n");
serial_put_hex(hdmi_cec_func_config,32);
f_serial_puts("\n");
#endif
if(p_arc_pwr_op->power_off_at_24M)
p_arc_pwr_op->power_off_at_24M();
#ifdef CONFIG_M201_COSTDOWN
/* for led */
clrbits_le32(P_AO_GPIO_O_EN_N,1<<18);
setbits_le32(P_AO_GPIO_O_EN_N,1<<29);
#endif
// while(readl(0xc8100000) != 0x13151719)
// {}
//non 32k crystal oscillator platform DONT enter 32k in suspend mode
#ifndef CONFIG_NON_32K
switch_24M_to_32K();
#endif
if(p_arc_pwr_op->power_off_at_32K_1)
p_arc_pwr_op->power_off_at_32K_1();
if(p_arc_pwr_op->power_off_at_32K_2)
p_arc_pwr_op->power_off_at_32K_2();
// gate off: bit0: REMOTE; bit3: UART
#ifndef CONFIG_NON_32K
writel(readl(P_AO_RTI_GEN_CNTL_REG0)&(~(0x8)),P_AO_RTI_GEN_CNTL_REG0);
#endif
if(uboot_cmd_flag == 0x87654321)//u-boot suspend cmd flag
{
if(p_arc_pwr_op->power_off_ddr15)
p_arc_pwr_op->power_off_ddr15();
}
wdt_flag=readl(P_WATCHDOG_TC)&(1<<19);
if(wdt_flag)
writel(readl(P_WATCHDOG_TC)&(~(1<<19)),P_WATCHDOG_TC);
#if 1
vcin_state = p_arc_pwr_op->detect_key(uboot_cmd_flag);
#else
for(i=0;i<10;i++)
{
udelay__(1000);
//udelay(1000);
}
#endif
if(uboot_cmd_flag == 0x87654321)//u-boot suspend cmd flag
{
if(p_arc_pwr_op->power_on_ddr15)
p_arc_pwr_op->power_on_ddr15();
}
if(wdt_flag)
writel((6*7812|((1<<16)-1))|(1<<19),P_WATCHDOG_TC);
// gate on: bit0: REMOTE; bit3: UART
writel(readl(P_AO_RTI_GEN_CNTL_REG0)|0x8,P_AO_RTI_GEN_CNTL_REG0);
if(p_arc_pwr_op->power_on_at_32K_2)
p_arc_pwr_op->power_on_at_32K_2();
if(p_arc_pwr_op->power_on_at_32K_1)
p_arc_pwr_op->power_on_at_32K_1();
#ifndef CONFIG_NON_32K
switch_32K_to_24M();
#endif
// power on even more domains
if(p_arc_pwr_op->power_on_at_24M)
p_arc_pwr_op->power_on_at_24M();
uart_reset();
f_serial_puts("step 8: ddr resume\n");
wait_uart_empty();
ddr_resume();
#ifdef CONFIG_M201_COSTDOWN
/* for led */
clrbits_le32(P_AO_GPIO_O_EN_N,1<<29);
setbits_le32(P_AO_GPIO_O_EN_N,1<<18);
#endif
f_serial_puts("restore pll\n");
wait_uart_empty();
store_restore_plls(1);//Before switch back to clk81, we need set PLL
if (uboot_cmd_flag == 0x87654321 && (vcin_state == FLAG_WAKEUP_PWROFF)) {
/*
* power off system before ARM is restarted
*/
f_serial_puts("no extern power shutdown\n");
wait_uart_empty();
p_arc_pwr_op->shut_down();
do {
udelay__(2000 * 100);
f_serial_puts("wait shutdown...\n");
wait_uart_empty();
}while(1);
}
#ifdef CONFIG_MESON_TRUSTZONE
copy_reboot_code(temp_arm_base);
#else
copy_reboot_code(NULL);
#endif
writel(vcin_state,P_AO_RTI_STATUS_REG2);
f_serial_puts("restart arm\n");
wait_uart_empty();
restart_arm();
if (uboot_cmd_flag == 0x87654321) {
writel(0,P_AO_RTI_STATUS_REG2);
writel(readl(P_AO_RTI_PWR_CNTL_REG0)|(1<<4),P_AO_RTI_PWR_CNTL_REG0);
clrbits_le32(P_HHI_SYS_CPU_CLK_CNTL,1<<19);
//writel(10,0xc1109904);
writel(1<<19|1<<24|10,0xc1109900);
do{udelay__(200);f_serial_puts("wait reset...\n");wait_uart_empty();}while(1);
}
}
int main(void)
{
unsigned cmd;
char c;
int i = 0,j;
timer_init();
#ifdef POWER_OFF_VDDIO
f_serial_puts("sleep ... off\n");
#else
f_serial_puts("sleep7 .......\n");
#endif
while(1){
cmd = readl(P_AO_RTI_STATUS_REG0);
if(cmd == 0)
{
delay_ms(10);
continue;
}
c = (char)cmd;
if(c == 't')
{
#if (defined(POWER_OFF_VDDIO) || defined(POWER_OFF_HDMI_VCC) || defined(POWER_OFF_AVDD33) || defined(POWER_OFF_AVDD25))
init_I2C();
#endif
copy_reboot_code();
enter_power_down();
//test_arc_core();
break;
}
else if(c == 'q')
{
serial_puts(" - quit command loop\n");
writel(0,P_AO_RTI_STATUS_REG0);
break;
}
else
{
serial_puts(" - cmd no support (ARC)\n");
}
//command executed
writel(0,P_AO_RTI_STATUS_REG0);
}
while(1){
udelay(6000);
cmd = readl(P_AO_RTI_STATUS_REG1);
c = (char)cmd;
if(c == 0)
{
udelay(6000);
cmd = readl(P_AO_RTI_STATUS_REG1);
c = (char)cmd;
if((c == 0)||(c!='r'))
{
#ifdef _UART_DEBUG_COMMUNICATION_
serial_put_hex(cmd,32);
f_serial_puts(" arm boot fail\n\n");
wait_uart_empty();
#endif
#if 0 //power down
cmd = readl(P_AO_GPIO_O_EN_N);
cmd &= ~(1<<6);
cmd &= ~(1<<22);
writel(cmd,P_AO_GPIO_O_EN_N);
#endif
}
}
else if(c=='r')
{
writel(0,0xc8100030);
#ifdef _UART_DEBUG_COMMUNICATION_
//f_serial_puts("arm boot succ\n");
//wait_uart_empty();
#endif
}
else
{
#ifdef _UART_DEBUG_COMMUNICATION_
serial_put_hex(cmd,32);
f_serial_puts(" arm unkonw state\n");
wait_uart_empty();
#endif
}
//cmd='f';
//writel(cmd,P_AO_RTI_STATUS_REG1);
asm(".long 0x003f236f"); //add sync instruction.
//asm("SLEEP");
asm("FLAG 1");//halt mode
}
return 0;
}
void c_main(void)
{
load_args();
if (fw_args->debug_ops > 0) {
do_debug();
return ;
}
switch (CPU_ID) {
case 0x4740:
gpio_init_4740();
pll_init_4740();
serial_init();
sdram_init_4740();
break;
case 0x4760:
gpio_init_4760();
cpm_start_all_4760();
serial_init();
pll_init_4760();
sdram_init_4760();
break;
default:
return;
}
#if 1
serial_puts("Setup xburst CPU args as:\n");
serial_put_hex(CPU_ID);
serial_put_hex(CFG_EXTAL);
serial_put_hex(CFG_CPU_SPEED);
serial_put_hex(PHM_DIV);
serial_put_hex(fw_args->use_uart);
serial_put_hex(CONFIG_BAUDRATE);
serial_put_hex(SDRAM_BW16);
serial_put_hex(SDRAM_BANK4);
serial_put_hex(SDRAM_ROW);
serial_put_hex(SDRAM_COL);
serial_put_hex(REG_CPM_CPCCR);
#endif
serial_puts("xburst stage1 run finish !\n");
if (CPU_ID == 0x4760) {
__asm__ (
"li $31, 0xbfc012e0 \n\t"
"jr $31 \n\t "
);
}
}
void init_pctl(void)
{
int nTempVal;
int stat;
MMC_Wr(MMC_PHY_CTRL,v_mmc_phy_ctrl);
/* MMC_Wr(UPCTL_DLLCR9_ADDR, v_dllcr9); //2a8
MMC_Wr(UPCTL_IOCR_ADDR, v_iocr); //248
MMC_Wr(UPCTL_PHYCR_ADDR, 2);//????
*/
//wait to DDR PLL lock.
//while (!(MMC_Rd(MMC_CLK_CNTL) & (1<<29)) ) {}
//dbg_out("d",1);
//Enable DDR DLL clock input from PLL.
// MMC_Wr(MMC_CLK_CNTL, 0xc0000080); // @@@ select the final mux from PLL output directly.
// MMC_Wr(MMC_CLK_CNTL, 0xc00000c0);
//enable the clock.
//MMC_Wr(MMC_CLK_CNTL, v_mmc_clk_cntl);
// release the DDR DLL reset pin.
// MMC_Wr( MMC_SOFT_RST, 0xffff);
//__udelay(10);
//UPCTL memory timing registers
MMC_Wr(UPCTL_TOGCNT1U_ADDR, v_t_1us_pck); //1us = nn cycles.
MMC_Wr(UPCTL_TOGCNT100N_ADDR, v_t_100ns_pck);//100ns = nn cycles.
MMC_Wr(UPCTL_TINIT_ADDR, v_t_init_us); //200us.
// MMC_Wr(UPCTL_TRSTH_ADDR, 2); // 0 for ddr2; 500 for ddr3. 2 for simulation.
MMC_Wr(UPCTL_TRSTH_ADDR, v_t_rsth_us); // 0 for ddr2; 2 for simulation; 500 for ddr3. //???
MMC_Wr(UPCTL_TRSTL_ADDR, v_t_rstl_us); //?????
MMC_Wr(UPCTL_MCFG_ADDR,v_mcfg);
MMC_Wr(UPCTL_DFIODTCFG_ADDR, v_dfiodrcfg_adr);//add for Eric fine-tune
//configure DDR PHY PUBL registers.
// 2:0 011: DDR3 mode. 100: LPDDR2 mode.
// 3: 8 bank.
MMC_Wr(PUB_DCR_ADDR, 0x3 | (1 << 3));
MMC_Wr(PUB_PGCR_ADDR, 0x01842e04); //PUB_PGCR_ADDR: c8001008
MMC_Wr( PUB_MR0_ADDR,v_msr0);
MMC_Wr( PUB_MR1_ADDR,v_msr1);
MMC_Wr( PUB_MR2_ADDR,v_msr2);
MMC_Wr( PUB_MR3_ADDR,v_msr3);
// MMC_Wr( PUB_MR3_ADDR,0);
MMC_Wr(PUB_DTPR0_ADDR,v_pub_dtpr0);
MMC_Wr(PUB_DTPR1_ADDR,v_pub_dtpr1);
MMC_Wr(PUB_DTPR2_ADDR,v_pub_dtpr2);
MMC_Wr(PUB_PTR0_ADDR,v_pub_ptr0);
// MMC_Wr( PUB_PIR_ADDR, 0x17);//Add By Dai
__udelay(50);
//wait PHY DLL LOCK
while(!(MMC_Rd( PUB_PGSR_ADDR) & 1)) {}
dbg_out("d",2);
// configure DDR3_rst pin.
MMC_Wr( PUB_ACIOCR_ADDR, MMC_Rd( PUB_ACIOCR_ADDR) & 0xdfffffff );
MMC_Wr( PUB_DSGCR_ADDR, MMC_Rd(PUB_DSGCR_ADDR) & 0xffffffef);
//MMC_Wr( PUB_ZQ0CR1_ADDR, 0x18); //???????
//MMC_Wr( PUB_ZQ0CR1_ADDR, 0x7b); //???????
#ifdef CONFIG_TURN_OFF_ODT
if(v_zq0cr0 & (1<<28))
MMC_Wr( PUB_ZQ0CR0_ADDR, v_zq0cr0);
else
MMC_Wr( PUB_ZQ0CR1_ADDR, v_zq0cr1);
if(v_cmdzq)
MMC_Wr( MMC_CMDZQ_CTRL, v_cmdzq);
#else
MMC_Wr( PUB_ZQ0CR1_ADDR, v_zq0cr1);
#endif
//for simulation to reduce the init time.
// MMC_Wr(PUB_PTR1_ADDR,v_pub_ptr1);
// MMC_Wr(PUB_PTR2_ADDR,v_pub_ptr2);
// MMC_Wr( PUB_PIR_ADDR, 0x9);//Add By Dai
__udelay(20);
//wait DDR3_ZQ_DONE:
#ifndef CONFIG_TURN_OFF_ODT
while( !(MMC_Rd( PUB_PGSR_ADDR) & (1<< 2))) {}
#endif
dbg_out("d",3);
// wait DDR3_PHY_INIT_WAIT :
#ifndef CONFIG_TURN_OFF_ODT
while (!(MMC_Rd(PUB_PGSR_ADDR) & 1 )) {}
#endif
dbg_out("d",4);
// Monitor DFI initialization status.
#ifndef CONFIG_TURN_OFF_ODT
while(!(MMC_Rd(UPCTL_DFISTSTAT0_ADDR) & 1)) {}
#endif
dbg_out("d",5);
MMC_Wr(UPCTL_POWCTL_ADDR, 1);
while(!(MMC_Rd( UPCTL_POWSTAT_ADDR & 1) )) {}
dbg_out("d",6);
// initial upctl ddr timing.
MMC_Wr(UPCTL_TREFI_ADDR, v_t_refi_100ns); // 7800ns to one refresh command.
// wr_reg UPCTL_TREFI_ADDR, 78
MMC_Wr(UPCTL_TMRD_ADDR, v_t_mrd);
//wr_reg UPCTL_TMRD_ADDR, 4
MMC_Wr(UPCTL_TRFC_ADDR, v_t_rfc); //64: 400Mhz. 86: 533Mhz.
// wr_reg UPCTL_TRFC_ADDR, 86
MMC_Wr(UPCTL_TRP_ADDR, v_t_rp); // 8 : 533Mhz.
//wr_reg UPCTL_TRP_ADDR, 8
MMC_Wr(UPCTL_TAL_ADDR, v_t_al);
//wr_reg UPCTL_TAL_ADDR, 0
// MMC_Wr(UPCTL_TCWL_ADDR, v_t_cl-1 + v_t_al);
MMC_Wr(UPCTL_TCWL_ADDR, v_t_cwl);
//wr_reg UPCTL_TCWL_ADDR, 6
MMC_Wr(UPCTL_TCL_ADDR, v_t_cl); //6: 400Mhz. 8 : 533Mhz.
// wr_reg UPCTL_TCL_ADDR, 8
MMC_Wr(UPCTL_TRAS_ADDR, v_t_ras); //16: 400Mhz. 20: 533Mhz.
// wr_reg UPCTL_TRAS_ADDR, 20
MMC_Wr(UPCTL_TRC_ADDR, v_t_rc); //24 400Mhz. 28 : 533Mhz.
//wr_reg UPCTL_TRC_ADDR, 28
MMC_Wr(UPCTL_TRCD_ADDR, v_t_rcd); //6: 400Mhz. 8: 533Mhz.
// wr_reg UPCTL_TRCD_ADDR, 8
MMC_Wr(UPCTL_TRRD_ADDR, v_t_rrd); //5: 400Mhz. 6: 533Mhz.
//wr_reg UPCTL_TRRD_ADDR, 6
MMC_Wr(UPCTL_TRTP_ADDR, v_t_rtp);
// wr_reg UPCTL_TRTP_ADDR, 4
MMC_Wr(UPCTL_TWR_ADDR, v_t_wr);
// wr_reg UPCTL_TWR_ADDR, 8
MMC_Wr(UPCTL_TWTR_ADDR, v_t_wtr);
//wr_reg UPCTL_TWTR_ADDR, 4
MMC_Wr(UPCTL_TEXSR_ADDR, v_t_exsr);
//wr_reg UPCTL_TEXSR_ADDR, 200
MMC_Wr(UPCTL_TXP_ADDR, v_t_xp);
//wr_reg UPCTL_TXP_ADDR, 4
MMC_Wr(UPCTL_TDQS_ADDR, v_t_dqs);
// wr_reg UPCTL_TDQS_ADDR, 2
MMC_Wr(UPCTL_TRTW_ADDR, v_t_trtw);
//wr_reg UPCTL_TRTW_ADDR, 2
//MMC_Wr(UPCTL_TCKSRE_ADDR, 5);
MMC_Wr(UPCTL_TCKSRE_ADDR, v_t_cksre);
//wr_reg UPCTL_TCKSRE_ADDR, 5
//MMC_Wr(UPCTL_TCKSRX_ADDR, 5);
MMC_Wr(UPCTL_TCKSRX_ADDR, v_t_cksrx);
//wr_reg UPCTL_TCKSRX_ADDR, 5
MMC_Wr(UPCTL_TMOD_ADDR, v_t_mod);
//wr_reg UPCTL_TMOD_ADDR, 8
//MMC_Wr(UPCTL_TCKE_ADDR, 4);
MMC_Wr(UPCTL_TCKE_ADDR, v_t_cke);
//wr_reg UPCTL_TCKE_ADDR, 4
MMC_Wr(UPCTL_TZQCS_ADDR, 64);
//wr_reg UPCTL_TZQCS_ADDR , 64
// MMC_Wr(UPCTL_TZQCL_ADDR, v_t_zqcl);
MMC_Wr(UPCTL_TZQCL_ADDR, 512);
//wr_reg UPCTL_TZQCL_ADDR , 512
MMC_Wr(UPCTL_TXPDLL_ADDR, 10);
// wr_reg UPCTL_TXPDLL_ADDR, 10
MMC_Wr(UPCTL_TZQCSI_ADDR, 1000);
// wr_reg UPCTL_TZQCSI_ADDR, 1000
MMC_Wr(UPCTL_SCFG_ADDR, 0xf00);
// wr_reg UPCTL_SCFG_ADDR, 0xf00
// MMC_Wr(UPCTL_LPDDR2ZQCFG_ADDR,v_odtcfg); //????
// MMC_Wr(UPCTL_ZQCR_ADDR,v_zqcr); //?????
MMC_Wr( UPCTL_SCTL_ADDR, 1);
while (!( MMC_Rd(UPCTL_STAT_ADDR) & 1)) {
MMC_Wr(UPCTL_SCTL_ADDR, 1);
}
dbg_out("d",7);
//config the DFI interface.
MMC_Wr( UPCTL_PPCFG_ADDR, (0xf0 << 1) );
MMC_Wr( UPCTL_DFITCTRLDELAY_ADDR, 2 );
MMC_Wr( UPCTL_DFITPHYWRDATA_ADDR, 0x1 );
MMC_Wr( UPCTL_DFITPHYWRLAT_ADDR, v_t_cwl -1 ); //CWL -1
MMC_Wr( UPCTL_DFITRDDATAEN_ADDR, v_t_cl - 2 ); //CL -2
MMC_Wr( UPCTL_DFITPHYRDLAT_ADDR, 15 );
MMC_Wr( UPCTL_DFITDRAMCLKDIS_ADDR, 2 );
MMC_Wr( UPCTL_DFITDRAMCLKEN_ADDR, 2 );
MMC_Wr( UPCTL_DFISTCFG0_ADDR, 0x4 );
MMC_Wr( UPCTL_DFITCTRLUPDMIN_ADDR, 0x4000 );
MMC_Wr( UPCTL_DFILPCFG0_ADDR, ( 1 | (7 << 4) | (1 << 8) | (10 << 12) | (12 <<16) | (1 <<24) | ( 7 << 28)));
MMC_Wr( UPCTL_CMDTSTATEN_ADDR, 1);
while (!(MMC_Rd(UPCTL_CMDTSTAT_ADDR) & 1 )) {}
dbg_out("d",8);
//MMC_Wr( PUB_DTAR_ADDR, (0x0 | (0 <<12) | (7 << 28))); //training address is 0x90001800 not safe
//MMC_Wr( PUB_DTAR_ADDR, (0xFc0 | (0xFFFF <<12) | (7 << 28))); //let training address is 0x9fffff00;
MMC_Wr(PUB_DTAR_ADDR,v_dtar);
serial_put_hex(MMC_Rd(PUB_DTAR_ADDR),32);
f_serial_puts(" PUB_DTAR_ADDR\n");
//start trainning.
// DDR PHY initialization
#ifdef CONFIG_TURN_OFF_ODT
if(v_zq0cr0 & (1<<28))
MMC_Wr( PUB_PIR_ADDR, 0x1e1);
else
MMC_Wr( PUB_PIR_ADDR, 0x1e9);
//MMC_Wr( PUB_PIR_ADDR, 0x69); //no training
#else
MMC_Wr( PUB_PIR_ADDR, 0x1e9);
#endif
//DDR3_SDRAM_INIT_WAIT :
while( !(MMC_Rd(PUB_PGSR_ADDR & 1))) {}
dbg_out("d",9);
if(MMC_Rd(PUB_PGSR_ADDR) & (3<<5)){
f_serial_puts("PUB_PGSR=");
serial_put_hex(MMC_Rd(PUB_PGSR_ADDR),8);
f_serial_puts("\n");
#ifdef CONFIG_TURN_OFF_ODT
MMC_Wr( PUB_PIR_ADDR, 0x1e1 | (1<<28));
#else
MMC_Wr( PUB_PIR_ADDR, 0x1e9 | (1<<28));
#endif
while( !(MMC_Rd(PUB_PGSR_ADDR & 1))) {}
dbg_out("d",0x91);
f_serial_puts("PUB_PGSR=");
serial_put_hex(MMC_Rd(PUB_PGSR_ADDR),8);
f_serial_puts("\n");
}
//check ZQ calibraration status.
stat = MMC_Rd(PUB_ZQ0SR0_ADDR);
serial_put_hex(stat,32);
f_serial_puts(" PUB_ZQ0SR0\n");
stat = MMC_Rd(PUB_ZQ0SR1_ADDR);
serial_put_hex(stat,32);
f_serial_puts(" PUB_ZQ0SR1\n");
//check data training result.
stat = MMC_Rd(PUB_DX0GSR0_ADDR);
serial_put_hex(stat,32);
f_serial_puts(" PUB_DX0GSR0\n");
wait_uart_empty();
stat = MMC_Rd(PUB_DX1GSR0_ADDR);
serial_put_hex(stat,32);
f_serial_puts(" PUB_DX1GSR0\n");
wait_uart_empty();
stat = MMC_Rd(PUB_DX2GSR0_ADDR);
serial_put_hex(stat,32);
f_serial_puts(" PUB_DX2GSR0\n");
wait_uart_empty();
stat = MMC_Rd(PUB_DX3GSR0_ADDR);
serial_put_hex(stat,32);
f_serial_puts(" PUB_DX3GSR0\n");
wait_uart_empty();
MMC_Wr(UPCTL_SCTL_ADDR, 2); // init: 0, cfg: 1, go: 2, sleep: 3, wakeup: 4
while ((MMC_Rd(UPCTL_STAT_ADDR) & 0x7 ) != 3 ) {}
dbg_out("d",10);
__udelay(200);
// MMC_Wr(MMC_DDR_CTRL,v_mmc_ddr_ctrl);
// MMC_Wr(MMC_PHY_CTRL,v_mmc_phy_ctrl);
// MMC_Wr(UPCTL_PHYCR_ADDR, 2);
// MMC_Wr(MMC_REQ_CTRL, 0xff ); //enable request in kreboot.s
// udelay(50);
// MMC_Wr(UPCTL_IOCR_ADDR, v_iocr); //248
//traning result
/*
MMC_Wr(UPCTL_RDGR0_ADDR,v_rdgr0);
MMC_Wr(UPCTL_RSLR0_ADDR,v_rslr0);
MMC_Wr(PUB_DX0GSR0_ADDR,v_dx0gsr0);
MMC_Wr(PUB_DX0GSR1_ADDR,v_dx0gsr1);
MMC_Wr(PUB_DX0DQSTR_ADDR,v_dx0dqstr);
MMC_Wr(PUB_DX1GSR0_ADDR,v_dx1gsr0);
MMC_Wr(PUB_DX1GSR1_ADDR,v_dx1gsr1);
MMC_Wr(PUB_DX1DQSTR_ADDR,v_dx1dqstr);
MMC_Wr(PUB_DX2GSR0_ADDR,v_dx2gsr0);
MMC_Wr(PUB_DX2GSR1_ADDR,v_dx2gsr1);
MMC_Wr(PUB_DX2DQSTR_ADDR,v_dx2dqstr);
MMC_Wr(PUB_DX3GSR0_ADDR,v_dx3gsr0);
MMC_Wr(PUB_DX3GSR1_ADDR,v_dx3gsr1);
MMC_Wr(PUB_DX3DQSTR_ADDR,v_dx3dqstr);
MMC_Wr(PUB_DX4GSR0_ADDR,v_dx4gsr0);
MMC_Wr(PUB_DX4GSR1_ADDR,v_dx4gsr1);
MMC_Wr(PUB_DX4DQSTR_ADDR,v_dx4dqstr);
MMC_Wr(PUB_DX5GSR0_ADDR,v_dx5gsr0);
MMC_Wr(PUB_DX5GSR1_ADDR,v_dx5gsr1);
MMC_Wr(PUB_DX5DQSTR_ADDR,v_dx5dqstr);
MMC_Wr(PUB_DX6GSR0_ADDR,v_dx6gsr0);
MMC_Wr(PUB_DX6GSR1_ADDR,v_dx6gsr1);
MMC_Wr(PUB_DX6DQSTR_ADDR,v_dx6dqstr);
MMC_Wr(PUB_DX7GSR0_ADDR,v_dx7gsr0);
MMC_Wr(PUB_DX7GSR1_ADDR,v_dx7gsr1);
MMC_Wr(PUB_DX7DQSTR_ADDR,v_dx7dqstr);
MMC_Wr(PUB_DX8GSR0_ADDR,v_dx8gsr0);
MMC_Wr(PUB_DX8GSR1_ADDR,v_dx8gsr1);
MMC_Wr(PUB_DX8DQSTR_ADDR,v_dx8dqstr);
*/
// MMC_Wr(MMC_REQ_CTRL, 0xff ); Already enable request in kreboot.s
return 0;
}
