/* Early cpumask setup - runs on TP0 */
static void brcmstb_smp_setup(void)
{
__cpu_number_map[0] = 0;
__cpu_logical_map[0] = 0;
set_cpu_possible(0, 1);
set_cpu_present(0, 1);
__cpu_number_map[1] = 1;
__cpu_logical_map[1] = 1;
set_cpu_possible(1, 1);
set_cpu_present(1, 1);
#if defined(CONFIG_BMIPS4380)
/* NBK and weak order flags */
set_c0_brcm_config_0(0x30000);
/*
* MIPS interrupts 0,1 (SW INT 0,1) cross over to the other TP
* MIPS interrupt 2 (HW INT 0) is the TP0 L1 controller output
* MIPS interrupt 3 (HW INT 1) is the TP1 L1 controller output
*/
change_c0_brcm_cmt_intr(0xf8018000, (0x02 << 27) | (0x03 << 15));
#elif defined(CONFIG_BMIPS5000)
/* enable raceless SW interrupts */
set_c0_brcm_config(0x03 << 22);
/* clear any pending SW interrupts */
write_c0_brcm_action(0x2000 | (0 << 9) | (0 << 8));
write_c0_brcm_action(0x2000 | (0 << 9) | (1 << 8));
write_c0_brcm_action(0x2000 | (1 << 9) | (0 << 8));
write_c0_brcm_action(0x2000 | (1 << 9) | (1 << 8));
#endif
}
void bchip_mips_setup(void)
{
/* enable RDHWR, BRDHWR */
set_c0_brcm_config(BIT(17) | BIT(21));
if (kernel_uses_smartmips_rixi) {
/* XI enable */
set_c0_brcm_config(BIT(27));
/* enable MIPS32R2 ROR instruction for XI TLB handlers */
__asm__ __volatile__(
" li $8, 0x5a455048\n"
" .word 0x4088b00f\n" /* mtc0 $8, $22, 15 */
" nop; nop; nop\n"
" .word 0x4008b008\n" /* mfc0 $8, $22, 8 */
" lui $9, 0x0100\n"
" or $8, $9\n"
" .word 0x4088b008\n" /* mtc0 $8, $22, 8 */
: : : "$8", "$9");
}
}
/* Early cpumask setup - runs on TP0 */
void brcmstb_smp_setup(void)
{
int i;
/* 1:1 mapping between logical and physical CPUs */
for (i = 0; i < NR_CPUS; i++) {
cpu_clear(i, cpu_possible_map);
__cpu_number_map[i] = i;
__cpu_logical_map[i] = i;
}
/* Enable TP0, TP1 */
cpu_set(0, cpu_possible_map);
cpu_set(1, cpu_possible_map);
cpu_present_map = cpu_possible_map;
#if defined(CONFIG_BMIPS4380)
/* NBK and weak order flags */
set_c0_brcm_config_0(0x30000);
/*
* MIPS interrupts 0,1 (SW INT 0,1) cross over to the other TP
* MIPS interrupt 2 (HW INT 0) is the TP0 L1 controller output
* MIPS interrupt 3 (HW INT 1) is the TP1 L1 controller output
*/
change_c0_brcm_cmt_intr(0xf8018000, (0x02 << 27) | (0x03 << 15));
#elif defined(CONFIG_BMIPS5000)
/* enable raceless SW interrupts */
set_c0_brcm_config(0x03 << 22);
/* clear any pending SW interrupts */
write_c0_brcm_action(0x2000 | (0 << 9) | (0 << 8));
write_c0_brcm_action(0x2000 | (0 << 9) | (1 << 8));
write_c0_brcm_action(0x2000 | (1 << 9) | (0 << 8));
write_c0_brcm_action(0x2000 | (1 << 9) | (1 << 8));
/* send HW interrupt 0 to TP0, HW interrupt 1 to TP1 */
change_c0_brcm_mode(0x1f << 27, 0x02 << 27);
#endif
}
