Exemple #1
0
phys_size_t fixed_sdram(void)
{
    int i;
    char buf[32];
    fsl_ddr_cfg_regs_t ddr_cfg_regs;
    phys_size_t ddr_size;
    unsigned int lawbar1_target_id;
    ulong ddr_freq, ddr_freq_mhz;

    ddr_freq = get_ddr_freq(0);
    ddr_freq_mhz = ddr_freq / 1000000;

    printf("Configuring DDR for %s MT/s data rate\n",
           strmhz(buf, ddr_freq));

    for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
        if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
                (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
            memcpy(&ddr_cfg_regs,
                   fixed_ddr_parm_0[i].ddr_settings,
                   sizeof(ddr_cfg_regs));
            break;
        }
    }

    if (fixed_ddr_parm_0[i].max_freq == 0)
        panic("Unsupported DDR data rate %s MT/s data rate\n",
              strmhz(buf, ddr_freq));

    ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
    ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN;
    fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);

    /*
     * setup laws for DDR. If not interleaving, presuming half memory on
     * DDR1 and the other half on DDR2
     */
    if (fixed_ddr_parm_0[i].ddr_settings->cs[0].config & 0x20000000) {
        if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
                         ddr_size,
                         LAW_TRGT_IF_DDR_INTRLV) < 0) {
            printf("ERROR setting Local Access Windows for DDR\n");
            return 0;
        }
    } else {
        lawbar1_target_id = LAW_TRGT_IF_DDR_1;
        if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
                         ddr_size,
                         lawbar1_target_id) < 0) {
            printf("ERROR setting Local Access Windows for DDR\n");
            return 0;
        }
    }
    return ddr_size;
}
Exemple #2
0
phys_size_t initdram(int board_type)
{
	phys_size_t dram_size = 0;
	struct cpu_type *cpu;

#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_FSL_BOOT_DDR)
	cpu = gd->cpu;
     
	/* //kosta comment 
	// P1020 and it's derivatives support max 32bit DDR width 
	if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1020_E ||
		cpu->soc_ver == SVR_P1011 || cpu->soc_ver == SVR_P1011_E)
		return (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024) / 2;
	else
		return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
    *///end kosta commetn
	//MPC_BOARD 32 bit memory device
	return (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024) / 2;
		
#endif
	dram_size = fixed_sdram();
	set_ddr_laws(0, dram_size, LAW_TRGT_IF_DDR_1);

	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
	dram_size *= 0x100000;

	puts("DDR: ");
	return dram_size;
}
Exemple #3
0
/* Fixed sdram init -- doesn't use serial presence detect. */
phys_size_t fixed_sdram(void)
{
	sys_info_t sysinfo;
	char buf[32];
	size_t ddr_size;
	fsl_ddr_cfg_regs_t ddr_cfg_regs = {
		.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
		.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
		.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
		.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
		.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
		.cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2,
#endif
		.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3,
		.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0,
		.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1,
		.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2,
		.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
		.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
		.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1,
		.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2,
		.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
		.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL,
		.ddr_data_init = CONFIG_SYS_DDR_DATA_INIT,
		.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL,
		.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
		.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
		.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
		.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
		.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
		.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
		.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
		.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
		.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
	};

	get_sys_info(&sysinfo);
	printf("Configuring DDR for %s MT/s data rate\n",
			strmhz(buf, sysinfo.freq_ddrbus));

	ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;

	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);

	if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
				ddr_size, LAW_TRGT_IF_DDR_1) < 0) {
		printf("ERROR setting Local Access Windows for DDR\n");
		return 0;
	};

	return ddr_size;
}
phys_size_t initdram(int board_type)
{
	phys_size_t dram_size = 0;

	dram_size = fixed_sdram();
	set_ddr_laws(0, dram_size, LAW_TRGT_IF_DDR_1);

	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
	dram_size *= 0x100000;

	puts("DDR: ");
	return dram_size;
}
Exemple #5
0
phys_size_t fixed_sdram (void)
{
    char buf[32];
    fsl_ddr_cfg_regs_t ddr_cfg_regs;
    size_t ddr_size;
    struct cpu_type *cpu;
    ulong ddr_freq, ddr_freq_mhz;

    cpu = gd->arch.cpu;
    /* P1020 and it's derivatives support max 32bit DDR width */
    if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1011) {
        ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2);
    } else {
        ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
    }
#if defined(CONFIG_SYS_RAMBOOT)
    return ddr_size;
#endif
    ddr_freq = get_ddr_freq(0);
    ddr_freq_mhz = ddr_freq / 1000000;

    printf("Configuring DDR for %s MT/s data rate\n",
           strmhz(buf, ddr_freq));

    if(ddr_freq_mhz <= 400)
        memcpy(&ddr_cfg_regs, &ddr_cfg_regs_400, sizeof(ddr_cfg_regs));
    else if(ddr_freq_mhz <= 533)
        memcpy(&ddr_cfg_regs, &ddr_cfg_regs_533, sizeof(ddr_cfg_regs));
    else if(ddr_freq_mhz <= 667)
        memcpy(&ddr_cfg_regs, &ddr_cfg_regs_667, sizeof(ddr_cfg_regs));
    else if(ddr_freq_mhz <= 800)
        memcpy(&ddr_cfg_regs, &ddr_cfg_regs_800, sizeof(ddr_cfg_regs));
    else
        panic("Unsupported DDR data rate %s MT/s data rate\n",
              strmhz(buf, ddr_freq));

    /* P1020 and it's derivatives support max 32bit DDR width */
    if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1011) {
        ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_32_BE;
        ddr_cfg_regs.cs[0].bnds = 0x0000001F;
    }

    fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);

    set_ddr_laws(0, ddr_size, LAW_TRGT_IF_DDR_1);
    return ddr_size;
}
Exemple #6
0
/*
 * Fixed sdram init -- doesn't use serial presence detect.
 */
phys_size_t fixed_sdram(void)
{
	int i;
	char buf[32];
	fsl_ddr_cfg_regs_t ddr_cfg_regs;
	phys_size_t ddr_size;
	ulong ddr_freq, ddr_freq_mhz;

	ddr_freq = get_ddr_freq(0);
	ddr_freq_mhz = ddr_freq / 1000000;

	printf("Configuring DDR for %s MT/s data rate\n",
				strmhz(buf, ddr_freq));

	for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
		if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
		   (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
			memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings,
							sizeof(ddr_cfg_regs));
			break;
		}
	}

	if (fixed_ddr_parm_0[i].max_freq == 0)
		panic("Unsupported DDR data rate %s MT/s data rate\n",
					strmhz(buf, ddr_freq));

	ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);

	if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size,
					LAW_TRGT_IF_DDR_1) < 0) {
		printf("ERROR setting Local Access Windows for DDR\n");
		return 0;
	}

	return ddr_size;
}
Exemple #7
0
phys_size_t fixed_sdram(void)
{
	volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
	uint d_init;

	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
	ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
	ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
	ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
	ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTRL;
	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
	ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
	ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
	ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
	ddr->ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL;
	ddr->ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL;
	ddr->ddr_cdr1 = CONFIG_SYS_DDR_CDR1;
	ddr->timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4;
	ddr->timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5;

	if (!strcmp("performance", getenv("perf_mode"))) {
		/* Performance Mode Values */

		ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG_PERF;
		ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS_PERF;
		ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS_PERF;
		ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_PERF;
		ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_PERF;

		asm("sync;isync");

		udelay(500);

		ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL_PERF;
	} else {
		/* Stable Mode Values */

		ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
		ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
		ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
		ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
		ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;

		/* ECC will be assumed in stable mode */
		ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
		ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
		ddr->err_sbe = CONFIG_SYS_DDR_SBE;

		asm("sync;isync");

		udelay(500);

		ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
	}

#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	d_init = 1;
	debug("DDR - 1st controller: memory initializing\n");
	/*
	 * Poll until memory is initialized.
	 * 512 Meg at 400 might hit this 200 times or so.
	 */
	while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
		udelay(1000);
	debug("DDR: memory initialized\n\n");
	asm("sync; isync");
	udelay(500);
#endif

	if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
			 CONFIG_SYS_SDRAM_SIZE * 1024 * 1024,
			 LAW_TRGT_IF_DDR) < 0) {
		printf("ERROR setting Local Access Windows for DDR\n");
		return 0;
	};

	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
}
Exemple #8
0
phys_size_t fixed_sdram(void)
{
	int i;
	sys_info_t sysinfo;
	char buf[32];
	fsl_ddr_cfg_regs_t ddr_cfg_regs;
	phys_size_t ddr_size;
	unsigned int lawbar1_target_id;

	get_sys_info(&sysinfo);
	printf("Configuring DDR for %s MT/s data rate\n",
				strmhz(buf, sysinfo.freqDDRBus));

	for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
		if ((sysinfo.freqDDRBus > fixed_ddr_parm_0[i].min_freq) &&
		   (sysinfo.freqDDRBus <= fixed_ddr_parm_0[i].max_freq)) {
			memcpy(&ddr_cfg_regs,
				fixed_ddr_parm_0[i].ddr_settings,
				sizeof(ddr_cfg_regs));
			break;
		}
	}

	if (fixed_ddr_parm_0[i].max_freq == 0)
		panic("Unsupported DDR data rate %s MT/s data rate\n",
			strmhz(buf, sysinfo.freqDDRBus));

	ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);

#if (CONFIG_NUM_DDR_CONTROLLERS == 2)
	memcpy(&ddr_cfg_regs,
		fixed_ddr_parm_1[i].ddr_settings,
		sizeof(ddr_cfg_regs));
	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 1);
#endif

	/*
	 * setup laws for DDR. If not interleaving, presuming half memory on
	 * DDR1 and the other half on DDR2
	 */
	if (fixed_ddr_parm_0[i].ddr_settings->cs[0].config & 0x20000000) {
		if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
				 ddr_size,
				 LAW_TRGT_IF_DDR_INTRLV) < 0) {
			printf("ERROR setting Local Access Windows for DDR\n");
			return 0;
		}
	} else {
#if (CONFIG_NUM_DDR_CONTROLLERS == 2)
		/* We require both controllers have identical DIMMs */
		lawbar1_target_id = LAW_TRGT_IF_DDR_1;
		if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
				 ddr_size / 2,
				 lawbar1_target_id) < 0) {
			printf("ERROR setting Local Access Windows for DDR\n");
			return 0;
		}
		lawbar1_target_id = LAW_TRGT_IF_DDR_2;
		if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE + ddr_size / 2,
				 ddr_size / 2,
				 lawbar1_target_id) < 0) {
			printf("ERROR setting Local Access Windows for DDR\n");
			return 0;
		}
#else
		lawbar1_target_id = LAW_TRGT_IF_DDR_1;
		if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
				 ddr_size,
				 lawbar1_target_id) < 0) {
			printf("ERROR setting Local Access Windows for DDR\n");
			return 0;
		}
#endif
	}
	return ddr_size;
}
Exemple #9
0
/* Fixed sdram init -- doesn't use serial presence detect. */
phys_size_t fixed_sdram(void)
{
    sys_info_t sysinfo;
    char buf[32];
    size_t ddr_size;
    fsl_ddr_cfg_regs_t ddr_cfg_regs = {
        .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
        .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
        .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
        .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
        .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
        .cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2,
#endif
        .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3,
        .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0,
        .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1,
        .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2,
        .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
        .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
        .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1,
        .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2,
        .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
        .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL,
        .ddr_data_init = CONFIG_SYS_DDR_DATA_INIT,
        .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL,
        .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
        .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
        .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
        .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
        .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
        .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
        .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
        .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
        .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
    };

    get_sys_info(&sysinfo);
    printf("Configuring DDR for %s MT/s data rate\n",
           strmhz(buf, sysinfo.freqDDRBus));

    ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;

    fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);

    if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
                     ddr_size, LAW_TRGT_IF_DDR_1) < 0) {
        printf("ERROR setting Local Access Windows for DDR\n");
        return 0;
    };

    return ddr_size;
}
#endif

void fsl_ddr_board_options(memctl_options_t *popts,
                           dimm_params_t *pdimm,
                           unsigned int ctrl_num)
{
    int i;
    popts->clk_adjust = 6;
    popts->cpo_override = 0x1f;
    popts->write_data_delay = 2;
    popts->half_strength_driver_enable = 1;
    /* Write leveling override */
    popts->wrlvl_en = 1;
    popts->wrlvl_override = 1;
    popts->wrlvl_sample = 0xf;
    popts->wrlvl_start = 0x8;
    popts->trwt_override = 1;
    popts->trwt = 0;

    if (pdimm->primary_sdram_width == 64)
        popts->data_bus_width = 0;
    else if (pdimm->primary_sdram_width == 32)
        popts->data_bus_width = 1;
    else
        printf("Error in DDR bus width configuration!\n");

    for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
        popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
        popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
    }
}