void trap_init(){ // 注册中断、异常处理函数
int i;
for(i=0;i<32;i++)
set_except_vector(i, handle_reserved);
/* Here only register two exception */
set_except_vector(0, handle_int); // ExcCode=0 interruption Exception
set_except_vector(8, handle_sys); // ExcCode=8 syscall Exception
}
void __init init_IRQ(void)
{
int i;
DANUBE_INT_DMSG("init_IRQ\n");
board_be_handler = &danube_be_handler;
init_generic_irq();
/* mask all interrupt sources */
*DANUBE_ICU_IM0_IER = 0;
*DANUBE_ICU_IM1_IER = 0;
*DANUBE_ICU_IM2_IER = 0;
*DANUBE_ICU_IM3_IER = 0;
*DANUBE_ICU_IM4_IER = 0;
/* Now safe to set the exception vector. */
set_except_vector(0, mipsIRQ);
for (i = 0; i <= INT_NUM_IM4_IRL31; i++) {
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = 0;
irq_desc[i].depth = 1;
irq_desc[i].handler = &danube_irq_type;
}
set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
#ifdef CONFIG_KGDB
set_debug_traps();
breakpoint();
#endif
}
void __init nino_irq_setup(void)
{
extern asmlinkage void ninoIRQ(void);
unsigned int i;
REG32(GIMR)=0;
/* Disable all hardware interrupts */
// change_cp0_status(ST0_IM, 0x00);
// cil();
/* Initialize IRQ vector table */
//init_generic_irq();
/* Initialize IRQ action handlers */
for (i = 0; i < 16; i++) {
hw_irq_controller *handler = NULL;
handler = &irq_type;
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = 0;
irq_desc[i].depth = 1;
irq_desc[i].handler = handler;
}
/* Set up the external interrupt exception vector */
set_except_vector(0, ninoIRQ);
/* Enable all interrupts */
// change_cp0_status(ST0_IM, ALLINTS);
}
void __init init_IRQ(void)
{
int i;
init_generic_irq();
switch (mips_machtype) {
case MACH_LASAT_100:
lasat_int_status = (void *)LASAT_INT_STATUS_REG_100;
lasat_int_mask = (void *)LASAT_INT_MASK_REG_100;
lasat_int_mask_shift = LASATINT_MASK_SHIFT_100;
get_int_status = get_int_status_100;
*lasat_int_mask = 0;
break;
case MACH_LASAT_200:
lasat_int_status = (void *)LASAT_INT_STATUS_REG_200;
lasat_int_mask = (void *)LASAT_INT_MASK_REG_200;
lasat_int_mask_shift = LASATINT_MASK_SHIFT_200;
get_int_status = get_int_status_200;
*lasat_int_mask &= 0xffff;
break;
default:
panic("init_IRQ: mips_machtype incorrect");
}
/* Now safe to set the exception vector. */
set_except_vector(0, lasatIRQ);
for (i = 0; i <= LASATINT_END; i++) {
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = 0;
irq_desc[i].depth = 1;
irq_desc[i].handler = &lasat_irq_type;
}
}
void __init init_IRQ(void)
{
int i;
/*
* Mask out all interrupt by writing "1" to all bit position in
* the interrupt reset reg.
*/
atlas_hw0_icregs->intrsten = 0xffffffff;
/* Now safe to set the exception vector. */
set_except_vector(0, mipsIRQ);
for (i = 0; i <= ATLASINT_END; i++) {
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = 0;
irq_desc[i].depth = 1;
irq_desc[i].handler = &atlas_irq_type;
}
#ifdef CONFIG_REMOTE_DEBUG
if (remote_debug) {
set_debug_traps();
breakpoint();
}
#endif
}
void __init bus_error_init(void)
{
/* XXX Initialize all the Hub & Bridge error handling here. */
int cpu = LOCAL_HUB_L(PI_CPU_NUM);
int cpuoff = cpu << 8;
set_except_vector(6, handle_ip27_ibe);
set_except_vector(7, handle_ip27_dbe);
LOCAL_HUB_S(PI_ERR_INT_PEND,
cpu ? PI_ERR_CLEAR_ALL_B : PI_ERR_CLEAR_ALL_A);
LOCAL_HUB_S(PI_ERR_INT_MASK_A + cpuoff, 0);
LOCAL_HUB_S(PI_ERR_STACK_ADDR_A + cpuoff, 0);
LOCAL_HUB_S(PI_ERR_STACK_SIZE, 0); /* Disable error stack */
LOCAL_HUB_S(PI_SYSAD_ERRCHK_EN, PI_SYSAD_CHECK_ALL);
}
void __init arch_init_irq(void)
{
mips_cpu_irq_init(MIPSCPU_INT_BASE);
/* Now safe to set the exception vector. */
set_except_vector(0, mipsIRQ);
}
void __init arch_init_irq(void)
{
/* hardware initialization */
nile4_irq_setup();
m1543_irq_setup();
/* controller setup */
init_i8259_irqs();
vrc5476_irq_init(VRC5476_IRQ_BASE);
mips_cpu_irq_init(CPU_IRQ_BASE);
/* setup cascade interrupts */
setup_irq(VRC5476_IRQ_BASE + VRC5476_I8259_CASCADE, &irq_cascade);
setup_irq(CPU_IRQ_BASE + CPU_VRC5476_CASCADE, &irq_cascade);
/* setup error interrupts for debugging */
setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_CPCE, &irq_error);
setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_CNTD, &irq_error);
setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_MCE, &irq_error);
setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_LBRT, &irq_error);
setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_PCIS, &irq_error);
setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_PCI, &irq_error);
/* setup the grandpa intr vector */
set_except_vector(0, ddb5476_handle_int);
}
static void trap_init(void)
{
extern char except_vec3_generic;
int i;
unsigned long ebase;
ebase = CKSEG1;
/*
* Copy the generic exception handlers to their final destination.
* This will be overriden later as suitable for a particular
* configuration.
*/
memcpy((void *)(ebase + 0x180), &except_vec3_generic, 0x80);
/*
* Setup default vectors
*/
for (i = 0; i <= 31; i++) {
set_except_vector(i, &handle_reserved);
}
if (!cpu_has_4kex)
memcpy((void *)(ebase + 0x080), &except_vec3_generic, 0x80);
/* FIXME: handle tlb */
memcpy((void *)(ebase), &except_vec3_generic, 0x80);
/* unset BOOT EXCEPTION VECTOR bit */
write_c0_status(read_c0_status() & ~ST0_BEV);
}
/*
* Set up exception handlers for tracing and breakpoints
*/
void set_debug_traps(void)
{
struct hard_trap_info *ht;
unsigned long flags;
unsigned char c;
save_and_cli(flags);
for (ht = hard_trap_info; ht->tt && ht->signo; ht++)
saved_vectors[ht->tt] = set_except_vector(ht->tt, trap_low);
#if 1
putDebugChar('+'); /* 'hello world' */
/*
* In case GDB is started before us, ack any packets
* (presumably "$?#xx") sitting there.
*/
while((c = getDebugChar()) != '$');
while((c = getDebugChar()) != '#');
c = getDebugChar(); /* eat first csum byte */
c = getDebugChar(); /* eat second csum byte */
putDebugChar('+'); /* ack it */
#endif
initialized = 1;
restore_flags(flags);
}
void __init arch_init_irq(void)
{
int i;
unsigned long cp0_status;
au1xxx_irq_map_t *imp;
extern au1xxx_irq_map_t au1xxx_irq_map[];
extern au1xxx_irq_map_t au1xxx_ic0_map[];
extern int au1xxx_nr_irqs;
extern int au1xxx_ic0_nr_irqs;
cp0_status = read_c0_status();
set_except_vector(0, au1000_IRQ);
/* Initialize interrupt controllers to a safe state.
*/
au_writel(0xffffffff, IC0_CFG0CLR);
au_writel(0xffffffff, IC0_CFG1CLR);
au_writel(0xffffffff, IC0_CFG2CLR);
au_writel(0xffffffff, IC0_MASKCLR);
au_writel(0xffffffff, IC0_ASSIGNSET);
au_writel(0xffffffff, IC0_WAKECLR);
au_writel(0xffffffff, IC0_SRCSET);
au_writel(0xffffffff, IC0_FALLINGCLR);
au_writel(0xffffffff, IC0_RISINGCLR);
au_writel(0x00000000, IC0_TESTBIT);
au_writel(0xffffffff, IC1_CFG0CLR);
au_writel(0xffffffff, IC1_CFG1CLR);
au_writel(0xffffffff, IC1_CFG2CLR);
au_writel(0xffffffff, IC1_MASKCLR);
au_writel(0xffffffff, IC1_ASSIGNSET);
au_writel(0xffffffff, IC1_WAKECLR);
au_writel(0xffffffff, IC1_SRCSET);
au_writel(0xffffffff, IC1_FALLINGCLR);
au_writel(0xffffffff, IC1_RISINGCLR);
au_writel(0x00000000, IC1_TESTBIT);
/* Initialize IC0, which is fixed per processor.
*/
imp = au1xxx_ic0_map;
for (i=0; i<au1xxx_ic0_nr_irqs; i++) {
setup_local_irq(imp->im_irq, imp->im_type, imp->im_request);
imp++;
}
/* Now set up the irq mapping for the board.
*/
imp = au1xxx_irq_map;
for (i=0; i<au1xxx_nr_irqs; i++) {
setup_local_irq(imp->im_irq, imp->im_type, imp->im_request);
imp++;
}
set_c0_status(ALLINTS);
/* Board specific IRQ initialization.
*/
if (board_init_irq)
(*board_init_irq)();
}
void __init arch_init_irq(void)
{
mips_cpu_irq_init(MIPS_CPU_IRQ_BASE);
init_vr41xx_icu_irq();
init_vr41xx_giuint_irq();
set_except_vector(0, vr41xx_handle_interrupt);
}
void __init arch_init_irq(void)
{
extern void hpIRQ(void);
extern void mips_cpu_irq_init(u32 base);
mips_cpu_irq_init(0);
set_except_vector(0, hpIRQ);
}
void __init tx4938_irq_init(void)
{
extern asmlinkage void tx4938_irq_handler(void);
tx4938_irq_cp0_init();
tx4938_irq_pic_init();
set_except_vector(0, tx4938_irq_handler);
return;
}
__initfunc(static void ps2_irq_setup(void))
{
/* handlers are already prepared */
enable_irq(IRQ_INTC_TIMER0);
enable_irq(IRQ_INTC_GS);
enable_irq(IRQ_INTC_SBUS);
/* Now safe to set the exception vector. */
set_except_vector(0, ps2_irq);
}
void restore_debug_traps(void)
{
struct hard_trap_info *ht;
unsigned long flags;
local_irq_save(flags);
for (ht = hard_trap_info; ht->tt && ht->signo; ht++)
set_except_vector(ht->tt, saved_vectors[ht->tt]);
local_irq_restore(flags);
}
void restore_debug_traps(void)
{
struct hard_trap_info *ht;
unsigned long flags;
save_and_cli(flags);
for (ht = hard_trap_info; ht->tt && ht->signo; ht++)
set_except_vector(ht->tt, saved_vectors[ht->tt]);
restore_flags(flags);
}
void __init nino_irq_setup(void)
{
extern asmlinkage void ninoIRQ(void);
extern void init_generic_irq(void);
unsigned int i;
/* Disable all hardware interrupts */
change_cp0_status(ST0_IM, 0x00);
/* Clear interrupts */
outl(0xffffffff, TX3912_INT1_CLEAR);
outl(0xffffffff, TX3912_INT2_CLEAR);
outl(0xffffffff, TX3912_INT3_CLEAR);
outl(0xffffffff, TX3912_INT4_CLEAR);
outl(0xffffffff, TX3912_INT5_CLEAR);
/*
* Disable all PR31700 interrupts. We let the various
* device drivers in the system register themselves
* and set the proper hardware bits.
*/
outl(0x00000000, TX3912_INT1_ENABLE);
outl(0x00000000, TX3912_INT2_ENABLE);
outl(0x00000000, TX3912_INT3_ENABLE);
outl(0x00000000, TX3912_INT4_ENABLE);
outl(0x00000000, TX3912_INT5_ENABLE);
/* Initialize IRQ vector table */
init_generic_irq();
/* Initialize IRQ action handlers */
for (i = 0; i < 16; i++) {
hw_irq_controller *handler = NULL;
if (i == 0 || i == 3)
handler = &irq6_type;
else
handler = &irq4_type;
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = 0;
irq_desc[i].depth = 1;
irq_desc[i].handler = handler;
}
/* Set up the external interrupt exception vector */
set_except_vector(0, ninoIRQ);
/* Enable high priority interrupts */
outl(TX3912_INT6_ENABLE_GLOBALEN | TX3912_INT6_ENABLE_HIGH_PRIORITY,
TX3912_INT6_ENABLE);
/* Enable all interrupts */
change_cp0_status(ST0_IM, ALLINTS);
}
void __init arch_init_irq(void)
{
switch (mips_machtype) {
case MACH_DS23100: /* DS2100/DS3100 Pmin/Pmax */
dec_init_kn01();
break;
case MACH_DS5100: /* DS5100 MIPSmate */
dec_init_kn230();
break;
case MACH_DS5000_200: /* DS5000/200 3max */
dec_init_kn02();
break;
case MACH_DS5000_1XX: /* DS5000/1xx 3min */
dec_init_kn02ba();
break;
case MACH_DS5000_2X0: /* DS5000/240 3max+ */
case MACH_DS5900: /* DS5900 bigmax */
dec_init_kn03();
break;
case MACH_DS5000_XX: /* Personal DS5000/xx */
dec_init_kn02ca();
break;
case MACH_DS5800: /* DS5800 Isis */
panic("Don't know how to set this up!");
break;
case MACH_DS5400: /* DS5400 MIPSfair */
panic("Don't know how to set this up!");
break;
case MACH_DS5500: /* DS5500 MIPSfair-2 */
panic("Don't know how to set this up!");
break;
}
set_except_vector(0, decstation_handle_int);
/* Free the FPU interrupt if the exception is present. */
if (!cpu_has_nofpuex) {
cpu_fpu_mask = 0;
dec_interrupt[DEC_IRQ_FPU] = -1;
}
/* Register board interrupts: FPU and cascade. */
if (dec_interrupt[DEC_IRQ_FPU] >= 0)
setup_irq(dec_interrupt[DEC_IRQ_FPU], &fpuirq);
if (dec_interrupt[DEC_IRQ_CASCADE] >= 0)
setup_irq(dec_interrupt[DEC_IRQ_CASCADE], &ioirq);
/* Register the bus error interrupt. */
if (dec_interrupt[DEC_IRQ_BUS] >= 0 && busirq.handler)
setup_irq(dec_interrupt[DEC_IRQ_BUS], &busirq);
/* Register the HALT interrupt. */
if (dec_interrupt[DEC_IRQ_HALT] >= 0)
setup_irq(dec_interrupt[DEC_IRQ_HALT], &haltirq);
}
void
ddb5477_irq_setup(void)
{
db_run(printk("ddb5477_irq_setup invoked.\n"));
/* by default, we disable all interrupts and route all vrc5477
* interrupts to pin 0 (irq 2) */
ddb_out32(DDB_INTCTRL0, 0);
ddb_out32(DDB_INTCTRL1, 0);
ddb_out32(DDB_INTCTRL2, 0);
ddb_out32(DDB_INTCTRL3, 0);
clear_cp0_status(0xff00);
set_cp0_status(0x0400);
/* setup PCI interrupt attributes */
set_pci_int_attr(PCI0, INTA, ACTIVE_LOW, LEVEL_SENSE);
set_pci_int_attr(PCI0, INTB, ACTIVE_LOW, LEVEL_SENSE);
set_pci_int_attr(PCI0, INTC, ACTIVE_LOW, LEVEL_SENSE);
set_pci_int_attr(PCI0, INTD, ACTIVE_LOW, LEVEL_SENSE);
set_pci_int_attr(PCI0, INTE, ACTIVE_LOW, LEVEL_SENSE);
set_pci_int_attr(PCI1, INTA, ACTIVE_LOW, LEVEL_SENSE);
set_pci_int_attr(PCI1, INTB, ACTIVE_LOW, LEVEL_SENSE);
set_pci_int_attr(PCI1, INTC, ACTIVE_LOW, LEVEL_SENSE);
set_pci_int_attr(PCI1, INTD, ACTIVE_LOW, LEVEL_SENSE);
set_pci_int_attr(PCI1, INTE, ACTIVE_LOW, LEVEL_SENSE);
/*
* for debugging purpose, we enable several error interrupts
* and route them to pin 1. (IP3)
*/
/* cpu parity check - 0 */
ll_vrc5477_irq_route(0, 1); ll_vrc5477_irq_enable(0);
/* cpu no-target decode - 1 */
ll_vrc5477_irq_route(1, 1); ll_vrc5477_irq_enable(1);
/* local bus read time-out - 7 */
ll_vrc5477_irq_route(7, 1); ll_vrc5477_irq_enable(7);
/* PCI SERR# - 14 */
ll_vrc5477_irq_route(14, 1); ll_vrc5477_irq_enable(14);
/* PCI internal error - 15 */
ll_vrc5477_irq_route(15, 1); ll_vrc5477_irq_enable(15);
/* IOPCI SERR# - 30 */
ll_vrc5477_irq_route(30, 1); ll_vrc5477_irq_enable(30);
/* IOPCI internal error - 31 */
ll_vrc5477_irq_route(31, 1); ll_vrc5477_irq_enable(31);
/* init all controllers */
mips_cpu_irq_init(0);
vrc5477_irq_init(8);
/* hook up the first-level interrupt handler */
set_except_vector(0, ddb5477_handle_int);
}
void __init init_IRQ(void)
{
memset(irq_desc, 0, sizeof(irq_desc));
init_generic_irq();
mips_cpu_irq_init(MIPS_CPU_IRQ_BASE);
init_vr41xx_icu_irq();
init_vr41xx_giuint_irq();
set_except_vector(0, vr41xx_handle_interrupt);
}
void __init arch_init_irq(void)
{
int i;
set_except_vector(0, vr4181_handle_irq);
/* init CPU irqs */
mips_cpu_irq_init(VR4181_CPU_IRQ_BASE);
/* init sys irqs */
sys_irq_base = VR4181_SYS_IRQ_BASE;
for (i=sys_irq_base; i < sys_irq_base + VR4181_NUM_SYS_IRQ; i++) {
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = NULL;
irq_desc[i].depth = 1;
irq_desc[i].handler = &sys_irq_controller;
}
/* init gpio irqs */
gpio_irq_base = VR4181_GPIO_IRQ_BASE;
for (i=gpio_irq_base; i < gpio_irq_base + VR4181_NUM_GPIO_IRQ; i++) {
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = NULL;
irq_desc[i].depth = 1;
irq_desc[i].handler = &gpio_irq_controller;
}
/* Default all ICU IRQs to off ... */
*VR4181_MSYSINT1REG = 0;
*VR4181_MSYSINT2REG = 0;
/* We initialize the level 2 ICU registers to all bits disabled. */
*VR4181_MPIUINTREG = 0;
*VR4181_MAIUINTREG = 0;
*VR4181_MKIUINTREG = 0;
/* disable all GPIO intrs */
*VR4181_GPINTMSK = 0xffff;
/* vector handler. What these do is register the IRQ as non-sharable */
setup_irq(VR4181_IRQ_INT0, &cascade);
setup_irq(VR4181_IRQ_GIU, &cascade);
/*
* RTC interrupts are interesting. They have two destinations.
* One is at sys irq controller, and the other is at CPU IP3 and IP4.
* RTC timer is used as system timer.
* We enable them here, but timer routine will register later
* with CPU IP3/IP4.
*/
setup_irq(VR4181_IRQ_RTCL1, &reserved);
setup_irq(VR4181_IRQ_RTCL2, &reserved);
}
void __init init_IRQ(void)
{
int i;
unsigned long flags;
memset(irq_desc, 0, sizeof(irq_desc));
set_except_vector(0, it8172_IRQ);
init_generic_irq();
/* mask all interrupts */
it8172_hw0_icregs->lb_mask = 0xffff;
it8172_hw0_icregs->lpc_mask = 0xffff;
it8172_hw0_icregs->pci_mask = 0xffff;
it8172_hw0_icregs->nmi_mask = 0xffff;
/* make all interrupts level triggered */
it8172_hw0_icregs->lb_trigger = 0;
it8172_hw0_icregs->lpc_trigger = 0;
it8172_hw0_icregs->pci_trigger = 0;
it8172_hw0_icregs->nmi_trigger = 0;
/* active level setting */
/* uart, keyboard, and mouse are active high */
it8172_hw0_icregs->lpc_level = (0x10 | 0x2 | 0x1000);
it8172_hw0_icregs->lb_level |= 0x20;
/* keyboard and mouse are edge triggered */
it8172_hw0_icregs->lpc_trigger |= (0x2 | 0x1000);
#if 0
// Enable this piece of code to make internal USB interrupt
// edge triggered.
it8172_hw0_icregs->pci_trigger |=
(1 << (IT8172_USB_IRQ - IT8172_PCI_DEV_IRQ_BASE));
it8172_hw0_icregs->pci_level &=
~(1 << (IT8172_USB_IRQ - IT8172_PCI_DEV_IRQ_BASE));
#endif
for (i = 0; i <= IT8172_LAST_IRQ; i++) {
irq_desc[i].handler = &it8172_irq_type;
}
irq_desc[MIPS_CPU_TIMER_IRQ].handler = &cp0_irq_type;
set_cp0_status(ALLINTS_NOTIMER);
#ifdef CONFIG_REMOTE_DEBUG
/* If local serial I/O used for debug port, enter kgdb at once */
puts("Waiting for kgdb to connect...");
set_debug_traps();
breakpoint();
#endif
}
void __init init_IRQ(void)
{
set_except_vector(0, mipsIRQ);
init_generic_irq();
init_i8259_irqs();
#ifdef CONFIG_REMOTE_DEBUG
if (remote_debug) {
set_debug_traps();
breakpoint();
}
#endif
}
void __init init_IRQ(void)
{
set_except_vector(0, cobalt_handle_int);
init_i8259_irqs(); /* 0 ... 15 */
mips_cpu_irq_init(16); /* 16 ... 23 */
/*
* Mask all cpu interrupts
* (except IE4, we already masked those at VIA level)
*/
change_c0_status(ST0_IM, IE_IRQ4);
}
void __init arch_init_irq(void)
{
set_except_vector(0, mipsIRQ);
init_i8259_irqs();
if (!cpu_has_veic)
mips_cpu_irq_init (MIPSCPU_INT_BASE);
switch(mips_revision_corid) {
case MIPS_REVISION_CORID_CORE_MSC:
case MIPS_REVISION_CORID_CORE_FPGA2:
case MIPS_REVISION_CORID_CORE_FPGA3:
case MIPS_REVISION_CORID_CORE_EMUL_MSC:
if (cpu_has_veic)
init_msc_irqs (MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs);
else
init_msc_irqs (MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs);
}
if (cpu_has_veic) {
set_vi_handler (MSC01E_INT_I8259A, malta_hw0_irqdispatch);
set_vi_handler (MSC01E_INT_COREHI, corehi_irqdispatch);
setup_irq (MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq);
setup_irq (MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction);
}
else if (cpu_has_vint) {
set_vi_handler (MIPSCPU_INT_I8259A, malta_hw0_irqdispatch);
set_vi_handler (MIPSCPU_INT_COREHI, corehi_irqdispatch);
setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq);
setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
}
else {
set_except_vector(0, mipsIRQ);
setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq);
setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
}
}
void __init init_IRQ(void)
{
int i;
set_except_vector(0, ev96100IRQ);
init_generic_irq();
for (i = 0; i < 8; i++) {
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = 0;
irq_desc[i].depth = 1;
irq_desc[i].handler = &ev96100_irq_type;
}
}
void __init arch_init_irq(void)
{
/*
* Clear all of the interrupts while we change the able around a bit.
* int-handler is not on bootstrap
*/
clear_c0_status(ST0_IM);
local_irq_disable();
/* Sets the first-level interrupt dispatcher. */
set_except_vector(0, ocelot_handle_int);
mips_cpu_irq_init(0);
rm7k_cpu_irq_init(8);
}
void __init brcm_irq_setup(void)
{
extern asmlinkage void brcmIRQ(void);
/* In 2.4.3 Kernel this was done in trap_init. In 2.4.17 it was
* moved to SMP code, which is only used by MIPS64. In other words
* Linux is free, you get what you pay for */
clear_cp0_status(ST0_BEV);
set_except_vector(0, brcmIRQ);
change_cp0_status(ST0_IM, ALLINTS_NOTIMER);
#ifdef CONFIG_REMOTE_DEBUG
rs_kgdb_hook(0);
#endif
}
void __init ddb_irq_setup(void)
{
#ifdef CONFIG_REMOTE_DEBUG
if (remote_debug)
set_debug_traps();
breakpoint(); /* you may move this line to whereever you want :-) */
#endif
request_region(0x20, 0x20, "pic1");
request_region(0xa0, 0x20, "pic2");
i8259_setup_irq(2, &irq2);
nile4_irq_setup();
m1543_irq_setup();
set_except_vector(0, ddbIRQ);
}
