float64 helper_fsqrt_DT(float64 t0)
{
set_float_exception_flags(0, &env->fp_status);
t0 = float64_sqrt(t0, &env->fp_status);
update_fpscr(GETPC());
return t0;
}
float32 helper_fsqrt_FT(CPUSH4State *env, float32 t0)
{
set_float_exception_flags(0, &env->fp_status);
t0 = float32_sqrt(t0, &env->fp_status);
update_fpscr(env, GETPC());
return t0;
}
void helper_ftrv(CPUSH4State *env, uint32_t n)
{
int bank_matrix, bank_vector;
int i, j;
float32 r[4];
float32 p;
bank_matrix = (env->sr & FPSCR_FR) ? 0 : 16;
bank_vector = (env->sr & FPSCR_FR) ? 16 : 0;
set_float_exception_flags(0, &env->fp_status);
for (i = 0 ; i < 4 ; i++) {
r[i] = float32_zero;
for (j = 0 ; j < 4 ; j++) {
p = float32_mul(env->fregs[bank_matrix + 4 * j + i],
env->fregs[bank_vector + j],
&env->fp_status);
r[i] = float32_add(r[i], p, &env->fp_status);
}
}
update_fpscr(env, GETPC());
for (i = 0 ; i < 4 ; i++) {
env->fregs[bank_vector + i] = r[i];
}
}
float32 helper_fsub_FT(float32 t0, float32 t1)
{
set_float_exception_flags(0, &env->fp_status);
t0 = float32_sub(t0, t1, &env->fp_status);
update_fpscr(GETPC());
return t0;
}
float64 helper_fmul_DT(float64 t0, float64 t1)
{
set_float_exception_flags(0, &env->fp_status);
t0 = float64_mul(t0, t1, &env->fp_status);
update_fpscr(GETPC());
return t0;
}
float64 helper_fsub_DT(CPUSH4State *env, float64 t0, float64 t1)
{
set_float_exception_flags(0, &env->fp_status);
t0 = float64_sub(t0, t1, &env->fp_status);
update_fpscr(env, GETPC());
return t0;
}
float32 helper_fmul_FT(CPUSH4State *env, float32 t0, float32 t1)
{
set_float_exception_flags(0, &env->fp_status);
t0 = float32_mul(t0, t1, &env->fp_status);
update_fpscr(env, GETPC());
return t0;
}
float64 helper_fcnvsd_FT_DT(float32 t0)
{
float64 ret;
set_float_exception_flags(0, &env->fp_status);
ret = float32_to_float64(t0, &env->fp_status);
update_fpscr(GETPC());
return ret;
}
float64 helper_float_DT(CPUSH4State *env, uint32_t t0)
{
float64 ret;
set_float_exception_flags(0, &env->fp_status);
ret = int32_to_float64(t0, &env->fp_status);
update_fpscr(env, GETPC());
return ret;
}
float32 helper_fcnvds_DT_FT(CPUSH4State *env, float64 t0)
{
float32 ret;
set_float_exception_flags(0, &env->fp_status);
ret = float64_to_float32(t0, &env->fp_status);
update_fpscr(env, GETPC());
return ret;
}
uint32_t helper_ftrc_DT(CPUSH4State *env, float64 t0)
{
uint32_t ret;
set_float_exception_flags(0, &env->fp_status);
ret = float64_to_int32_round_to_zero(t0, &env->fp_status);
update_fpscr(env, GETPC());
return ret;
}
uint32_t helper_ftrc_FT(float32 t0)
{
uint32_t ret;
set_float_exception_flags(0, &env->fp_status);
ret = float32_to_int32_round_to_zero(t0, &env->fp_status);
update_fpscr(GETPC());
return ret;
}
float32 helper_fmac_FT(float32 t0, float32 t1, float32 t2)
{
set_float_exception_flags(0, &env->fp_status);
t0 = float32_mul(t0, t1, &env->fp_status);
t0 = float32_add(t0, t2, &env->fp_status);
update_fpscr(GETPC());
return t0;
}
float32 helper_float_FT(uint32_t t0)
{
float32 ret;
set_float_exception_flags(0, &env->fp_status);
ret = int32_to_float32(t0, &env->fp_status);
update_fpscr(GETPC());
return ret;
}
void helper_fcmp_gt_DT(CPUSH4State *env, float64 t0, float64 t1)
{
int relation;
set_float_exception_flags(0, &env->fp_status);
relation = float64_compare(t0, t1, &env->fp_status);
if (unlikely(relation == float_relation_unordered)) {
update_fpscr(env, GETPC());
} else {
env->sr_t = (relation == float_relation_greater);
}
}
uint32_t helper_fsqrt(CPUMBState *env, uint32_t a)
{
CPU_FloatU fd, fa;
int flags;
set_float_exception_flags(0, &env->fp_status);
fa.l = a;
fd.l = float32_sqrt(fa.f, &env->fp_status);
flags = get_float_exception_flags(&env->fp_status);
update_fpu_flags(env, flags);
return fd.l;
}
uint32_t helper_fcmp_gt(CPUMBState *env, uint32_t a, uint32_t b)
{
CPU_FloatU fa, fb;
int flags, r;
fa.l = a;
fb.l = b;
set_float_exception_flags(0, &env->fp_status);
r = float32_lt(fa.f, fb.f, &env->fp_status);
flags = get_float_exception_flags(&env->fp_status);
update_fpu_flags(env, flags & float_flag_invalid);
return r;
}
uint32_t helper_frsub(CPUMBState *env, uint32_t a, uint32_t b)
{
CPU_FloatU fd, fa, fb;
int flags;
set_float_exception_flags(0, &env->fp_status);
fa.l = a;
fb.l = b;
fd.f = float32_sub(fb.f, fa.f, &env->fp_status);
flags = get_float_exception_flags(&env->fp_status);
update_fpu_flags(env, flags);
return fd.l;
}
void helper_fcmp_gt_DT(float64 t0, float64 t1)
{
int relation;
set_float_exception_flags(0, &env->fp_status);
relation = float64_compare(t0, t1, &env->fp_status);
if (unlikely(relation == float_relation_unordered)) {
update_fpscr(GETPC());
} else if (relation == float_relation_greater) {
set_t();
} else {
clr_t();
}
}
uint32_t helper_fint(CPUMBState *env, uint32_t a)
{
CPU_FloatU fa;
uint32_t r;
int flags;
set_float_exception_flags(0, &env->fp_status);
fa.l = a;
r = float32_to_int32(fa.f, &env->fp_status);
flags = get_float_exception_flags(&env->fp_status);
update_fpu_flags(env, flags);
return r;
}
uint32_t helper_fcmp_ne(uint32_t a, uint32_t b)
{
CPU_FloatU fa, fb;
int flags, r;
fa.l = a;
fb.l = b;
set_float_exception_flags(0, &env->fp_status);
r = !float32_eq_quiet(fa.f, fb.f, &env->fp_status);
flags = get_float_exception_flags(&env->fp_status);
update_fpu_flags(flags & float_flag_invalid);
return r;
}
uint32_t helper_fmul(uint32_t a, uint32_t b)
{
CPU_FloatU fd, fa, fb;
int flags;
set_float_exception_flags(0, &env->fp_status);
fa.l = a;
fb.l = b;
fd.f = float32_mul(fa.f, fb.f, &env->fp_status);
flags = get_float_exception_flags(&env->fp_status);
update_fpu_flags(flags);
return fd.l;
}
void helper_fcmp_eq_FT(CPUSH4State *env, float32 t0, float32 t1)
{
int relation;
set_float_exception_flags(0, &env->fp_status);
relation = float32_compare(t0, t1, &env->fp_status);
if (unlikely(relation == float_relation_unordered)) {
update_fpscr(env, GETPC());
} else if (relation == float_relation_equal) {
set_t(env);
} else {
clr_t(env);
}
}
static uint32_t soft_to_fpcr_exc(CPUAlphaState *env)
{
uint8_t exc = get_float_exception_flags(&FP_STATUS);
uint32_t ret = 0;
if (unlikely(exc)) {
set_float_exception_flags(0, &FP_STATUS);
ret |= CONVERT_BIT(exc, float_flag_invalid, FPCR_INV);
ret |= CONVERT_BIT(exc, float_flag_divbyzero, FPCR_DZE);
ret |= CONVERT_BIT(exc, float_flag_overflow, FPCR_OVF);
ret |= CONVERT_BIT(exc, float_flag_underflow, FPCR_UNF);
ret |= CONVERT_BIT(exc, float_flag_inexact, FPCR_INE);
}
return ret;
}
void helper_fipr(CPUSH4State *env, uint32_t m, uint32_t n)
{
int bank, i;
float32 r, p;
bank = (env->sr & FPSCR_FR) ? 16 : 0;
r = float32_zero;
set_float_exception_flags(0, &env->fp_status);
for (i = 0 ; i < 4 ; i++) {
p = float32_mul(env->fregs[bank + m + i],
env->fregs[bank + n + i],
&env->fp_status);
r = float32_add(r, p, &env->fp_status);
}
update_fpscr(env, GETPC());
env->fregs[bank + n + 3] = r;
}
void helper_fp_exc_clear(CPUAlphaState *env)
{
set_float_exception_flags(0, &FP_STATUS);
}
