static struct gdbarch *
tilegx_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
{
struct gdbarch *gdbarch;
int arch_size = 64;
/* Handle arch_size == 32 or 64. Default to 64. */
if (info.abfd)
arch_size = bfd_get_arch_size (info.abfd);
/* Try to find a pre-existing architecture. */
for (arches = gdbarch_list_lookup_by_info (arches, &info);
arches != NULL;
arches = gdbarch_list_lookup_by_info (arches->next, &info))
{
/* We only have two flavors -- just make sure arch_size matches. */
if (gdbarch_ptr_bit (arches->gdbarch) == arch_size)
return (arches->gdbarch);
}
gdbarch = gdbarch_alloc (&info, NULL);
/* Basic register fields and methods, datatype sizes and stuff. */
/* There are 64 physical registers which can be referenced by
instructions (although only 56 of them can actually be
debugged) and 1 magic register (the PC). The other three
magic registers (ex1, syscall, orig_r0) which are known to
"ptrace" are ignored by "gdb". Note that we simply pretend
that there are 65 registers, and no "pseudo registers". */
set_gdbarch_num_regs (gdbarch, TILEGX_NUM_REGS);
set_gdbarch_num_pseudo_regs (gdbarch, 0);
set_gdbarch_sp_regnum (gdbarch, TILEGX_SP_REGNUM);
set_gdbarch_pc_regnum (gdbarch, TILEGX_PC_REGNUM);
set_gdbarch_register_name (gdbarch, tilegx_register_name);
set_gdbarch_register_type (gdbarch, tilegx_register_type);
set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
set_gdbarch_long_bit (gdbarch, arch_size);
set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
set_gdbarch_ptr_bit (gdbarch, arch_size);
set_gdbarch_addr_bit (gdbarch, arch_size);
set_gdbarch_cannot_fetch_register (gdbarch,
tilegx_cannot_reference_register);
set_gdbarch_cannot_store_register (gdbarch,
tilegx_cannot_reference_register);
/* Stack grows down. */
set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
/* Frame Info. */
set_gdbarch_unwind_sp (gdbarch, tilegx_unwind_sp);
set_gdbarch_unwind_pc (gdbarch, tilegx_unwind_pc);
set_gdbarch_dummy_id (gdbarch, tilegx_unwind_dummy_id);
set_gdbarch_frame_align (gdbarch, tilegx_frame_align);
frame_base_set_default (gdbarch, &tilegx_frame_base);
set_gdbarch_skip_prologue (gdbarch, tilegx_skip_prologue);
set_gdbarch_stack_frame_destroyed_p (gdbarch, tilegx_stack_frame_destroyed_p);
/* Map debug registers into internal register numbers. */
set_gdbarch_dwarf2_reg_to_regnum (gdbarch, tilegx_dwarf2_reg_to_regnum);
/* These values and methods are used when gdb calls a target function. */
set_gdbarch_push_dummy_call (gdbarch, tilegx_push_dummy_call);
set_gdbarch_get_longjmp_target (gdbarch, tilegx_get_longjmp_target);
set_gdbarch_write_pc (gdbarch, tilegx_write_pc);
set_gdbarch_breakpoint_from_pc (gdbarch, tilegx_breakpoint_from_pc);
set_gdbarch_return_value (gdbarch, tilegx_return_value);
set_gdbarch_print_insn (gdbarch, print_insn_tilegx);
gdbarch_init_osabi (info, gdbarch);
dwarf2_append_unwinders (gdbarch);
frame_unwind_append_unwinder (gdbarch, &tilegx_frame_unwind);
return gdbarch;
}
static struct gdbarch *
lm32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
{
struct gdbarch *gdbarch;
struct gdbarch_tdep *tdep;
/* If there is already a candidate, use it. */
arches = gdbarch_list_lookup_by_info (arches, &info);
if (arches != NULL)
return arches->gdbarch;
/* None found, create a new architecture from the information provided. */
tdep = XMALLOC (struct gdbarch_tdep);
gdbarch = gdbarch_alloc (&info, tdep);
/* Type sizes. */
set_gdbarch_short_bit (gdbarch, 16);
set_gdbarch_int_bit (gdbarch, 32);
set_gdbarch_long_bit (gdbarch, 32);
set_gdbarch_long_long_bit (gdbarch, 64);
set_gdbarch_float_bit (gdbarch, 32);
set_gdbarch_double_bit (gdbarch, 64);
set_gdbarch_long_double_bit (gdbarch, 64);
set_gdbarch_ptr_bit (gdbarch, 32);
/* Register info. */
set_gdbarch_num_regs (gdbarch, SIM_LM32_NUM_REGS);
set_gdbarch_sp_regnum (gdbarch, SIM_LM32_SP_REGNUM);
set_gdbarch_pc_regnum (gdbarch, SIM_LM32_PC_REGNUM);
set_gdbarch_register_name (gdbarch, lm32_register_name);
set_gdbarch_register_type (gdbarch, lm32_register_type);
set_gdbarch_cannot_store_register (gdbarch, lm32_cannot_store_register);
/* Frame info. */
set_gdbarch_skip_prologue (gdbarch, lm32_skip_prologue);
set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
set_gdbarch_decr_pc_after_break (gdbarch, 0);
set_gdbarch_frame_args_skip (gdbarch, 0);
/* Frame unwinding. */
set_gdbarch_frame_align (gdbarch, lm32_frame_align);
frame_base_set_default (gdbarch, &lm32_frame_base);
set_gdbarch_unwind_pc (gdbarch, lm32_unwind_pc);
set_gdbarch_unwind_sp (gdbarch, lm32_unwind_sp);
set_gdbarch_dummy_id (gdbarch, lm32_dummy_id);
frame_unwind_append_unwinder (gdbarch, &lm32_frame_unwind);
/* Breakpoints. */
set_gdbarch_breakpoint_from_pc (gdbarch, lm32_breakpoint_from_pc);
set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
/* Calling functions in the inferior. */
set_gdbarch_push_dummy_call (gdbarch, lm32_push_dummy_call);
set_gdbarch_return_value (gdbarch, lm32_return_value);
/* Instruction disassembler. */
set_gdbarch_print_insn (gdbarch, print_insn_lm32);
lm32_add_reggroups (gdbarch);
set_gdbarch_register_reggroup_p (gdbarch, lm32_register_reggroup_p);
return gdbarch;
}
void
amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
/* AMD64 generally uses `fxsave' instead of `fsave' for saving its
floating-point registers. */
tdep->sizeof_fpregset = I387_SIZEOF_FXSAVE;
/* AMD64 has an FPU and 16 SSE registers. */
tdep->st0_regnum = AMD64_ST0_REGNUM;
tdep->num_xmm_regs = 16;
/* This is what all the fuss is about. */
set_gdbarch_long_bit (gdbarch, 64);
set_gdbarch_long_long_bit (gdbarch, 64);
set_gdbarch_ptr_bit (gdbarch, 64);
/* In contrast to the i386, on AMD64 a `long double' actually takes
up 128 bits, even though it's still based on the i387 extended
floating-point format which has only 80 significant bits. */
set_gdbarch_long_double_bit (gdbarch, 128);
set_gdbarch_num_regs (gdbarch, AMD64_NUM_REGS);
set_gdbarch_register_name (gdbarch, amd64_register_name);
set_gdbarch_register_type (gdbarch, amd64_register_type);
/* Register numbers of various important registers. */
set_gdbarch_sp_regnum (gdbarch, AMD64_RSP_REGNUM); /* %rsp */
set_gdbarch_pc_regnum (gdbarch, AMD64_RIP_REGNUM); /* %rip */
set_gdbarch_ps_regnum (gdbarch, AMD64_EFLAGS_REGNUM); /* %eflags */
set_gdbarch_fp0_regnum (gdbarch, AMD64_ST0_REGNUM); /* %st(0) */
/* APPLE LOCAL: Add the frame pointer register so it can be modified
in expressions. */
set_gdbarch_deprecated_fp_regnum (gdbarch, AMD64_RBP_REGNUM); /* %rbp */
/* The "default" register numbering scheme for AMD64 is referred to
as the "DWARF Register Number Mapping" in the System V psABI.
The preferred debugging format for all known AMD64 targets is
actually DWARF2, and GCC doesn't seem to support DWARF (that is
DWARF-1), but we provide the same mapping just in case. This
mapping is also used for stabs, which GCC does support. */
set_gdbarch_stab_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
set_gdbarch_dwarf_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
set_gdbarch_dwarf2_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
/* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to
be in use on any of the supported AMD64 targets. */
/* Call dummy code. */
set_gdbarch_push_dummy_call (gdbarch, amd64_push_dummy_call);
set_gdbarch_frame_align (gdbarch, amd64_frame_align);
set_gdbarch_frame_red_zone_size (gdbarch, 128);
set_gdbarch_convert_register_p (gdbarch, amd64_convert_register_p);
set_gdbarch_register_to_value (gdbarch, i387_register_to_value);
set_gdbarch_value_to_register (gdbarch, i387_value_to_register);
set_gdbarch_return_value (gdbarch, amd64_return_value);
set_gdbarch_skip_prologue (gdbarch, amd64_skip_prologue);
/* Avoid wiring in the MMX registers for now. */
set_gdbarch_num_pseudo_regs (gdbarch, 0);
tdep->mm0_regnum = -1;
set_gdbarch_unwind_dummy_id (gdbarch, amd64_unwind_dummy_id);
frame_unwind_append_sniffer (gdbarch, amd64_sigtramp_frame_sniffer);
frame_unwind_append_sniffer (gdbarch, amd64_frame_sniffer);
frame_base_set_default (gdbarch, &amd64_frame_base);
/* If we have a register mapping, enable the generic core file support. */
if (tdep->gregset_reg_offset)
set_gdbarch_regset_from_core_section (gdbarch,
amd64_regset_from_core_section);
/* APPLE LOCAL: A handy little function. */
set_gdbarch_fetch_pointer_argument (gdbarch, amd64_fetch_pointer_argument);
}
