static int msm_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
{
unsigned long irq_flags;
struct msm_gpio_dev *msm_gpio = get_irq_chip_data(irq);
unsigned offset = irq - msm_gpio->irq_base;
if ((flow_type & (IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING)) ==
(IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING))
return -ENOTSUPP;
if ((flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) ==
(IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW))
return -ENOTSUPP;
spin_lock_irqsave(&msm_gpio->lock, irq_flags);
if (flow_type & (IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING)) {
set_gpio_bit(offset, msm_gpio->regs.int_edge);
irq_desc[irq].handle_irq = handle_edge_irq;
} else {
clr_gpio_bit(offset, msm_gpio->regs.int_edge);
irq_desc[irq].handle_irq = handle_level_irq;
}
if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_RISING))
set_gpio_bit(offset, msm_gpio->regs.int_pos);
else
clr_gpio_bit(offset, msm_gpio->regs.int_pos);
spin_unlock_irqrestore(&msm_gpio->lock, irq_flags);
return 0;
}
static void spi_send_byte(ice1712_t *ice, unsigned char data)
{
int i;
for (i = 0; i < 8; i++) {
set_gpio_bit(ice, PONTIS_CS_CLK, 0);
udelay(1);
set_gpio_bit(ice, PONTIS_CS_WDATA, data & 0x80);
udelay(1);
set_gpio_bit(ice, PONTIS_CS_CLK, 1);
udelay(1);
data <<= 1;
}
}
static void wm8766_spi_send_word(struct snd_ice1712 *ice, unsigned int data)
{
int i;
for (i = 0; i < 16; i++) {
set_gpio_bit(ice, WM8766_SPI_CLK, 0);
udelay(1);
set_gpio_bit(ice, WM8766_SPI_MD, data & 0x8000);
udelay(1);
set_gpio_bit(ice, WM8766_SPI_CLK, 1);
udelay(1);
data <<= 1;
}
}
static void ak4396_send_word(struct snd_ice1712 *ice, unsigned int data)
{
int i;
for (i = 0; i < 16; i++) {
set_gpio_bit(ice, AK4396_CCLK, 0);
udelay(1);
set_gpio_bit(ice, AK4396_CDTI, data & 0x8000);
udelay(1);
set_gpio_bit(ice, AK4396_CCLK, 1);
udelay(1);
data <<= 1;
}
}
static void spi_write(ice1712_t *ice, unsigned int dev, unsigned int reg, unsigned int data)
{
snd_ice1712_gpio_set_dir(ice, PONTIS_CS_CS|PONTIS_CS_WDATA|PONTIS_CS_CLK);
snd_ice1712_gpio_set_mask(ice, ~(PONTIS_CS_CS|PONTIS_CS_WDATA|PONTIS_CS_CLK));
set_gpio_bit(ice, PONTIS_CS_CS, 0);
spi_send_byte(ice, dev & ~1); /* WRITE */
spi_send_byte(ice, reg); /* MAP */
spi_send_byte(ice, data); /* DATA */
/* trigger */
set_gpio_bit(ice, PONTIS_CS_CS, 1);
udelay(1);
/* restore */
snd_ice1712_gpio_set_mask(ice, ice->gpio.write_mask);
snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
}
/*
* This function assumes that msm_gpio_dev::lock is held.
*/
static inline void
msm_gpio_write(struct msm_gpio_dev *dev, unsigned n, unsigned on)
{
if (on)
set_gpio_bit(n, dev->regs.out);
else
clr_gpio_bit(n, dev->regs.out);
}
static unsigned int spi_read_byte(ice1712_t *ice)
{
int i;
unsigned int val = 0;
for (i = 0; i < 8; i++) {
val <<= 1;
set_gpio_bit(ice, PONTIS_CS_CLK, 0);
udelay(1);
if (snd_ice1712_gpio_read(ice) & PONTIS_CS_RDATA)
val |= 1;
udelay(1);
set_gpio_bit(ice, PONTIS_CS_CLK, 1);
udelay(1);
}
return val;
}
static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
int i = -EINVAL;
if (offset < NR_MSM_GPIOS) {
set_gpio_bit(offset, GPIO_OE_CLR(offset));
i = 0;
}
return i;
}
static void ak4396_write(struct snd_ice1712 *ice, unsigned int reg,
unsigned int data)
{
unsigned int block;
snd_ice1712_gpio_set_dir(ice, AK4396_CSN|AK4396_CCLK|AK4396_CDTI);
snd_ice1712_gpio_set_mask(ice, ~(AK4396_CSN|AK4396_CCLK|AK4396_CDTI));
set_gpio_bit(ice, AK4396_CSN, 0);
block = ((AK4396_ADDR & 0x03) << 14) | (1 << 13) |
((reg & 0x1f) << 8) | (data & 0xff);
ak4396_send_word(ice, block);
set_gpio_bit(ice, AK4396_CSN, 1);
udelay(1);
snd_ice1712_gpio_set_mask(ice, ice->gpio.write_mask);
snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
}
static void msm_gpio_irq_enable(unsigned int irq)
{
unsigned long irq_flags;
unsigned gpio = irq_to_gpio(irq);
spin_lock_irqsave(&gpio_lock, irq_flags);
set_gpio_bit(gpio, GPIO_OE_CLR(gpio));
writel(DC_IRQ_DISABLE | TARGET_PROC_SCORPION, GPIO_INTR_CFG_SU(gpio));
enable_summary_irq(gpio);
spin_unlock_irqrestore(&gpio_lock, irq_flags);
}
void set_offdelay_shutdown(void)
{
struct gpio *gpio1;
gpio1 = getgpio_byname(NAME_OFF_DELAY);
if (NULL != gpio1) {
set_gpio_bit(gpio1->number, HI_FALSE);
}
return ;
}
static void wm8766_spi_write(struct snd_ice1712 *ice, unsigned int reg,
unsigned int data)
{
unsigned int block;
snd_ice1712_gpio_set_dir(ice, WM8766_SPI_MD|
WM8766_SPI_CLK|WM8766_SPI_ML);
snd_ice1712_gpio_set_mask(ice, ~(WM8766_SPI_MD|
WM8766_SPI_CLK|WM8766_SPI_ML));
set_gpio_bit(ice, WM8766_SPI_ML, 0);
block = (reg << 9) | (data & 0x1ff);
wm8766_spi_send_word(ice, block);
set_gpio_bit(ice, WM8766_SPI_ML, 1);
udelay(1);
snd_ice1712_gpio_set_mask(ice, ice->gpio.write_mask);
snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
}
static int msm_gpio_direction_output(struct gpio_chip *chip,
unsigned offset,
int val)
{
int i = -EINVAL;
if (offset < NR_MSM_GPIOS) {
msm_gpio_set(chip, offset, val);
set_gpio_bit(offset, GPIO_OE_SET(offset));
i = 0;
}
return i;
}
static unsigned int spi_read(ice1712_t *ice, unsigned int dev, unsigned int reg)
{
unsigned int val;
snd_ice1712_gpio_set_dir(ice, PONTIS_CS_CS|PONTIS_CS_WDATA|PONTIS_CS_CLK);
snd_ice1712_gpio_set_mask(ice, ~(PONTIS_CS_CS|PONTIS_CS_WDATA|PONTIS_CS_CLK));
set_gpio_bit(ice, PONTIS_CS_CS, 0);
spi_send_byte(ice, dev & ~1); /* WRITE */
spi_send_byte(ice, reg); /* MAP */
/* trigger */
set_gpio_bit(ice, PONTIS_CS_CS, 1);
udelay(1);
set_gpio_bit(ice, PONTIS_CS_CS, 0);
spi_send_byte(ice, dev | 1); /* READ */
val = spi_read_byte(ice);
/* trigger */
set_gpio_bit(ice, PONTIS_CS_CS, 1);
udelay(1);
/* restore */
snd_ice1712_gpio_set_mask(ice, ice->gpio.write_mask);
snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
return val;
}
static int
gpio_chip_direction_output(struct gpio_chip *chip, unsigned offset, int value)
{
struct msm_gpio_dev *msm_gpio = TO_MSM_GPIO_DEV(chip);
unsigned long irq_flags;
spin_lock_irqsave(&msm_gpio->lock, irq_flags);
msm_gpio_write(msm_gpio, offset, value);
set_gpio_bit(offset, msm_gpio->regs.oe);
spin_unlock_irqrestore(&msm_gpio->lock, irq_flags);
return 0;
}
int msm_gpio_install_direct_irq(unsigned gpio, unsigned irq)
{
int rc = -EINVAL;
unsigned long irq_flags;
if (gpio < NR_MSM_GPIOS && irq < NR_TLMM_SCSS_DIR_CONN_IRQ) {
spin_lock_irqsave(&gpio_lock, irq_flags);
set_gpio_bit(gpio, GPIO_OE_CLR(gpio));
disable_summary_irq(gpio);
writel(DC_IRQ_ENABLE | TARGET_PROC_NONE,
GPIO_INTR_CFG_SU(gpio));
writel(DC_POLARITY_HI | TARGET_PROC_SCORPION | (gpio << 3),
DIR_CONN_INTR_CFG_SU(irq));
spin_unlock_irqrestore(&gpio_lock, irq_flags);
rc = 0;
}
return rc;
}
/*升级FPGA程序*/
static int updateFpgaProgram(const char *fpgafile, int fd,int fpgaNo)
{
int r_cnt1=0,r_cnt2=0;
int ret = 0;
char spidata[PER_READ_LEN];
int spifd = -1;
FILE *fpgafd = NULL;
int readlen = 0;
int writelen = 0;
int totalwritelen = 0;
int flshEnableBit,fpgaProBit,fpgaDoneBit;
//升级FPGA1
if(0 == fpgaNo)
{
flshEnableBit = FLASH_ENABLE_1;
fpgaProBit = FPGA_PRO_1;
fpgaDoneBit = FPGA_DONE_1;
}
else
{
flshEnableBit = FLASH_ENABLE_2;
fpgaProBit = FPGA_PRO_2;
fpgaDoneBit = FPGA_DONE_2;
}
printf("Enter into update FPGA Program \n");
ret = clear_gpio_bit(flshEnableBit, fd);
printf("FLASH_ENABLE ret=%x \n", ret);
clear_gpio_bit(fpgaProBit, fd);
while(1){
usleep(100);
ret = get_gpio_bit(fpgaDoneBit, fd);
if( ret != 0 ){
printf("fpga Done is Not 0!ret:%d\n",ret);
}else{
printf("fpga Done is 0!\n");
break;
}
r_cnt1++;
if( r_cnt1>10){
break;
}
}
if(0 == fpgaNo)
{
ret = system("flash_eraseall /dev/mtd0");
printf(" flash_eraseall /dev/mtd0 ret=%x \n", ret);
spifd = open("/dev/mtd0", O_RDWR, 0);
if(spifd < 0) {
printf("open the SPI flash 0 Failed \n");
ret = -1;
goto cleanup;
}
}
else
{
ret = system("flash_eraseall /dev/mtd1");
printf(" flash_eraseall /dev/mtd1 ret=%x \n", ret);
spifd = open("/dev/mtd1", O_RDWR, 0);
if(spifd < 0) {
printf("open the SPI flash 1 Failed \n");
ret = -1;
goto cleanup;
}
}
fpgafd = fopen(fpgafile, "r+b");
if(fpgafd == NULL) {
printf("open the FPGA bin Failed \n");
ret = -1;
goto cleanup;
}
rewind(fpgafd);
while(1) {
readlen = fread(spidata, 1, PER_READ_LEN, fpgafd);
if(readlen < 1) {
printf("file read end \n");
break;
}
writelen = write(spifd, spidata, readlen);
totalwritelen += writelen;
if(feof(fpgafd)) {
printf("writelen = %d \n", writelen);
writelen = write(spifd, spidata, readlen);
break;
}
}
close(spifd);
spifd = -1;
printf("totalwritelen = %d \n", totalwritelen);
cleanup:
printf("002 flash_eraseall updateFpgaProgram \n");
ret = set_gpio_bit(flshEnableBit, fd);
printf("FLASH_ENABLE ret=%x \n", ret);
if(spifd > 0) {
close(spifd);
}
if(fpgafd) {
fclose(fpgafd);
}
ret = set_gpio_bit(fpgaProBit, fd);
printf("========set_gpio_bit:ret:%d\n",ret);
usleep(300);
while( 1 ) {
ret = get_gpio_bit(fpgaDoneBit, fd);
printf("========get_gpio_bit:ret:%d\n",ret);
if( ret == 0){//正在写，允许写3s
r_cnt1++;
r_cnt2=0;
}else if(1 == ret ){ //写完成，确保5次
r_cnt2++;
r_cnt1=0;
}else{
break;
}
if(r_cnt1 >10 || r_cnt2 >5){
break;
}
usleep(300);
}
return ret;
}
