void set_pcie_dereset(void) { device_t pcie_core_dev; pcie_core_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); set_htiu_enable_bits(pcie_core_dev, 0xA8, 0xFFFFFFFF, 0x6F6F6F6F); set_htiu_enable_bits(pcie_core_dev, 0xA9, 0x000000FF, 0x0000006F); }
/***************************************************************** * The sr5650 uses NBCONFIG:0x1c (BAR3) to map the PCIE Extended Configuration * Space to a 256MB range within the first 4GB of addressable memory. *****************************************************************/ void enable_pcie_bar3(device_t nb_dev) { printk(BIOS_DEBUG, "enable_pcie_bar3()\n"); set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 1 << 30); /* Enables writes to the BAR3 register. */ set_nbcfg_enable_bits(nb_dev, 0x84, 7 << 16, 0 << 16); pci_write_config32(nb_dev, 0x1C, EXT_CONF_BASE_ADDRESS); /* PCIEMiscInit */ pci_write_config32(nb_dev, 0x20, 0x00000000); set_htiu_enable_bits(nb_dev, 0x32, 1 << 28, 1 << 28); /* PCIEMiscInit */ ProgK8TempMmioBase(1, EXT_CONF_BASE_ADDRESS, TEMP_MMIO_BASE_ADDRESS); }
/***************************************** * Some setting is from rpr. Some is from CIMx. *****************************************/ static void rs780_por_htiu_index_init(pci_devfn_t nb_dev) { #if 0 /* get from rpr. */ set_htiu_enable_bits(nb_dev, 0x1C, 0x1<<17, 0x1<<17); set_htiu_enable_bits(nb_dev, 0x06, 0x1<<0, 0x0<<0); set_htiu_enable_bits(nb_dev, 0x06, 0x1<<1, 0x1<<1); set_htiu_enable_bits(nb_dev, 0x06, 0x1<<9, 0x1<<9); set_htiu_enable_bits(nb_dev, 0x06, 0x1<<13, 0x1<<13); set_htiu_enable_bits(nb_dev, 0x06, 0x1<<17, 0x1<<17); set_htiu_enable_bits(nb_dev, 0x06, 0x3<<15, 0x3<<15); set_htiu_enable_bits(nb_dev, 0x06, 0x1<<25, 0x1<<25); set_htiu_enable_bits(nb_dev, 0x06, 0x1<<30, 0x1<<30); set_htiu_enable_bits(nb_dev, 0x07, 0x1<<0, 0x1<<0); set_htiu_enable_bits(nb_dev, 0x07, 0x1<<1, 0x0<<1); set_htiu_enable_bits(nb_dev, 0x07, 0x1<<2, 0x0<<2); set_htiu_enable_bits(nb_dev, 0x07, 0x1<<15, 0x1<<15); set_htiu_enable_bits(nb_dev, 0x0C, 0x3<<0, 0x1<<0); set_htiu_enable_bits(nb_dev, 0x0C, 0x3<<2, 0x2<<2); set_htiu_enable_bits(nb_dev, 0x0C, 0x3<<4, 0x0<<4); /* A12 only */ set_htiu_enable_bits(nb_dev, 0x2D, 0x1<<4, 0x1<<4); set_htiu_enable_bits(nb_dev, 0x2D, 0x1<<6, 0x1<<6); set_htiu_enable_bits(nb_dev, 0x05, 0x1<<2, 0x1<<2); set_htiu_enable_bits(nb_dev, 0x1E, 0xFFFFFFFF, 0xFFFFFFFF); #else /* get from CIM. It is more reliable than above. */ set_htiu_enable_bits(nb_dev, 0x05, (1<<10|1<<9), 1<<10 | 1<<9); set_htiu_enable_bits(nb_dev, 0x06, ~0xFFFFFFFE, 0x04203A202); set_htiu_enable_bits(nb_dev, 0x07, ~0xFFFFFFF9, 0x8001/* | 7 << 8 */); /* fam 10 */ set_htiu_enable_bits(nb_dev, 0x15, ~0xFFFFFFFF, 1<<31| 1<<30 | 1<<27); set_htiu_enable_bits(nb_dev, 0x1C, ~0xFFFFFFFF, 0xFFFE0000); set_htiu_enable_bits(nb_dev, 0x4B, (1<<11), 1<<11); set_htiu_enable_bits(nb_dev, 0x0C, ~0xFFFFFFC0, 1<<0|1<<3); set_htiu_enable_bits(nb_dev, 0x17, (1<<27|1<<1), 0x1<<1); set_htiu_enable_bits(nb_dev, 0x17, 0x1 << 30, 0x1<<30); set_htiu_enable_bits(nb_dev, 0x19, (0xFFFFF+(1<<31)), 0x186A0+(1<<31)); set_htiu_enable_bits(nb_dev, 0x16, (0x3F<<10), 0x7<<10); set_htiu_enable_bits(nb_dev, 0x23, 0xFFFFFFF, 1<<28); set_htiu_enable_bits(nb_dev, 0x1E, 0xFFFFFFFF, 0xFFFFFFFF); #endif }
void rs780_htinit(void) { /* * About HT, it has been done in enumerate_ht_chain(). */ pci_devfn_t cpu_f0, rs780_f0, clk_f1; u32 reg; u8 cpu_ht_freq, ibias; cpu_f0 = PCI_DEV(0, 0x18, 0); /************************ * get cpu's ht freq, in cpu's function 0, offset 0x88 * bit11-8, specifics the maximum operation frequency of the link's transmitter clock. * The link frequency field (Frq) is cleared by cold reset. SW can write a nonzero * value to this reg, and that value takes effect on the next warm reset or * LDTSTOP_L disconnect sequence. * please see the table rs780_ibias about the value and its corresponding frequency. ************************/ reg = pci_read_config32(cpu_f0, 0x88); cpu_ht_freq = (reg & 0xf00) >> 8; printk(BIOS_INFO, "rs780_htinit cpu_ht_freq=%x.\n", cpu_ht_freq); rs780_f0 = PCI_DEV(0, 0, 0); //set_nbcfg_enable_bits(rs780_f0, 0xC8, 0x7<<24 | 0x7<<28, 1<<24 | 1<<28); clk_f1 = PCI_DEV(0, 0, 1); /* We need to make sure the F1 is accessible. */ ibias = rs780_ibias[cpu_ht_freq]; /* If HT freq>1GHz, we assume the CPU is fam10, else it is K8. * Is it appropriate? * Frequency is 1GHz, i.e. cpu_ht_freq is 6, in most cases. * So we check 6 only, it would be faster. */ if ((cpu_ht_freq == 0x6) || (cpu_ht_freq == 0x5) || (cpu_ht_freq == 0x4) || (cpu_ht_freq == 0x2) || (cpu_ht_freq == 0x0)) { printk(BIOS_INFO, "rs780_htinit: HT1 mode\n"); /* HT1 mode, RPR 8.4.2 */ /* set IBIAS code */ set_nbcfg_enable_bits(clk_f1, 0xD8, 0x3FF, ibias); /* Optimizes chipset HT transmitter drive strength */ set_htiu_enable_bits(rs780_f0, 0x2A, 0x3, 0x1); } else if ((cpu_ht_freq > 0x6) && (cpu_ht_freq < 0xf)) { printk(BIOS_INFO, "rs780_htinit: HT3 mode\n"); #if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) /* HT3 mode, RPR 8.4.3 */ set_nbcfg_enable_bits(rs780_f0, 0x9c, 0x3 << 16, 0); /* set IBIAS code */ set_nbcfg_enable_bits(clk_f1, 0xD8, 0x3FF, ibias); /* Optimizes chipset HT transmitter drive strength */ set_htiu_enable_bits(rs780_f0, 0x2A, 0x3, 0x1); /* Enables error-retry mode */ set_nbcfg_enable_bits(rs780_f0, 0x44, 0x1, 0x1); /* Enables scrambling and Disables command throttling */ set_nbcfg_enable_bits(rs780_f0, 0xac, (1 << 3) | (1 << 14), (1 << 3) | (1 << 14)); /* Enables transmitter de-emphasis */ set_nbcfg_enable_bits(rs780_f0, 0xa4, 1 << 31, 1 << 31); /* Enables transmitter de-emphasis level */ /* Sets training 0 time */ set_nbcfg_enable_bits(rs780_f0, 0xa0, 0x3F, 0x14); /* Enables strict TM4 detection */ set_htiu_enable_bits(rs780_f0, 0x15, 0x1 << 22, 0x1 << 22); /* Enables proper DLL reset sequence */ set_htiu_enable_bits(rs780_f0, 0x16, 0x1 << 10, 0x1 << 10); /* HyperTransport 3 Processor register settings to be done in northbridge */ /* Enables error-retry mode */ set_fam10_ext_cfg_enable_bits(cpu_f0, 0x130, 1 << 0, 1 << 0); /* Enables scrambling */ set_fam10_ext_cfg_enable_bits(cpu_f0, 0x170, 1 << 3, 1 << 3); /* Enables transmitter de-emphasis * This depends on the PCB design and the trace */ /* TODO: */ /* Disables command throttling */ set_fam10_ext_cfg_enable_bits(cpu_f0, 0x168, 1 << 10, 1 << 10); /* Sets Training 0 Time. See T0Time table for encodings */ set_fam10_ext_cfg_enable_bits(cpu_f0, 0x16C, 0x3F, 0x20); /* TODO: */ #endif /* CONFIG_NORTHBRIDGE_AMD_AMDFAM10 */ } }
void rs780_enable(device_t dev) { device_t nb_dev, sb_dev; int dev_ind; nb_dev = _pci_make_tag(0, 0, 0); sb_dev = _pci_make_tag(0, 8, 0); _pci_break_tag(dev, NULL, &dev_ind, NULL); switch(dev_ind) { case 0: printk_info("enable_pcie_bar3\n"); enable_pcie_bar3(nb_dev); /* PCIEMiscInit */ printk_info("config_gpp_core\n"); config_gpp_core(nb_dev, sb_dev); printk_info("rs780_gpp_sb_init\n"); rs780_gpp_sb_init(nb_dev, sb_dev, 8); /* set SB payload size: 64byte */ printk_info("set sb payload size:64byte\n"); set_pcie_enable_bits(nb_dev, 0x10 | PCIE_CORE_INDEX_GPPSB, 3 << 11, 2 << 11); /* Bus0Dev0Fun1Clock control init, we have to do it here, for dev0 Fun1 doesn't have a vendor or device ID */ //rs780_config_misc_clk(nb_dev); { /* BTDC: NBPOR_InitPOR function. */ u8 temp8; u16 temp16; u32 temp32; /* BTDC: Program NB PCI table. */ printk_info("Program NB PCI table\n"); temp16 = pci_read_config16(nb_dev, 0x04); printk_debug("BTDC: NB_PCI_REG04 = %x.\n", temp16); temp32 = pci_read_config32(nb_dev, 0x84); printk_debug("BTDC: NB_PCI_REG84 = %x.\n", temp32); pci_write_config8(nb_dev, 0x4c, 0x42); temp8 = pci_read_config8(nb_dev, 0x4e); temp8 |= 0x05; pci_write_config8(nb_dev, 0x4e, temp8); temp32 = pci_read_config32(nb_dev, 0x4c); printk_debug("BTDC: NB_PCI_REG4C = %x.\n", temp32); /* BTDC: disable GFX debug. */ printk_info("disable gfx debug\n"); temp8 = pci_read_config8(nb_dev, 0x8d); temp8 &= ~(1<<1); pci_write_config8(nb_dev, 0x8d, temp8); /* BTDC: set temporary NB TOM to 0x40000000. */ //printk_info("set temporary NB TOM to 0xf0000000\n"); //pci_write_config32(nb_dev, 0x90, 0x40000000); //pci_write_config32(nb_dev, 0x90, 0xf0000000); printk_info("set temporary NB TOM to 0xffffffff\n"); pci_write_config32(nb_dev, 0x90, 0xffffffff); /* BTDC: Program NB HTIU table. */ printk_info("Program NB HTIU table\n"); set_htiu_enable_bits(nb_dev, 0x05, 1<<10 | 1<<9, 1<<10|1<<9); set_htiu_enable_bits(nb_dev, 0x06, 1, 0x4203a202); set_htiu_enable_bits(nb_dev, 0x07, 1<<1 | 1<<2, 0x8001); set_htiu_enable_bits(nb_dev, 0x15, 0, 1<<31 | 1<<30 | 1<<27); set_htiu_enable_bits(nb_dev, 0x1c, 0, 0xfffe0000); set_htiu_enable_bits(nb_dev, 0x4b, 1<<11, 1<<11); set_htiu_enable_bits(nb_dev, 0x0c, 0x3f, 1 | 1<<3); set_htiu_enable_bits(nb_dev, 0x17, 1<<1 | 1<<27, 1<<1); set_htiu_enable_bits(nb_dev, 0x17, 0, 1<<30); set_htiu_enable_bits(nb_dev, 0x19, 0xfffff+(1<<31), 0x186a0+(1<<31)); set_htiu_enable_bits(nb_dev, 0x16, 0x3f<<10, 0x7<<10); set_htiu_enable_bits(nb_dev, 0x23, 0, 1<<28); /* BTDC: Program NB MISC table. */ printk_info("set NB MISC table\n"); set_nbmisc_enable_bits(nb_dev, 0x0b, 0xffff, 0x00000180); set_nbmisc_enable_bits(nb_dev, 0x00, 0xffff, 0x00000106); set_nbmisc_enable_bits(nb_dev, 0x51, 0xffffffff, 0x00100100); set_nbmisc_enable_bits(nb_dev, 0x53, 0xffffffff, 0x00100100); set_nbmisc_enable_bits(nb_dev, 0x55, 0xffffffff, 0x00100100); set_nbmisc_enable_bits(nb_dev, 0x57, 0xffffffff, 0x00100100); set_nbmisc_enable_bits(nb_dev, 0x59, 0xffffffff, 0x00100100); set_nbmisc_enable_bits(nb_dev, 0x5b, 0xffffffff, 0x00100100); set_nbmisc_enable_bits(nb_dev, 0x5d, 0xffffffff, 0x00100100); set_nbmisc_enable_bits(nb_dev, 0x5f, 0xffffffff, 0x00100100); set_nbmisc_enable_bits(nb_dev, 0x20, 1<<1, 0); set_nbmisc_enable_bits(nb_dev, 0x37, 1<<11|1<<12|1<<13|1<<26, 0); set_nbmisc_enable_bits(nb_dev, 0x68, 1<<5|1<<6, 1<<5); set_nbmisc_enable_bits(nb_dev, 0x6b, 1<<22, 1<<10); set_nbmisc_enable_bits(nb_dev, 0x67, 1<<26, 1<<14|1<<10); set_nbmisc_enable_bits(nb_dev, 0x24, 1<<28|1<<26|1<<25|1<<16, 1<<29|1<<25); set_nbmisc_enable_bits(nb_dev, 0x38, 1<<24|1<<25, 1<<24); set_nbmisc_enable_bits(nb_dev, 0x36, 1<<29, 1<<29|1<<28); set_nbmisc_enable_bits(nb_dev, 0x0c, 0, 1<<13); set_nbmisc_enable_bits(nb_dev, 0x34, 1<<22, 1<<10); set_nbmisc_enable_bits(nb_dev, 0x39, 1<<10, 1<<30); set_nbmisc_enable_bits(nb_dev, 0x22, 1<<3, 0); set_nbmisc_enable_bits(nb_dev, 0x68, 1<<19, 0); set_nbmisc_enable_bits(nb_dev, 0x24, 1<<16|1<<17, 1<<17); set_nbmisc_enable_bits(nb_dev, 0x6a, 1<<22|1<<23, 1<<17|1<<23); set_nbmisc_enable_bits(nb_dev, 0x35, 1<<21|1<<22, 1<<22); set_nbmisc_enable_bits(nb_dev, 0x01, 0xffffffff, 0x48); /* BTDC: the last two step. */ set_nbmisc_enable_bits(nb_dev, 0x01, 1<<8, 1<<8); set_htiu_enable_bits(nb_dev, 0x2d, 1<<6|1<<4, 1<<6|1<<4); } break; case 1: /* bus0, dev1, APC. */ printk_info("Bus-0, Dev-1, Fun-0.\n"); rs780_internal_gfx_enable(nb_dev,dev); break; case 2: case 3: set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind, (1 ? 0 : 1) << dev_ind); rs780_gfx_init(nb_dev, dev, dev_ind); break; case 4: /* bus0, dev4-7, four GPP */ case 5: case 6: case 7: enable_pcie_bar3(nb_dev); /* PCIEMiscInit */ set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind, (1 ? 0 : 1) << dev_ind); rs780_gpp_sb_init(nb_dev, dev, dev_ind); break; case 8: /* bus0, dev8, SB */ set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 6, (1 ? 0 : 1) << dev_ind); rs780_gpp_sb_init(nb_dev, dev, dev_ind); disable_pcie_bar3(nb_dev); break; case 9: /* bus 0, dev 9,10, GPP */ case 10: enable_pcie_bar3(nb_dev); /* PCIEMiscInit */ set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << (7 + dev_ind), (1 ? 0 : 1) << (7 + dev_ind)); rs780_gpp_sb_init(nb_dev, dev, dev_ind); break; default: printk_debug("unknown dev: %s\n", dev_ind); } }
/***************************************** * Compliant with CIM_33's ATINB_HTIUNBIND_POR_TABLE *****************************************/ static void rs780_por_htiu_index_init(device_t nb_dev) { printk_info("enter rs780_por_htiu_index_init\n"); //vga lycheng set_htiu_enable_bits(nb_dev, 0x05, (1<<10|1<<9), 1<<10 | 1<<9); set_htiu_enable_bits(nb_dev, 0x06, ~0xFFFFFFFE, 0x04203A202); set_htiu_enable_bits(nb_dev, 0x07, ~0xFFFFFFF9, 0x8001/* | 7 << 8 */); /* fam 10 */ set_htiu_enable_bits(nb_dev, 0x15, ~0xFFFFFFFF, 1<<31| 1<<30 | 1<<27); set_htiu_enable_bits(nb_dev, 0x1C, ~0xFFFFFFFF, 0xFFFE0000); set_htiu_enable_bits(nb_dev, 0x4B, (1<<11), 1<<11); set_htiu_enable_bits(nb_dev, 0x0C, ~0xFFFFFFC0, 1<<0|1<<3); set_htiu_enable_bits(nb_dev, 0x17, (1<<27|1<<1), 0x1<<1); set_htiu_enable_bits(nb_dev, 0x17, 0x1 << 30, 0x1<<30); set_htiu_enable_bits(nb_dev, 0x19, (0xFFFFF+(1<<31)), 0x186A0+(1<<31)); set_htiu_enable_bits(nb_dev, 0x16, (0x3F<<10), 0x7<<10); set_htiu_enable_bits(nb_dev, 0x23, 0xFFFFFFF, 1<<28); set_htiu_enable_bits(nb_dev, 0x1E, 0xFFFFFFFF, 0xFFFFFFFF); /* here we set lower of top of dram2 to 0x0 and enabled*/ printk_info("before lower tom2 is %x, upper tom2 %x\n", htiu_read_indexN(nb_dev, 0x30), htiu_read_indexN(nb_dev, 0x31)); htiu_write_indexN(nb_dev, 0x30, 0x01); htiu_write_indexN(nb_dev, 0x31, 0x80); /* here we set upper of top of dram2 to 0x0 and enabled, so the top * of dram 2 is 0x80 0000 0000 = 512GB*/ printk_info("lower tom2 is %x, upper tom2 %x\n", htiu_read_indexN(nb_dev, 0x30), htiu_read_indexN(nb_dev, 0x31)); printk_info("exit rs780_por_htiu_index_init\n"); }
/***************************************** * Compliant with CIM_33's PCIEGPPInit * nb_dev: * root bridge struct * dev: * p2p bridge struct * port: * p2p bridge number, 4-10 *****************************************/ void sr5650_gpp_sb_init(device_t nb_dev, device_t dev, u32 port) { u32 gpp_sb_sel = 0; struct southbridge_amd_sr5650_config *cfg = (struct southbridge_amd_sr5650_config *)nb_dev->chip_info; printk(BIOS_DEBUG, "gpp_sb_init nb_dev=0x%p, dev=0x%p, port=0x%x\n", nb_dev, dev, port); switch (port) { case 2: case 3: gpp_sb_sel = PCIE_CORE_INDEX_GPP1; break; case 4 ... 7: case 9: case 10: gpp_sb_sel = PCIE_CORE_INDEX_GPP3a; break; case 8: gpp_sb_sel = PCIE_CORE_INDEX_SB; break; case 11: case 12: gpp_sb_sel = PCIE_CORE_INDEX_GPP2; break; case 13: gpp_sb_sel = PCIE_CORE_INDEX_GPP3b; break; } /* Init common Core registers */ set_pcie_enable_bits(dev, 0xB1, 1 << 28 | 1 << 23 | 1 << 20 | 1 << 19, 1 << 28 | 1 << 23 | 1 << 20 | 1 << 19); if (gpp_sb_sel == PCIE_CORE_INDEX_GPP3a) { set_pcie_enable_bits(dev, 0xB1, 1 << 22, 1 << 22); /* 4.3.3.2.3 Step 10: Dynamic Slave CPL Buffer Allocation */ gpp3a_cpl_buf_alloc(nb_dev, dev); } if (gpp_sb_sel == PCIE_CORE_INDEX_GPP1 || gpp_sb_sel == PCIE_CORE_INDEX_GPP2) { gpp12_cpl_buf_alloc(nb_dev, dev); } set_pcie_enable_bits(dev, 0xA1, (1 << 26) | (1 << 24) | (1 << 11), 1 << 11); set_pcie_enable_bits(dev, 0xA0, 0x0000FFF0, 0x6830); // PCIE should not ignore malformed packet error or ATS request set_pcie_enable_bits(dev, 0x70, 1 << 12, 0); //Step 14.1: Advertising Hot Plug Capabilities set_pcie_enable_bits(dev, 0x10, 1 << 4, 1 << 4); //Enable power fault set_pcie_enable_bits(nb_dev, 0xC1 | gpp_sb_sel, 1 << 0, 1 << 0); /* init GPP core */ /* 4.4.2.step13.1. Sets RCB completion timeout to be 200ms */ pci_ext_write_config32(nb_dev, dev, 0x80, 0xF << 0, 0x6 << 0); /* 4.4.2.step13.2. RCB completion timeout on link down to shorten enumeration time. */ set_pcie_enable_bits(dev, 0x70, 1 << 19, 1 << 19); /* 4.4.2.step13.3. Enable slave ordering rules */ set_pcie_enable_bits(nb_dev, 0x20 | gpp_sb_sel, 1 << 8, 0 << 8); /* 4.4.2.step13.4. Sets DMA payload size to 64 bytes. */ set_pcie_enable_bits(nb_dev, 0x10 | gpp_sb_sel, 7 << 10, 4 << 10); /* 4.4.2.step13.5. Set REGS_DLP_IGNORE_IN_L1_EN to ignore DLLPs during L1 so that Tx Clk can be turned off. */ set_pcie_enable_bits(nb_dev, 0x02 | gpp_sb_sel, 1 << 0 | 1 << 8, 1 << 0 | 1 << 8); // add bit 8 from CIMx /* 4.4.2.step13.6. Set REGS_LC_ALLOW_TX_L1_CONTROL to allow TX to prevent LC from going to L1 when there are outstanding completions.*/ set_pcie_enable_bits(dev, 0x02, 1 << 15, 1 << 15); /* 4.4.2.step13.7. Set REGS_LC_DONT_GO_TO_L0S_IF_L1_ARMED to prevent lc to go to from L0 to Rcv_L0s if L1 is armed. */ set_pcie_enable_bits(dev, 0xA1, 1 << 11, 1 << 11); /* 4.4.2.step13.8. CMGOOD_OVERRIDE for all five PCIe cores. */ set_nbmisc_enable_bits(nb_dev, 0x22, 1 << 27, 1 << 27); /* 4.4.2.step13.9. Prevents Electrical Idle from causing a transition from Rcv_L0 to Rcv_L0s. */ set_pcie_enable_bits(dev, 0xB1, 1 << 20, 1 << 20); /* 4.4.2.step13.10. Prevents the LTSSM from going to Rcv_L0s if it has already acknowledged a request to go to L1 but it has not transitioned there yet. */ /* seems the same as step13.7 */ set_pcie_enable_bits(dev, 0xA1, 1 << 11, 1 << 11); /* 4.4.2.step13.11. Transmits FTS before Recovery. */ set_pcie_enable_bits(dev, 0xA3, 1 << 9, 1 << 9); /* 4.4.2.step13.12. Sets TX arbitration algorithm to round robin for PCIE-GPP1, PCIE-GPP2, PCIE-GPP3a and PCIE-GPP3b cores only. */ //if (gpp_sb_sel != PCIE_CORE_INDEX_SB) /* RPR NOT set SB_CORE, BTS set SB_CORE, we comply with BTS */ set_pcie_enable_bits(nb_dev, 0x1C | gpp_sb_sel, 0x7FF, 0x109); /* 4.4.2.step13.13. Sets number of TX Clocks to drain TX Pipe to 0x3.*/ set_pcie_enable_bits(dev, 0xA0, 0xF << 4, 0x3 << 4); /* 4.4.2.step13.14. Lets PI use Electrical Idle from PHY when turning off PLL in L1 at Gen 2 speed instead of Inferred Electrical Idle. NOTE: LC still uses Inferred Electrical Idle. */ set_pcie_enable_bits(nb_dev, 0x40 | gpp_sb_sel, 3 << 14, 2 << 14); /* 4.4.2.step13.15. Turn on rx_fronten_en for all active lanes upon exit from Electrical Idle, rather than being tied to PLL_PDNB. */ set_pcie_enable_bits(nb_dev, 0xC2 | gpp_sb_sel, 1 << 25, 1 << 25); /* 4.4.2.step13.16. Advertises TX L0s and L1 exit latency. TX L0s exit latency to be 100b: 512ns to less than 1us; L1 exit latency to be 011b: 4us to less than 8us. For Hot-Plug Slots: Advertise TX L0s and L1 exit latency. TX L0s exit latency to be 110b: 2us to 4us. L1 exit latency to be 111b: more than 64us.*/ //set_pcie_enable_bits(dev, 0xC1, 0xF << 0, 0xC << 0); /* 0xF for htplg. */ set_pcie_enable_bits(dev, 0xC1, 0xF << 0, 0xF << 0); /* 0xF for htplg. */ /* 4.4.2.step13.17. Always ACK an ASPM L1 entry DLLP to workaround credit control issue on PM_NAK message of SB700 and SB800. */ /* 4.4.4.step13.18. To allow advertising Gen 2 capabilities to Southbridge. */ if (port == 8) { set_pcie_enable_bits(dev, 0xA0, 1 << 23, 1 << 23); set_pcie_enable_bits(nb_dev, 0xC1 | gpp_sb_sel, 1 << 1, 1 << 1); } /* 4.4.2.step13.19. CMOS Option (Gen 2 AUTO-Part 1 - Enabled by Default) */ /* 4.4.2.step13.20. CMOS Option (RC Advertised Gen 2-Part1 - Disabled by Default)*/ set_nbcfg_enable_bits(dev, 0x88, 0xF << 0, 0x2 << 0); /* Disables GEN2 capability of the device. * RPR typo- it says enable but the bit setting says disable. * Disable it here and we enable it later. */ set_pcie_enable_bits(dev, 0xA4, 1 << 0, 1 << 0); /* 4.4.2.step13.21. */ /* 4.4.2.step13.22 */ /* Enable native PME. */ set_pcie_enable_bits(dev, 0x10, 1 << 3, 1 < 3); /* This bit when set indicates that the PCIe Link associated with this port is connected to a slot. */ pci_ext_write_config32(nb_dev, dev, 0x5a, 1 << 8, 1 << 8); /* This bit when set indicates that this slot is capable of supporting Hot-Plug operations. */ set_nbcfg_enable_bits(dev, 0x6C, 1 << 6, 1 << 6); /* Enables flushing of TLPs when Data Link is down. */ set_pcie_enable_bits(dev, 0x20, 1 << 19, 0 << 19); /* 4.4.2.step14. Server Class Hot Plug Feature */ /* 4.4.2 step14.1: Advertising Hot Plug Capabilities */ /* 4.4.2.step14.2: Firmware Upload */ /* 4.4.2.Step14.3: SBIOS Acknowledgment to Firmware of Successful Firmware Upload */ /* step14.4 */ /* step14.5 */ /* skip */ /* CIMx LPC Deadlock workaround - Enable Memory Write Map*/ if (gpp_sb_sel == PCIE_CORE_INDEX_SB) { set_pcie_enable_bits(nb_dev, 0x10 | gpp_sb_sel, 1 << 9, 1 << 9); set_htiu_enable_bits(nb_dev, 0x06, 1 << 26, 1 << 26); } /* This CPL setup requires more than this one register and should be done in gpp_core. * The additional setup is for the different revisions. */ /* CIMx CommonPortInit settings that are not set above. */ pci_ext_write_config32(nb_dev, dev, 0x88, 0xF0, 1 << 0); /* LINK_CRTL2 */ if ( port == 8 ) set_pcie_enable_bits(dev, 0xA0, 0, 1 << 23); /* set automatic Gen2 support, needs mainboard config option as Gen2 can cause issues on some platforms. */ init_gen2(nb_dev, dev, port); set_pcie_enable_bits(dev, 0xA4, 1 << 29, 1 << 29); set_pcie_enable_bits(dev, 0xC0, 1 << 15, 0); set_pcie_enable_bits(dev, 0xA2, 1 << 13, 0); /* Hotplug Support - bit5 + bit6 capable and surprise */ pci_ext_write_config32(nb_dev, dev, 0x6c, 0x60, 0x60); /* Set interrupt pin info 0x3d */ pci_ext_write_config32(nb_dev, dev, 0x3c, 1 << 8, 1 << 8); /* 5.12.9.3 Hotplug step 1 - NB_PCIE_ROOT_CTRL - enable pm irq The RPR is wrong - this is not a PCIEND_P register */ pci_ext_write_config32(nb_dev, dev, 0x74, 1 << 3, 1 << 3); /* 5.12.9.3 step 2 - PCIEP_PORT_CNTL - enable hotplug messages */ if ( port != 8) set_pcie_enable_bits(dev, 0x10, 1 << 2, 1 << 2); /* Not sure about this PME setup */ /* Native PME */ set_pcie_enable_bits(dev, 0x10, 1 << 3, 1 << 3); /* Not set in CIMx */ /* PME Enable */ pci_ext_write_config32(nb_dev, dev, 0x54, 1 << 8, 1 << 8); /* Not in CIMx */ /* 4.4.3 Training for GPP devices */ /* init GPP */ switch (port) { case 2: case 3: case 4: /* GPP_SB */ case 5: case 6: case 7: case 9: /*GPP*/ case 10: case 11: case 12: case 13: /* 4.4.2.step13.5. Blocks DMA traffic during C3 state */ set_pcie_enable_bits(dev, 0x10, 1 << 0, 0 << 0); /* Enabels TLP flushing */ set_pcie_enable_bits(dev, 0x20, 1 << 19, 0 << 19); /* check port enable */ if (cfg->port_enable & (1 << port)) { PcieReleasePortTraining(nb_dev, dev, port); if (!(AtiPcieCfg.Config & PCIE_GPP_COMPLIANCE)) { u8 res = PcieTrainPort(nb_dev, dev, port); printk(BIOS_DEBUG, "PcieTrainPort port=0x%x result=%d\n", port, res); if (res) { AtiPcieCfg.PortDetect |= 1 << port; } } } break; case 8: /* SB */ break; default: break; } /* Re-enable RC ordering logic after training (from CIMx)*/ set_pcie_enable_bits(nb_dev, 0x20 | gpp_sb_sel, 1 << 9, 0); /* Advertising Hot Plug Capabilities */ pci_ext_write_config32(nb_dev, dev, 0x6c, 0x04001B, 0x00001B); /* PCIE Late Init (CIMx late init - Maybe move somewhere else? Later in the coreboot PCI device enum?) */ /* Set Slot Number */ pci_ext_write_config32(nb_dev, dev, 0x6c, 0x1FFF << 19, port << 19); /* Set Slot present 0x5A*/ pci_ext_write_config32(nb_dev, dev, 0x58, 1 << 24, 1 << 24); //PCIE-GPP1 TXCLK Clock Gating In L1 Late Core sttting - Maybe move somewhere else? */ set_pcie_enable_bits(nb_dev, 0x11 | gpp_sb_sel, 0xF << 0, 0x0C << 0); /* Enable powering down PLLs in L1 or L23 Ready states. * Turns off PHY`s RX FRONTEND during L1 when PLL power down is enabled */ set_pcie_enable_bits(nb_dev, 0x40 | gpp_sb_sel, 0x1219, 0x1009); /* 4.4..7.1 TXCLK Gating in L1, Enables powering down TXCLK clock pads on the receive side. */ set_pcie_enable_bits(nb_dev, 0x40 | gpp_sb_sel, 1 << 6, 1 << 6); /* Step 21: Register Locking PCIE Misc. Late Core sttting - Must move somewhere do PciInitLate FIXME */ /* Lock HWInit Register */ //set_pcie_enable_bits(nb_dev, 0x10 | gpp_sb_sel, 1 << 0, 1 << 0); /* Step 27: LCLK Gating */ //EnableLclkGating(dev); /* Set Common Clock */ /* If dev present, set PcieCapPtr+0x10, BIT6); * set dev 0x68,bit 6 * retrain link, set dev, 0x68 bit 5; * wait dev 0x6B bit3 clear */ if (port == 8){ PciePowerOffGppPorts(nb_dev, dev, port); /* , This should be run for all ports that are not hotplug and don't detect devices */ } }
/***************************************** * Compliant with CIM_33's ATINB_MiscClockCtrl *****************************************/ void static rs690_config_misc_clk(device_t nb_dev) { u32 reg; u16 word; /* u8 byte; */ struct bus pbus; /* fake bus for dev0 fun1 */ reg = pci_read_config32(nb_dev, 0x4c); reg |= 1 << 0; pci_write_config32(nb_dev, 0x4c, reg); word = pci_cf8_conf1.read16(&pbus, 0, 1, 0xf8); word &= 0xf00; pci_cf8_conf1.write16(&pbus, 0, 1, 0xf8, word); word = pci_cf8_conf1.read16(&pbus, 0, 1, 0xe8); word &= ~((1 << 12) | (1 << 13) | (1 << 14)); word |= 1 << 13; pci_cf8_conf1.write16(&pbus, 0, 1, 0xe8, word); reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x94); reg &= ~((1 << 16) | (1 << 24) | (1 << 28)); pci_cf8_conf1.write32(&pbus, 0, 1, 0x94, reg); reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x8c); reg &= ~((1 << 13) | (1 << 14) | (1 << 24) | (1 << 25)); reg |= 1 << 13; pci_cf8_conf1.write32(&pbus, 0, 1, 0x8c, reg); reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0xcc); reg |= 1 << 24; pci_cf8_conf1.write32(&pbus, 0, 1, 0xcc, reg); reg = nbmc_read_index(nb_dev, 0x7a); reg &= ~0x3f; reg |= 1 << 2; reg &= ~(1 << 6); set_htiu_enable_bits(nb_dev, 0x05, 1 << 11, 1 << 11); nbmc_write_index(nb_dev, 0x7a, reg); /* Powering Down efuse and strap block clocks after boot-up. GFX Mode. */ reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0xcc); reg &= ~(1 << 23); reg |= 1 << 24; pci_cf8_conf1.write32(&pbus, 0, 1, 0xcc, reg); #if 0 /* Powerdown reference clock to graphics core PLL in northbridge only mode */ reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x8c); reg |= 1 << 21; pci_cf8_conf1.write32(&pbus, 0, 1, 0x8c, reg); /* Powering Down efuse and strap block clocks after boot-up. NB Only Mode. */ reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0xcc); reg |= (1 << 23) | (1 << 24); pci_cf8_conf1.write32(&pbus, 0, 1, 0xcc, reg); /* Powerdown clock to memory controller in northbridge only mode */ byte = pci_cf8_conf1.read8(&pbus, 0, 1, 0xe4); byte |= 1 << 0; pci_cf8_conf1.write8(&pbus, 0, 1, 0xe4, reg); /* CLKCFG:0xE8 Bit[17] = 0x1 Powerdown clock to IOC GFX block in no external graphics mode */ /* TODO: */ #endif reg = pci_read_config32(nb_dev, 0x4c); reg &= ~(1 << 0); pci_write_config32(nb_dev, 0x4c, reg); set_htiu_enable_bits(nb_dev, 0x05, 7 << 8, 7 << 8); }
/* * nb_misc_clock : * rs690 misc clock parameters setting */ static void nb_misc_clock(void) { pcitag_t clk_dev = _pci_make_tag(0, 0, 1); pcitag_t nb_dev = _pci_make_tag(0, 0, 0); pcitag_t gfx_dev2 = _pci_make_tag(0, 2, 0); u8 rev = get_nb_revision(); u32 val; /* visible CLK func */ set_nbcfg_enable_bits(nb_dev, 0x4C, 1 << 0, 1 << 0); if(ati_nb_cfg.ext_config & EXT_DEBUG_NB_DYNAMIC_CLK){ /* disable NB dynamic clock to htiu rx */ set_nbcfg_enable_bits(clk_dev, 0xE8, 0x07 << 12, 1 << 13); /* ENABLE : CLKGATE_DIS_GFX_TXCLK & CLKGATE_DIS_GPPSB_CCLK & CLKGATE_DIS_CFG_S1X */ set_nbcfg_enable_bits(clk_dev, 0x94, (1 << 16) | (1 << 24) | (1 << 28), 0); /* ENABEL : CLKDATE_DIS_IOC_CCLK_MST/SLV, enabel clkdate for C/MCLK goto BIF branch */ set_nbcfg_enable_bits(clk_dev, 0x8C, (1 << 13) | (1 << 14) | (1 << 24) | (1 << 25), 0); if(rev < REV_RS690_A21){ /* CKLGATE_DIS_IO_CCLK_MST */ set_nbcfg_enable_bits(clk_dev, 0x8C, 1 << 13, 1 << 13); } /* Powering Down efuse and strap block clocks in GFX mode as default */ set_nbcfg_enable_bits(clk_dev, 0xCC, 1 << 24, 1 << 24); /* dynamic clock setting for MC and HTIU */ val = nbmc_read_index(nb_dev, 0x7A); val &= 0xffffffc0; val |= 1 << 2; if(rev >= REV_RS690_A21){ val &= ~(1 << 6); set_htiu_enable_bits(nb_dev, 0x05, 1 << 11, 1 << 11); } nbmc_write_index(nb_dev, 0x7A, val); if(ati_nb_cfg.gfx_config & (GFX_SP_ENABLE | GFX_UMA_ENABLE)){ /* Powering Down efuse and strap block clocks in GFX mode : PWM???*/ set_nbcfg_enable_bits(clk_dev, 0xCC, (1 << 23) | (1 << 24), 1 << 24); }else{ /* nb only mode */ /* Powers down reference clock to graphics core PLL */ set_nbcfg_enable_bits(clk_dev, 0x8C, 1 << 21, 1 << 21); /* Powering Down efuse and strap block clocks after boot-up */ set_nbcfg_enable_bits(clk_dev, 0xCC, (1 << 23) | (1 << 24), (1 << 23) | (1 << 24)); /* powerdown clock to MC */ set_nbcfg_enable_bits(clk_dev, 0xE4, 1 << 0, 1 << 0); } if(ati_nb_cfg.pcie_gfx_info == 0){ if(_pci_conf_read(gfx_dev2, 0x00) == 0xffffffff){ /* Powerdown GFX ports clock when no external GFX detected */ set_nbcfg_enable_bits(clk_dev, 0xE8, 1 << 17, 1 << 17); } } } /* hide CLK func */ set_nbcfg_enable_bits(nb_dev, 0x4C, 1 << 0, 0 << 0); if(rev >= REV_RS690_A21){ set_htiu_enable_bits(nb_dev, 0x05, (1 << 8) | (1 << 9), (1 << 8) | (1 << 9)); set_htiu_enable_bits(nb_dev, 0x05, (1 << 10), (1 << 10)); } DEBUG_INFO("NB POST STAGE : nb_misc_clock function : should we use PWM for efuse and strap powerdown?\n"); return; }