Exemple #1
0
int i2s_tx_init(struct i2stx_info *pi2s_tx)
{
	int ret;
	struct i2s_reg *i2s_reg =
				(struct i2s_reg *)pi2s_tx->base_address;

	/* Initialize GPIO for I2s */
	exynos_pinmux_config(PERIPH_ID_I2S1, 0);

	/* Set EPLL Clock */
	ret = set_epll_clk(pi2s_tx->audio_pll_clk);
	if (ret != 0) {
		debug("%s: epll clock set rate falied\n", __func__);
		return -1;
	}

	/* Select Clk Source for Audio1 */
	set_i2s_clk_source();

	/* Set Prescaler to get MCLK */
	set_i2s_clk_prescaler(pi2s_tx->audio_pll_clk,
				(pi2s_tx->samplingrate * (pi2s_tx->rfs)));

	/* Configure I2s format */
	ret = i2s_set_fmt(i2s_reg, (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
				SND_SOC_DAIFMT_CBM_CFM));
	if (ret == 0) {
		i2s_set_lr_framesize(i2s_reg, pi2s_tx->rfs);
		ret = i2s_set_samplesize(i2s_reg, pi2s_tx->bitspersample);
		if (ret != 0) {
			debug("%s:set sample rate failed\n", __func__);
			return -1;
		}

		i2s_set_bitclk_framesize(i2s_reg, pi2s_tx->bfs);
		/* disable i2s transfer flag and flush the fifo */
		i2s_txctrl(i2s_reg, I2S_TX_OFF);
		i2s_fifo(i2s_reg, FIC_TXFLUSH);
	} else {
		debug("%s: failed\n", __func__);
	}

	return ret;
}
Exemple #2
0
static int i2s_tx_init(struct i2s_uc_priv *pi2s_tx)
{
	int ret;
	struct i2s_reg *i2s_reg = (struct i2s_reg *)pi2s_tx->base_address;

	if (pi2s_tx->id == 0) {
		/* Initialize GPIO for I2S-0 */
		exynos_pinmux_config(PERIPH_ID_I2S0, 0);

		/* Set EPLL Clock */
		ret = set_epll_clk(pi2s_tx->samplingrate * pi2s_tx->rfs * 4);
	} else if (pi2s_tx->id == 1) {
		/* Initialize GPIO for I2S-1 */
		exynos_pinmux_config(PERIPH_ID_I2S1, 0);

		/* Set EPLL Clock */
		ret = set_epll_clk(pi2s_tx->audio_pll_clk);
	} else {
		debug("%s: unsupported i2s-%d bus\n", __func__, pi2s_tx->id);
		return -ERANGE;
	}

	if (ret) {
		debug("%s: epll clock set rate failed\n", __func__);
		return ret;
	}

	/* Select Clk Source for Audio 0 or 1 */
	ret = set_i2s_clk_source(pi2s_tx->id);
	if (ret) {
		debug("%s: unsupported clock for i2s-%d\n", __func__,
		      pi2s_tx->id);
		return ret;
	}

	if (pi2s_tx->id == 0) {
		/*Reset the i2s module */
		writel(CON_RESET, &i2s_reg->con);

		writel(MOD_OP_CLK | MOD_RCLKSRC, &i2s_reg->mod);
		/* set i2s prescaler */
		writel(PSREN | PSVAL, &i2s_reg->psr);
	} else {
		/* Set Prescaler to get MCLK */
		ret = set_i2s_clk_prescaler(pi2s_tx->audio_pll_clk,
				(pi2s_tx->samplingrate * (pi2s_tx->rfs)),
				pi2s_tx->id);
	}
	if (ret) {
		debug("%s: unsupported prescalar for i2s-%d\n", __func__,
		      pi2s_tx->id);
		return ret;
	}

	/* Configure I2s format */
	ret = i2s_set_fmt(i2s_reg, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
			  SND_SOC_DAIFMT_CBM_CFM);
	if (ret == 0) {
		i2s_set_lr_framesize(i2s_reg, pi2s_tx->rfs);
		ret = i2s_set_samplesize(i2s_reg, pi2s_tx->bitspersample);
		if (ret != 0) {
			debug("%s:set sample rate failed\n", __func__);
			return ret;
		}

		i2s_set_bitclk_framesize(i2s_reg, pi2s_tx->bfs);
		/* disable i2s transfer flag and flush the fifo */
		i2s_txctrl(i2s_reg, I2S_TX_OFF);
		i2s_fifo(i2s_reg, FIC_TXFLUSH);
	} else {
		debug("%s: failed\n", __func__);
	}

	return ret;
}