/*************************************************************************
* @brief Activate internal bootloader using GPIO RESET pin.
*
* @param None
* @retval None
************************************************************************/
void BlueNRG_HW_Bootloader (void)
{
set_irq_as_output();
BlueNRG_RST();
set_irq_as_input();
}
/**
* @brief Manage the SPI transmit
* @param TransmitRequest: the transmit request
* @retval None
*/
static void SPI_Transmit_Manager(SPI_TRANSMIT_REQUEST_t TransmitRequest)
{
/*
* Disable both DMA
*/
__HAL_DMA_DISABLE(SPI_Context.hspi->hdmatx);
__HAL_DMA_DISABLE(SPI_Context.hspi->hdmarx);
__HAL_DMA_DISABLE_IT(SPI_Context.hspi->hdmarx, DMA_IT_TC); /**< Disable Receive packet notification */
__HAL_DMA_CLEAR_FLAG(SPI_Context.hspi->hdmatx, BNRG_SPI_TX_DMA_TC_FLAG); /**< Clear flag in DMA */
HAL_NVIC_ClearPendingIRQ(BNRG_SPI_DMA_TX_IRQn); /**< Clear DMA pending bit in NVIC */
__HAL_DMA_ENABLE_IT(SPI_Context.hspi->hdmatx, DMA_IT_TC); /**< Enable Transmit packet notification */
__HAL_BLUENRG_DMA_SET_MINC(SPI_Context.hspi->hdmatx); /**< Configure DMA to send Tx packet */
switch (TransmitRequest)
{
case SPI_HEADER_TRANSMIT:
SPI_Context.SPI_Transmit_Context.Spi_Transmit_Event = SPI_HEADER_TRANSMITTED;
#ifdef ENABLE_SPI_FIX
set_irq_as_input();
#endif
__HAL_BLUENRG_DMA_SET_COUNTER(SPI_Context.hspi->hdmatx, SPI_Context.SPI_Transmit_Context.header_size); /**< Set counter in DMA TX */
__HAL_BLUENRG_DMA_SET_MEMORY_ADDRESS(SPI_Context.hspi->hdmatx, (uint32_t)SPI_Context.SPI_Transmit_Context.header_data); /**< Set memory address in DMA TX */
break;
case SPI_PAYLOAD_TRANSMIT:
SPI_Context.SPI_Transmit_Context.Spi_Transmit_Event = SPI_PAYLOAD_TRANSMITTED;
__HAL_BLUENRG_DMA_SET_COUNTER(SPI_Context.hspi->hdmatx, SPI_Context.SPI_Transmit_Context.payload_size_to_transmit); /**< Set counter in DMA TX */
__HAL_BLUENRG_DMA_SET_MEMORY_ADDRESS(SPI_Context.hspi->hdmatx, (uint32_t)SPI_Context.SPI_Transmit_Context.payload_data); /**< Set memory address in DMA TX */
break;
default:
break;
}
__HAL_DMA_ENABLE(SPI_Context.hspi->hdmatx); /**< Enable DMA TX */
}
/**
* @brief Writes data from local buffer to SPI.
* @param hspi : Handle of the STM32Cube HAL SPI interface
* @param data1 : First data buffer to be written
* @param data2 : Second data buffer to be written
* @param Nb_bytes1: Size of first data buffer to be written
* @param Nb_bytes2: Size of second data buffer to be written
* @retval Number of read bytes
*/
int32_t BlueNRG_SPI_Write(SPI_HandleTypeDef * hspi, uint8_t * data1,
uint8_t * data2, uint8_t Nb_bytes1, uint8_t Nb_bytes2)
{
int32_t result = 0;
int32_t spi_fix_enabled = 0;
#ifdef ENABLE_SPI_FIX
spi_fix_enabled = 1;
#endif //ENABLE_SPI_FIX
unsigned char header_master[HEADER_SIZE] =
{ 0x0a, 0x00, 0x00, 0x00, 0x00 };
unsigned char header_slave[HEADER_SIZE] =
{ 0xaa, 0x00, 0x00, 0x00, 0x00 };
unsigned char read_char_buf[MAX_BUFFER_SIZE];
Disable_SPI_IRQ();
/*
If the SPI_FIX is enabled the IRQ is set in Output mode, then it is pulled
high and, after a delay of at least 112us, the CS line is asserted and the
header transmit/receive operations are started.
After these transmit/receive operations the IRQ is reset in input mode.
*/
if (spi_fix_enabled) {
set_irq_as_output();
/* Assert CS line after at least 112us */
us150Delay();
}
/* CS reset */
HAL_GPIO_WritePin(BNRG_SPI_CS_PORT, BNRG_SPI_CS_PIN, GPIO_PIN_RESET);
/* Exchange header */
HAL_SPI_TransmitReceive(hspi, header_master, header_slave, HEADER_SIZE,
TIMEOUT_DURATION);
if (spi_fix_enabled) {
set_irq_as_input();
}
if (header_slave[0] == 0x02) {
/* SPI is ready */
if (header_slave[1] >= (Nb_bytes1 + Nb_bytes2)) {
/* Buffer is big enough */
if (Nb_bytes1 > 0) {
HAL_SPI_TransmitReceive(hspi, data1,
read_char_buf,
Nb_bytes1,
TIMEOUT_DURATION);
}
if (Nb_bytes2 > 0) {
HAL_SPI_TransmitReceive(hspi, data2,
read_char_buf,
Nb_bytes2,
TIMEOUT_DURATION);
}
} else {
/* Buffer is too small */
result = -2;
}
} else {
/* SPI is not ready */
result = -1;
}
/* Release CS line */
HAL_GPIO_WritePin(BNRG_SPI_CS_PORT, BNRG_SPI_CS_PIN, GPIO_PIN_SET);
Enable_SPI_IRQ();
return result;
}
/*******************************************************************************
* @brief Writes data from local buffer to SPI.
*
* @param hspi : Handle of the STM32Cube HAL SPI interface
* @param data1 : First data buffer to be written
* @param data2 : Second data buffer to be written
* @param Nb_bytes1: Size of first data buffer to be written
* @param Nb_bytes2: Size of second data buffer to be written
* @retval Number of read bytes
*
* Called by: Hal_Write_Serial
*
*
* _All_ those routines call this using a hardcoded pointer to &SpiHandle.
* CALLERs: aci_write_hal_config -> hci_send_cmd -> hci_write -> Hal_Write_Serial()
* aci_gatt_init -> hci_send_cmd -> hci_write -> Hal_Write_Serial()
* aci_gap_init -> hci_send_cmd -> hci_write -> Hal_Write_Serial()
*******************************************************************************/
int32_t BlueNRG_SPI_Write (SPI_HandleTypeDef *hspi, uint8_t* data1,
uint8_t* data2, uint8_t Nb_bytes1, uint8_t Nb_bytes2)
{
int32_t result = 0;
int32_t spi_fix_enabled = 0;
#ifdef ENABLE_SPI_FIX
spi_fix_enabled = 1;
#endif //ENABLE_SPI_FIX
unsigned char header_master[HEADER_SIZE] = {0x0a, 0x00, 0x00, 0x00, 0x00};
unsigned char header_slave[HEADER_SIZE] = {0xaa, 0x00, 0x00, 0x00, 0x00};
unsigned char read_char_buf [MAX_BUFFER_SIZE];
Disable_SPI_IRQ();
/*
** If the SPI_FIX is enabled, the IRQ is set in Output mode, then it is pulled
** high and, after a delay of at least 112us, the CS line is asserted and the
** header transmit/receive operations are started.
** After these transmit/receive operations the IRQ is reset in input mode.
*/
if (spi_fix_enabled)
{
set_irq_as_output();
// VVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVV
// WVD ??? !!! CROSS_PLATFORM EXPOSURE - esp for FASTER DEVICES !!! ???
// VVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVV
/* Wait to Assert CS line until after at least 112us */
us150Delay();
}
/* ASSERT CS line */
////HAL_GPIO_WritePin (BNRG_SPI_CS_PORT, BNRG_SPI_CS_PIN, GPIO_PIN_RESET);
ASSERT_CS_BlueNRG(); // Ensure CS is set to ACTIVE
/* Exchange header with BlueNRG */
////HAL_SPI_TransmitReceive (hspi, header_master, header_slave, HEADER_SIZE, TIMEOUT_DURATION); // WORKS
spi_Write_Read (BLE_BLUENRG_SPI_ID, header_master, header_slave,
HEADER_SIZE, 0);
if (spi_fix_enabled)
{
set_irq_as_input();
}
if (header_slave[0] == 0x02)
{
/* SPI is ready */
if (header_slave[1] >= (Nb_bytes1+Nb_bytes2))
{
/* ensure Buffer is big enough */
if (Nb_bytes1 > 0)
{
//// HAL_SPI_TransmitReceive (hspi, data1, read_char_buf, Nb_bytes1, TIMEOUT_DURATION);
spi_Write_Read (BLE_BLUENRG_SPI_ID,
data1, read_char_buf,
Nb_bytes1, 0);
}
if (Nb_bytes2 > 0)
{
//// HAL_SPI_TransmitReceive (hspi, data2, read_char_buf, Nb_bytes2, TIMEOUT_DURATION);
spi_Write_Read (BLE_BLUENRG_SPI_ID,
data2, read_char_buf,
Nb_bytes2, 0);
}
}
else {
/* Buffer is too small */
result = -2;
}
}
else {
/* SPI is not ready */
result = -1;
}
/* Release CS line */
////HAL_GPIO_WritePin (BNRG_SPI_CS_PORT, BNRG_SPI_CS_PIN, GPIO_PIN_SET);
DEASSERT_CS_BlueNRG(); // Ensure CS is set to NOT active
Enable_SPI_IRQ();
return result;
}
