void init_registers () { set_register_cache (regs_ppc, sizeof (regs_ppc) / sizeof (regs_ppc[0])); gdbserver_expedite_regs = expedite_regs_ppc; }
void amd64_init_architecture (struct valgrind_target_ops *target) { *target = low_target; if (have_avx()) dyn_num_regs = max_num_regs; else dyn_num_regs = max_num_regs - 16; // remove the AVX "high" registers. target->num_regs = dyn_num_regs; set_register_cache (regs, dyn_num_regs); gdbserver_expedite_regs = expedite_regs; }
void initialize_shadow_low(Bool shadow_mode) { if (non_shadow_reg_defs == NULL) { non_shadow_reg_defs = the_low_target.reg_defs; non_shadow_num_regs = the_low_target.num_regs; } regcache_invalidate(); if (the_low_target.reg_defs != non_shadow_reg_defs) { free (the_low_target.reg_defs); } if (shadow_mode) { the_low_target.num_regs = 3 * non_shadow_num_regs; the_low_target.reg_defs = build_shadow_arch (non_shadow_reg_defs, non_shadow_num_regs); } else { the_low_target.num_regs = non_shadow_num_regs; the_low_target.reg_defs = non_shadow_reg_defs; } set_register_cache (the_low_target.reg_defs, the_low_target.num_regs); }
void tilegx_init_architecture ( struct valgrind_target_ops *target ) { *target = low_target; set_register_cache (regs, num_regs); gdbserver_expedite_regs = expedite_regs; }