static void SyncPRG(void)
{
setprg8(0x8000,PRG[0]);
setprg8(0xa000,PRG[1]);
setprg8(0xc000,PRG[2]);
setprg8(0xe000,0x3F);
}
static void Sync(void)
{
uint8 i;
setprg8r(0x10,0x6000,0);
setprg8(0x8000,prg[0]);
setprg8(0xa000,prg[1]);
setprg8(0xc000,~1);
setprg8(0xe000,~0);
for(i=0; i<8; i++)
{
uint32 chr = chrlo[i]|(chrhi[i]<<8);
if(chrlo[i]==0xc8)
{
vlock = 0;
continue;
}
else if(chrlo[i]==0x88)
{
vlock = 1;
continue;
}
if(((chrlo[i]==4)||(chrlo[i]==5))&&!vlock)
setchr1r(0x10,i<<10,chr&1);
else
setchr1(i<<10,chr);
}
switch(mirr)
{
case 0: setmirror(MI_V); break;
case 1: setmirror(MI_H); break;
case 2: setmirror(MI_0); break;
case 3: setmirror(MI_1); break;
}
}
static DECLFW(Mapper95_write)
{
switch(A&0xF001)
{
case 0x8000:
cmd = V;
break;
case 0x8001:
switch(cmd&0x07)
{
case 0: DRegs[0]=(V&0x3F)>>1;toot();V>>=1;setchr2(0x0000,V&0x1F);break;
case 1: DRegs[1]=(V&0x3F)>>1;toot();V>>=1;setchr2(0x0800,V&0x1F);break;
case 2: DRegs[2]=V&0x3F;toot();setchr1(0x1000,V&0x1F); break;
case 3: DRegs[3]=V&0x3F;toot();setchr1(0x1400,V&0x1F); break;
case 4: DRegs[4]=V&0x3F;toot();setchr1(0x1800,V&0x1F); break;
case 5: DRegs[5]=V&0x3F;toot();setchr1(0x1C00,V&0x1F); break;
case 6: DRegs[6]=V&0x3F;
setprg8(0x8000,V);
break;
case 7: DRegs[7]=V&0x3F;
setprg8(0xA000,V);
break;
}
break;
}
}
static void UNLYOKOSync(void)
{
setmirror((mode & 1)^1);
setchr2(0x0000,reg[3]);
setchr2(0x0800,reg[4]);
setchr2(0x1000,reg[5]);
setchr2(0x1800,reg[6]);
if(mode & 0x10)
{
uint32 base = (bank & 8) << 1;
setprg8(0x8000,(reg[0]&0x0f)|base);
setprg8(0xA000,(reg[1]&0x0f)|base);
setprg8(0xC000,(reg[2]&0x0f)|base);
setprg8(0xE000,0x0f|base);
}
else
{
if(mode & 8)
setprg32(0x8000,bank >> 1);
else
{
setprg16(0x8000,bank);
setprg16(0xC000,~0);
}
}
static void Synco(void)
{
int x;
if(cmd&0x20)
{
setchr1wrap(0x0000,DRegs[0]);
setchr1wrap(0x0800,DRegs[1]);
setchr1wrap(0x0400,DRegs[8]);
setchr1wrap(0x0c00,DRegs[9]);
}
else
{
setchr1wrap(0x0000,(DRegs[0]&0xFE));
setchr1wrap(0x0400,(DRegs[0]&0xFE)|1);
setchr1wrap(0x0800,(DRegs[1]&0xFE));
setchr1wrap(0x0C00,(DRegs[1]&0xFE)|1);
}
for(x=0;x<4;x++)
setchr1wrap(0x1000+x*0x400,DRegs[2+x]);
setprg8(0x8000,DRegs[6]);
setprg8(0xA000,DRegs[7]);
setprg8(0xC000,DRegs[10]);
}
static void Sync(void) {
setprg8(0x8000, regs[0]);
setprg8(0xA000, regs[2]);
setprg8(0xC000, regs[4]);
setprg8(0xE000, ~0);
setchr4(0x0000, regs[6]);
setchr4(0x1000, regs[7]);
}
static void Sync(void) {
setprg8(0x6000, reg);
setprg8(0x8000, ~3);
setprg8(0xa000, ~2);
setprg8r(0x10, 0xc000, 0);
setprg8(0xe000, ~0);
setchr8(0);
}
static void Sync(void) {
setprg8(0x8000, prg_reg[0]);
setprg8(0xA000, prg_reg[1]);
int i;
for (i = 0; i < 8; i++)
setchr1(i << 10, chr_reg[i]);
setmirror(mirr ^ 1);
}
static void Sync(void) {
setprg8(0x6000, reg[4]);
setprg8(0x8000, reg[1]);
setprg8(0xA000, reg[2]);
setprg8(0xC000, reg[3]);
setprg8(0xE000, ~0);
setchr8(0);
}
static void Sync(void) {
setprg8(0x8000, preg[0]);
setprg8(0xA000, preg[1]);
setprg8(0xC000, preg[2]);
setprg8(0xE000, ~0);
setchr4(0x0000, creg[0] | ((mode & 2) << 3));
setchr4(0x1000, creg[1] | ((mode & 4) << 2));
setmirror((mode & 1) ^ 1);
}
static void SyncLH10(void) {
setprg8(0x6000, ~1);
setprg8(0x8000, reg[6]);
setprg8(0xA000, reg[7]);
setprg8r(0x10, 0xC000, 0);
setprg8(0xE000, ~0);
setchr8(0);
setmirror(0);
}
static void Sync(void)
{
int x;
setprg8(0x8000, PRGBanks[0]);
setprg8(0xa000, PRGBanks[1]);
for(x = 0; x < 8; x++)
setchr1(x * 1024, CHRBanks[x]);
}
static void Sync(void) {
int i;
setprg8(0x8000, reg[0]);
setprg8(0xA000, reg[1]);
setprg8(0xC000, reg[2]);
for (i = 0; i < 8; i++)
setchr1(i << 10, chr[i]);
setmirror(reg[3] ^ 1);
}
static void Sync(void)
{
setprg8r(0x10,0x6000,0);
setprg8(0x8000,prg[0]);
setprg8(0xA000,prg[1]);
setprg8(0xC000,prg[2]);
setprg8(0xE000,prg[3]);
setchr8(chr);
}
static void Sync(void)
{
setprg4(0x5000,16);
setprg8(0x6000,2);
setprg8(0x8000,1);
setprg8(0xa000,0);
setprg8(0xc000,reg);
setprg8(0xe000,9);
setchr8(0);
}
static void Sync(void) {
setprg8(0x8000, prgreg[0]);
setprg8(0xa000, prgreg[1]);
setprg8(0xc000, prgreg[2]);
setprg8(0xe000, prgreg[3]);
int i;
for (i = 0; i < 8; i++)
setchr1(i << 10, chrreg[i]);
setmirror(mirror ^ 1);
}
static void Sync(void) {
setmirror(mirror ^ 1);
setprg8(0x8000, reg[3]);
setprg8(0xA000, 0xD);
setprg8(0xC000, 0xE);
setprg8(0xE000, 0xF);
setchr4(0x0000, reg[0] >> 2);
setchr2(0x1000, reg[1] >> 1);
setchr2(0x1800, reg[2] >> 1);
}
static void DEIPower(void)
{
setprg8(0xc000,0xE);
setprg8(0xe000,0xF);
cmd=0;
memset(DRegs,0,8);
Sync();
SetReadHandler(0x8000,0xFFFF,CartBR);
SetWriteHandler(0x8000,0xFFFF,DEIWrite);
}
static DECLFW(M121Write)
{
// FCEU_printf("write: %04x:%04x\n",A&0xE003,V);
if((A&0xF003)==0x8003)
{
// FCEU_printf(" prot write");
// FCEU_printf("write: %04x:%04x\n",A,V);
if (V==0xAB) setprg8(0xE000,7);
else if(V==0x26) setprg8(0xE000,8);
// else if(V==0x26) setprg8(0xE000,1); // MK3
// else if(V==0x26) setprg8(0xE000,0x15); // sonic 3D blast, 8003 - command (0x26), 8001 - data 0x2A (<<1 = 0x15)
else if(V==0xFF) setprg8(0xE000,9);
else if(V==0x28) setprg8(0xC000,0xC);
else if(V==0xEC) setprg8(0xE000,0xD);
// else if(V==0xEC) setprg8(0xE000,0xC);//MK3
else if(V==0xEF) setprg8(0xE000,0xD); // damn mess, need real hardware to figure out bankswitching
else if(V==0x2A) setprg8(0xA000,0x0E);
// else if(V==0x2A) setprg8(0xE000,0x0C); // MK3
else if(V==0x20) setprg8(0xE000,0x13);
else if(V==0x29) setprg8(0xE000,0x1B);
else
{
// FCEU_printf(" unknown");
FixMMC3PRG(MMC3_cmd);
MMC3_CMDWrite(A,V);
}
// FCEU_printf("\n");
}
else
{
// FixMMC3PRG(MMC3_cmd);
MMC3_CMDWrite(A,V);
}
}
static void Sync(void) {
setprg8(0x8000, reg_prg[0]);
setprg8(0xa000, reg_prg[1]);
setprg8(0xc000, reg_prg[2]);
setprg8(0xe000, reg_prg[3]);
setchr2(0x0000, reg_chr[0]);
setchr2(0x0800, reg_chr[1]);
setchr2(0x1000, reg_chr[2]);
setchr2(0x1800, reg_chr[3]);
setmirror(MI_V);
}
static void Sync(void)
{
setprg8(0x8000,pregs[0]);
setprg8(0xa000,pregs[1]);
setprg8(0xc000,~1);
setprg8(0xe000,~0);
setchr2(0x0000,cregs[0]);
setchr2(0x0800,cregs[1]);
setchr2(0x1000,cregs[2]);
setchr2(0x1800,cregs[3]);
}
static void Sync(void) {
setprg2r(0x10, 0x6800, 0);
setprg8(0x8000, regs[0]);
setprg8(0xA000, regs[1]);
setprg8(0xC000, regs[2]);
setprg8(0xE000, regs[3]);
setchr2(0x0000, regs[4]);
setchr2(0x0800, regs[5]);
setchr2(0x1000, regs[6]);
setchr2(0x1800, regs[7]);
}
static void SyncKS7037(void) {
setprg4r(0x10, 0x6000, 0);
setprg4(0x7000, 15);
setprg8(0x8000, reg[6]);
setprg4(0xA000, ~3);
setprg4r(0x10, 0xB000, 1);
setprg8(0xC000, reg[7]);
setprg8(0xE000, ~0);
setchr8(0);
setmirrorw(reg[2] & 1, reg[4] & 1, reg[3] & 1, reg[5] & 1);
}
static void Sync(void)
{
int x;
setchr2(0x0000,DRegs[0]);
setchr2(0x0800,DRegs[1]);
for(x=0;x<4;x++)
setchr1(0x1000+(x<<10),DRegs[2+x]);
setprg8(0x8000,DRegs[6]);
setprg8(0xa000,DRegs[7]);
}
static void Sync(void)
{
setchr8(reg);
if(!delay)
{
setprg16(0x8000,reg);
setprg8(0xC000,reg << 1);
}
setprg8(0xE000,(reg << 1) + 1);
setmirror(((mirr&4)>>2)^1);
}
static void SyncPRGCHR(void)
{
setprg8(0x8000, Regs[0]);
setprg8(0xa000, Regs[1]);
setchr2(0x0000, Regs[2] >> 1);
setchr2(0x0800, Regs[3] >> 1);
setchr1(0x1000, Regs[4]);
setchr1(0x1400, Regs[5]);
setchr1(0x1800, Regs[6]);
setchr1(0x1C00, Regs[7]);
}
static void Sync(void) {
uint16 swap = ((mirr & 2) << 13);
setmirror((mirr & 1) ^ 1);
setprg8r(0x10, 0x6000, 0);
setprg8(0x8000 ^ swap, preg[0]);
setprg8(0xA000, preg[1]);
setprg8(0xC000 ^ swap, ~1);
setprg8(0xE000, ~0);
uint8 i;
for (i = 0; i < 8; i++)
setchr1(i << 10, creg[i]);
}
static void DBPower(CartInfo *info)
{
lastmc = -1;
memset(DRegs,0x3F,8);
DRegs[0]=DRegs[1]=0x1F;
DBSync();
setprg8(0xc000,0x3E);
setprg8(0xe000,0x3F);
}
static void Sync(void) {
setprg4(0x5000, 8 << 1); // Only YS-612 advanced version
setprg8(0x6000, swap?0:2);
setprg8(0x8000, 1);
setprg8(0xa000, 0);
setprg8(0xc000, reg);
setprg8(0xe000, swap?8:9); // hard dump for mr.Mary is 128K,
// bank 9 is the last 2K ok bank 8 repeated 4 times, then till the end of 128K
// instead used bank A, containing some CHR data, ines rom have unused banks removed,
// and bank A moved to the bank 9 place for compatibility with other crappy dumps
setchr8(0);
}
static void Sync(void)
{
setmirror(mirror^1);
setprg8(0x8000,reg[0]);
setprg8(0xA000,reg[1]);
setchr2(0x0000,(reg[2]>>1));
setchr2(0x0800,(reg[3]>>1));
setchr1(0x1000,((bank&0x10)<<4)|reg[4]);
setchr1(0x1400,((bank&0x20)<<3)|reg[5]);
setchr1(0x1800,((bank&0x40)<<2)|reg[6]);
setchr1(0x1C00,((bank&0x80)<<1)|reg[7]);
}