void __init orion5x_setup_cpu_mbus_bridge(void) { int i; int cs; /* * First, disable and clear windows. */ for (i = 0; i < 8; i++) { writel(0, CPU_WIN_BASE(i)); writel(0, CPU_WIN_CTRL(i)); if (orion5x_cpu_win_can_remap(i)) { writel(0, CPU_WIN_REMAP_LO(i)); writel(0, CPU_WIN_REMAP_HI(i)); } } /* * Setup windows for PCI+PCIe IO+MEM space. */ setup_cpu_win(0, ORION5X_PCIE_IO_PHYS_BASE, ORION5X_PCIE_IO_SIZE, TARGET_PCIE, ATTR_PCIE_IO, ORION5X_PCIE_IO_BUS_BASE); setup_cpu_win(1, ORION5X_PCI_IO_PHYS_BASE, ORION5X_PCI_IO_SIZE, TARGET_PCI, ATTR_PCI_IO, ORION5X_PCI_IO_BUS_BASE); setup_cpu_win(2, ORION5X_PCIE_MEM_PHYS_BASE, ORION5X_PCIE_MEM_SIZE, TARGET_PCIE, ATTR_PCIE_MEM, -1); setup_cpu_win(3, ORION5X_PCI_MEM_PHYS_BASE, ORION5X_PCI_MEM_SIZE, TARGET_PCI, ATTR_PCI_MEM, -1); win_alloc_count = 4; /* * Setup MBUS dram target info. */ orion5x_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; for (i = 0, cs = 0; i < 4; i++) { u32 base = readl(DDR_BASE_CS(i)); u32 size = readl(DDR_SIZE_CS(i)); /* * Chip select enabled? */ if (size & 1) { struct mbus_dram_window *w; w = &orion5x_mbus_dram_info.cs[cs++]; w->cs_index = i; w->mbus_attr = 0xf & ~(1 << i); w->base = base & 0xffff0000; w->size = (size | 0x0000ffff) + 1; } } orion5x_mbus_dram_info.num_cs = cs; }
void __init kirkwood_setup_cpu_mbus(void) { void __iomem *addr; int i; int cs; for (i = 0; i < 8; i++) { addr = (void __iomem *)WIN_OFF(i); writel(0, addr + WIN_BASE_OFF); writel(0, addr + WIN_CTRL_OFF); if (cpu_win_can_remap(i)) { writel(0, addr + WIN_REMAP_LO_OFF); writel(0, addr + WIN_REMAP_HI_OFF); } } setup_cpu_win(0, KIRKWOOD_PCIE_IO_PHYS_BASE, KIRKWOOD_PCIE_IO_SIZE, TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE); setup_cpu_win(1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE, TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE); setup_cpu_win(2, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE, TARGET_DEV_BUS, ATTR_DEV_NAND, -1); setup_cpu_win(3, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE, TARGET_SRAM, ATTR_SRAM, -1); kirkwood_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; addr = (void __iomem *)DDR_WINDOW_CPU_BASE; for (i = 0, cs = 0; i < 4; i++) { u32 base = readl(addr + DDR_BASE_CS_OFF(i)); u32 size = readl(addr + DDR_SIZE_CS_OFF(i)); if (size & 1) { struct mbus_dram_window *w; w = &kirkwood_mbus_dram_info.cs[cs++]; w->cs_index = i; w->mbus_attr = 0xf & ~(1 << i); w->base = base & 0xffff0000; w->size = (size | 0x0000ffff) + 1; } } kirkwood_mbus_dram_info.num_cs = cs; }
void __init loki_setup_cpu_mbus(void) { int i; int cs; /* * First, disable and clear windows. */ for (i = 0; i < 8; i++) { writel(0, CPU_WIN_BASE(i)); writel(0, CPU_WIN_CTRL(i)); if (i < 2) { writel(0, CPU_WIN_REMAP_LO(i)); writel(0, CPU_WIN_REMAP_HI(i)); } } /* * Setup windows for PCIe IO+MEM space. */ setup_cpu_win(2, LOKI_PCIE0_MEM_PHYS_BASE, LOKI_PCIE0_MEM_SIZE, TARGET_PCIE0, ATTR_PCIE_MEM, -1); setup_cpu_win(3, LOKI_PCIE1_MEM_PHYS_BASE, LOKI_PCIE1_MEM_SIZE, TARGET_PCIE1, ATTR_PCIE_MEM, -1); /* * Setup MBUS dram target info. */ loki_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; for (i = 0, cs = 0; i < 4; i++) { u32 base = readl(DDR_BASE_CS(i)); u32 size = readl(DDR_SIZE_CS(i)); /* * Chip select enabled? */ if (size & 1) { struct mbus_dram_window *w; w = &loki_mbus_dram_info.cs[cs++]; w->cs_index = i; w->mbus_attr = 0xf & ~(1 << i); w->base = base & 0xffff0000; w->size = (size | 0x0000ffff) + 1; } } loki_mbus_dram_info.num_cs = cs; }
void __init loki_setup_dev_boot_win(u32 base, u32 size) { setup_cpu_win(4, base, size, TARGET_DEV_BUS, ATTR_DEV_BOOT, -1); }
int __init orion5x_setup_sram_win(void) { return setup_cpu_win(win_alloc_count++, ORION5X_SRAM_PHYS_BASE, ORION5X_SRAM_SIZE, TARGET_SRAM, ATTR_SRAM, -1); }
void __init orion5x_setup_pcie_wa_win(u32 base, u32 size) { setup_cpu_win(win_alloc_count++, base, size, TARGET_PCIE, ATTR_PCIE_WA, -1); }
void __init orion5x_setup_dev2_win(u32 base, u32 size) { setup_cpu_win(win_alloc_count++, base, size, TARGET_DEV_BUS, ATTR_DEV_CS2, -1); }
void __init mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size, int maj, int min) { setup_cpu_win(window, base, size, TARGET_PCIE(maj), ATTR_PCIE_MEM(min), -1); }