static void vx900_lpc_interrupt_stuff(device_t dev) { /* Enable setting trigger mode through 0x4d0, and 0x4d1 ports * And enable I/O recovery time */ pci_mod_config8(dev, 0x40, 0, (1 << 2) | (1 << 6)); /* Set serial IRQ frame width to 6 PCI cycles (recommended by VIA) * And enable serial IRQ */ pci_mod_config8(dev, 0x52, 3 << 0, (1 << 3) | (1 << 0)); /* Disable IRQ12 storm FIXME: bad comment */ pci_mod_config8(dev, 0x51, (1 << 2), 0); pci_write_config8(dev, 0x4c, (1 << 6)); /* FIXME: Do we really need this? SeaBIOS/linux runs fine without it. * Is this something the payload/OS should do, or is it safe for us to * do it? */ /* Get the IRQs up and running */ setup_i8259(); vx900_lpc_dma_setup(dev); /* The IOAPIC is special, and we treat it separately */ vx900_lpc_ioapic_setup(dev); }
static void lpc_init(struct device *dev) { printk(BIOS_DEBUG, "pch: lpc_init\n"); /* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, 0x000f); /* IO APIC initialization. */ pch_enable_ioapic(dev); pch_enable_serial_irqs(dev); /* Setup the PIRQ. */ pch_pirq_init(dev); /* Setup power options. */ pch_power_options(dev); /* Initialize power management */ switch (pch_silicon_type()) { case PCH_TYPE_CPT: /* CougarPoint */ cpt_pm_init(dev); break; case PCH_TYPE_PPT: /* PantherPoint */ ppt_pm_init(dev); break; default: printk(BIOS_ERR, "Unknown Chipset: 0x%04x\n", dev->device); } /* Set the state of the GPIO lines. */ //gpio_init(dev); /* Initialize the real time clock. */ pch_rtc_init(dev); /* Initialize ISA DMA. */ isa_dma_init(); /* Initialize the High Precision Event Timers, if present. */ enable_hpet(); /* Initialize Clock Gating */ enable_clock_gating(dev); setup_i8259(); /* The OS should do this? */ /* Interrupt 9 should be level triggered (SCI) */ i8259_configure_irq_trigger(9, 1); pch_disable_smm_only_flashing(dev); #if CONFIG_HAVE_SMI_HANDLER pch_lock_smm(dev); #endif pch_fixups(dev); }
static void p160x_pic_setup(void) { pic_init(); /* I really wonder if this shouldn't be prepivr instead */ isa_pic = setup_i8259(); oea_install_extint(pic_ext_intr); }
static void lpc_init(device_t dev) { u8 byte; u32 dword; device_t sm_dev; /* Enable the LPC Controller */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); dword = pci_read_config32(sm_dev, 0x64); dword |= 1 << 20; pci_write_config32(sm_dev, 0x64, dword); /* Initialize isa dma */ isa_dma_init(); /* Enable DMA transaction on the LPC bus */ byte = pci_read_config8(dev, 0x40); byte |= (1 << 2); pci_write_config8(dev, 0x40, byte); /* Disable the timeout mechanism on LPC */ byte = pci_read_config8(dev, 0x48); byte &= ~(1 << 7); pci_write_config8(dev, 0x48, byte); /* Disable LPC MSI Capability */ byte = pci_read_config8(dev, 0x78); byte &= ~(1 << 1); byte &= ~(1 << 0); /* Keep the old way. i.e., when bus master/DMA cycle is going on on LPC, it holds PCI grant, so no LPC slave cycle can interrupt and visit LPC. */ pci_write_config8(dev, 0x78, byte); /* bit0: Enable prefetch a cacheline (64 bytes) when Host reads code from SPI ROM */ /* bit3: Fix SPI_CS# timing issue when running at 66M. TODO:A12. */ byte = pci_read_config8(dev, 0xBB); byte |= 1 << 0 | 1 << 3; pci_write_config8(dev, 0xBB, byte); cmos_check_update_date(); /* Initialize the real time clock. * The 0 argument tells cmos_init not to * update CMOS unless it is invalid. * 1 tells cmos_init to always initialize the CMOS. */ cmos_init(0); /* Initialize i8259 pic */ setup_i8259 (); /* Initialize i8254 timers */ setup_i8254 (); }
static void lpc_init(struct device *dev) { printk(BIOS_DEBUG, "i82801gx: lpc_init\n"); /* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, 0x000f); /* IO APIC initialization. */ i82801gx_enable_ioapic(dev); i82801gx_enable_serial_irqs(dev); /* Setup the PIRQ. */ i82801gx_pirq_init(dev); /* Setup power options. */ i82801gx_power_options(dev); /* Configure Cx state registers */ i82801gx_configure_cstates(dev); /* Set the state of the GPIO lines. */ //gpio_init(dev); /* Initialize the real time clock. */ i82801gx_rtc_init(dev); /* Initialize ISA DMA. */ isa_dma_init(); /* Initialize the High Precision Event Timers, if present. */ enable_hpet(); /* Initialize Clock Gating */ enable_clock_gating(); setup_i8259(); /* The OS should do this? */ /* Interrupt 9 should be level triggered (SCI) */ i8259_configure_irq_trigger(9, 1); #if CONFIG_HAVE_SMI_HANDLER i82801gx_lock_smm(dev); #endif i82801gx_spi_init(); i82801gx_fixups(dev); }
static void lpc_init(device_t dev) { printk(BIOS_DEBUG, "SB700 - Late.c - lpc_init - Start.\n"); rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY); /* Initialize the real time clock. * The 0 argument tells rtc_init not to * update CMOS unless it is invalid. * 1 tells rtc_init to always initialize the CMOS. */ rtc_init(0); setup_i8259(); /* Initialize i8259 pic */ setup_i8254(); /* Initialize i8254 timers */ printk(BIOS_DEBUG, "SB700 - Late.c - lpc_init - End.\n"); }
static void vt8235_enable(struct device *dev) { u8 regval; u16 vendor,model; vendor = pci_read_config16(dev,0); model = pci_read_config16(dev,0x2); printk(BIOS_DEBUG, "In vt8235_enable %04x %04x.\n",vendor,model); /* If this is not the southbridge itself just return. * This is necessary because USB devices are slot 10, whereas this * device is slot 11 therefore usb devices get called first during * the bus scan. We don't want to wait until we could do dev->init * because that's too late. */ if( (vendor != PCI_VENDOR_ID_VIA) || (model != PCI_DEVICE_ID_VIA_8235)) return; printk(BIOS_DEBUG, "Initialising Devices\n"); /* make sure interupt controller is configured before keyboard init */ setup_i8259(); /* enable RTC and ethernet */ regval = pci_read_config8(dev, 0x51); regval |= 0x18; pci_write_config8(dev, 0x51, regval); /* turn on keyboard */ keyboard_on(dev); /* enable USB 1.1 & USB 2.0 - redundant really since we've * already been there - see note above */ regval = pci_read_config8(dev, 0x50); regval &= ~(0x36); pci_write_config8(dev, 0x50, regval); }
static void southbridge_init(struct device *dev) { printk(BIOS_DEBUG, "vx800 sb init\n"); vx800_sb_init(dev); pci_routing_fixup(dev); setup_i8259(); // make sure interupt controller is configured before keyboard init /* turn on keyboard and RTC, no need to visit this reg twice */ pc_keyboard_init(); printk(BIOS_DEBUG, "ps2 usb lid, you set who can wakeup system from s3 sleep\n"); S3_ps2_kb_ms_wakeup(dev); S3_usb_wakeup(dev); S3_lid_wakeup(dev); /* enable acpi cpu c3 state. (c2 state need not do anything.) #1 fadt->pm2_cnt_blk = 0x22;//to support cpu-c3 fadt->p_lvl2_lat = 0x50; //this is the coreboot source fadt->p_lvl3_lat = 0x320;// fadt->pm2_cnt_len = 1;//to support cpu-c3 #2 ssdt? ->every cpu has a P_BLK address. set it to 0x10 (so that "Read Processor Level3 register(PMIORx15<7:0>) to enter C3 state"---VIA vx800 P SPEC ) #3 write 0x17 in to PMIO=VX800_ACPI_IO_BASE + 0x26, following the describtion in the P-spec. 1 enable SLP# asserts in C3 state PMIORx26<1> =1 2 enable CPUSTP# asserts in C3 state; PMIORx26<2> =1 3 CLKRUN# is always asserted PMIORx26<3> =0 4 Disable PCISTP# When CLKRUN# is asserted 1: PCISTP# will not assert When CLKRUN# is asserted PMIORx26<4> =1 5 This bit controls whether the CPU voltage is lowered when in C3/S1 state. VRDSLP will be active in either this bit set in C3 or LVL4 register read PMIORx26<0> =0 6 Read Processor Level3 register(PMIORx15<7:0>) to enter C3 state PMIORx15 */ outb(0x17, VX800_ACPI_IO_BASE + 0x26); }
static void r8610_init(struct device *dev) { device_t nb_dev; u32 tmp; printk(BIOS_DEBUG, "r8610 init\n"); /* clear DMA? */ outb(0x4, 0x8); outb(0x4, 0x10); outb(0xfc, 0x61); /* Set serial base */ pci_write_config32(dev, 0x54, 0x3f8); /* serial IRQ disable, LPC disable, COM2 goes to LPC, internal UART for COM1 */ pci_write_config32(dev, 0x50, 0x84101012); /* Enable internal Port92, enable chipselect for flash */ tmp = pci_read_config32(dev, 0x40); pci_write_config32(dev, 0x40, tmp | 0x07FF0600); /* buffer strength SB pins */ pci_write_config32(dev, 0x5c, 0x2315); /* EHCI 14, OHCI 15, MAC1 disable, MAC0 10, INTD 9, INTC 9, INTB 12, INTA INT10 */ pci_write_config32(dev, 0x58, 0xdf0311b3); /* USB PHY control */ nb_dev = dev_find_device(PCI_VENDOR_ID_RDC, PCI_DEVICE_ID_RDC_R8610_NB, 0); tmp = pci_read_config32(nb_dev, 0xc0); tmp |= 0x40000; pci_write_config32(nb_dev, 0xc0, tmp); setup_i8259(); }
void lpc_soc_init(struct device *dev) { /* Legacy initialization */ isa_dma_init(); pch_misc_init(); /* Enable CLKRUN_EN for power gating LPC */ lpc_enable_pci_clk_cntl(); /* Set LPC Serial IRQ mode */ if (IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)) lpc_set_serirq_mode(SERIRQ_CONTINUOUS); else lpc_set_serirq_mode(SERIRQ_QUIET); /* Interrupt configuration */ pch_enable_ioapic(dev); soc_pch_pirq_init(dev); setup_i8259(); i8259_configure_irq_trigger(9, 1); clock_gate_8254(dev); soc_mirror_dmi_pcr_io_dec(); }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; u8 reg8; // all cores: allow caching of flash chip code and data // (there are no cache-as-ram reliability concerns with family 14h) __writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5); __writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800); // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time __writemsr (0xc0010062, 0); if (boot_cpu()) { u8 reg8; // SB800: program AcpiMmioEn to enable MMIO access to MiscCntrl register outb(0x24, 0xCD6); reg8 = inb(0xCD7); reg8 |= 1; reg8 &= ~(1 << 1); outb(reg8, 0xCD7); // program SB800 MiscCntrl *(volatile u32 *)(0xFED80000+0xE00+0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */ *(volatile u32 *)(0xFED80000+0xE00+0x40) |= 1 << 1; /* 48Mhz */ } // early enable of PrefetchEnSPIFromHost if (boot_cpu()) { __outdword (0xcf8, 0x8000a3b8); __outdword (0xcfc, __indword (0xcfc) | 1 << 24); } // early enable of SPI 33 MHz fast mode read if (boot_cpu()) { volatile u32 *spiBase = (void *) 0xa0000000; u32 save; __outdword (0xcf8, 0x8000a3a0); save = __indword (0xcfc); __outdword (0xcfc, (u32) spiBase | 2); // set temp MMIO base spiBase [3] = (spiBase [3] & ~(3 << 14)) | (1 << 14); spiBase [0] |= 1 << 18; // fast read enable __outdword (0xcfc, save); // clear temp base } if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_poweron_init(); post_code(0x31); f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); } /* Halt if there was a built in self test failure */ post_code(0x34); report_bist_failure(bist); // Load MPB val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); post_code(0x35); val = agesawrapper_amdinitmmio(); post_code(0x37); val = agesawrapper_amdinitreset(); if(val) { printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val); } post_code(0x38); printk(BIOS_DEBUG, "Got past sb800_early_setup\n"); post_code(0x39); val = agesawrapper_amdinitearly (); if(val) { printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val); } printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n"); post_code(0x40); val = agesawrapper_amdinitpost (); if(val) { printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val); } printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n"); post_code(0x41); val = agesawrapper_amdinitenv (); if(val) { printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val); } printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n"); /* Initialize i8259 pic */ post_code(0x41); setup_i8259 (); /* Initialize i8254 timers */ post_code(0x42); setup_i8254 (); post_code(0x50); copy_and_run(0); post_code(0x54); // Should never see this post code. }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; #if CONFIG_HAVE_ACPI_RESUME void *resume_backup_memory; #endif /* * All cores: allow caching of flash chip code and data * (there are no cache-as-ram reliability concerns with family 14h) */ __writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5); __writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800); /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr (0xc0010062, 0); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_Poweron_Init(); post_code(0x31); smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); } /* Halt if there was a built in self test failure */ post_code(0x34); report_bist_failure(bist); /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); post_code(0x35); printk(BIOS_DEBUG, "agesawrapper_amdinitmmio "); val = agesawrapper_amdinitmmio(); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); post_code(0x37); printk(BIOS_DEBUG, "agesawrapper_amdinitreset "); val = agesawrapper_amdinitreset(); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); post_code(0x39); printk(BIOS_DEBUG, "agesawrapper_amdinitearly "); val = agesawrapper_amdinitearly (); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); #if CONFIG_HAVE_ACPI_RESUME if (!acpi_is_wakeup_early()) { /* Check for S3 resume */ #endif post_code(0x40); printk(BIOS_DEBUG, "agesawrapper_amdinitpost "); val = agesawrapper_amdinitpost (); /* Reboots with outb(3,0x92), outb(4,0xcf9) or triple-fault all * hang, looks like DRAM re-init goes wrong, don't know why. */ if (val == 7) /* fatal, amdinitenv below is going to hang */ outb(0x06, 0x0cf9); /* reset system harder instead */ if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); post_code(0x42); printk(BIOS_DEBUG, "agesawrapper_amdinitenv "); val = agesawrapper_amdinitenv (); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); #if CONFIG_HAVE_ACPI_RESUME } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); printk(BIOS_DEBUG, "agesawrapper_amdinitresume "); val = agesawrapper_amdinitresume(); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); printk(BIOS_DEBUG, "agesawrapper_amds3laterestore "); val = agesawrapper_amds3laterestore (); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); post_code(0x61); printk(BIOS_DEBUG, "Find resume memory location\n"); resume_backup_memory = backup_resume(); post_code(0x62); printk(BIOS_DEBUG, "Move CAR stack.\n"); move_stack_high_mem(); printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE)); post_code(0x63); disable_cache_as_ram(); printk(BIOS_DEBUG, "CAR disabled.\n"); set_resume_cache(); /* * Copy the system memory that is in the ramstage area to the * reserved area. */ if (resume_backup_memory) memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE); printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n"); } #endif /* Initialize i8259 pic */ post_code(0x43); setup_i8259 (); /* Initialize i8254 timers */ post_code(0x44); setup_i8254 (); post_code(0x50); copy_and_run(0); printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); post_code(0x54); /* Should never see this post code. */ }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sch4037_early_init (CONFIG_SIO_PORT); /* Detect SMSC SIO1036 LPC Debug Card status */ if (detect_sio1036_chip(0x4E)) { /* Found SMSC SIO1036 LPC Debug Card */ sio1036_early_init(0x4E); } post_code(0x31); uart_init(); console_init(); /* * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR, * Disable all Pcie Bridges to work around It. */ sr56x0_rd890_disable_pcie_bridge(); } post_code(0x32); val = agesawrapper_amdinitmmio(); if (val) { printk(BIOS_DEBUG, "agesawrapper_amdinitmmio failed: %x \n", val); } else { printk(BIOS_DEBUG, "agesawrapper_amdinitmmio passed\n"); } /* Halt if there was a built in self test failure */ post_code(0x33); report_bist_failure(bist); // Load MPB val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); if(boot_cpu()) { post_code(0x34); sb_Poweron_Init(); } post_code(0x35); val = agesawrapper_amdinitreset(); if (val) { printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val); } else { printk(BIOS_DEBUG, "agesawrapper_amdinitreset passed\n"); } post_code(0x36); val = agesawrapper_amdinitearly (); if (val) { printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val); } else { printk(BIOS_DEBUG, "agesawrapper_amdinitearly passed\n"); } post_code(0x37); nb_Poweron_Init(); post_code(0x38); nb_Ht_Init(); post_code(0x39); val = agesawrapper_amdinitpost (); if (val) { printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val); } else { printk(BIOS_DEBUG, "agesawrapper_amdinitpost passed\n"); } post_code(0x40); val = agesawrapper_amdinitenv (); if (val) { printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val); } else { printk(BIOS_DEBUG, "agesawrapper_amdinitenv passed\n"); } /* Initialize i8259 pic */ post_code(0x41); setup_i8259 (); /* Initialize i8254 timers */ post_code(0x42); setup_i8254 (); post_code(0x43); print_debug("Disabling cache as ram "); disable_cache_as_ram(); print_debug("done\n"); post_code(0x44); copy_and_run(0); post_code(0x45); // Should never see this post code. }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_Poweron_Init(); post_code(0x31); kbc1100_early_init(CONFIG_SIO_PORT); console_init(); } /* Halt if there was a built in self test failure */ post_code(0x34); report_bist_failure(bist); // Load MPB val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); post_code(0x35); val = agesawrapper_amdinitmmio(); post_code(0x37); val = agesawrapper_amdinitreset(); if(val) { printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val); } post_code(0x38); printk(BIOS_DEBUG, "Got past sb800_early_setup\n"); post_code(0x39); val = agesawrapper_amdinitearly (); if(val) { printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val); } printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n"); post_code(0x40); val = agesawrapper_amdinitpost (); if(val) { printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val); } printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n"); post_code(0x41); val = agesawrapper_amdinitenv (); if(val) { printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val); } printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n"); /* Initialize i8259 pic */ post_code(0x41); setup_i8259 (); /* Initialize i8254 timers */ post_code(0x42); setup_i8254 (); post_code(0x50); copy_and_run(0); post_code(0x54); // Should never see this post code. }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; post_code(0x35); printk(BIOS_DEBUG, "agesawrapper_amdinitmmio "); val = agesawrapper_amdinitmmio(); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); gpioEarlyInit(); sb_poweron_init(); post_code(0x31); kbc1100_early_init(CONFIG_SIO_PORT); post_code(0x32); uart_init(); post_code(0x33); console_init(); } /* Halt if there was a built in self test failure */ post_code(0x34); report_bist_failure(bist); // Load MPB val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); post_code(0x36); printk(BIOS_DEBUG, "agesawrapper_amdinitreset "); val = agesawrapper_amdinitreset(); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); post_code(0x37); printk(BIOS_DEBUG, "agesawrapper_amdinitearly "); val = agesawrapper_amdinitearly(); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); post_code(0x38); printk(BIOS_DEBUG, "agesawrapper_amdinitpost "); val = agesawrapper_amdinitpost(); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); post_code(0x39); printk(BIOS_DEBUG, "sb_before_pci_init "); sb_before_pci_init(); printk(BIOS_DEBUG, "passed.\n"); post_code(0x40); printk(BIOS_DEBUG, "agesawrapper_amdinitenv "); val = agesawrapper_amdinitenv(); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); /* Initialize i8259 pic */ post_code(0x41); printk(BIOS_DEBUG, "setup_i8259\n"); setup_i8259(); /* Initialize i8254 timers */ post_code(0x42); printk(BIOS_DEBUG, "setup_i8254\n"); setup_i8254(); post_code(0x43); copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run returned!\n"); post_code(0x44); // Should never see this post code. }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; post_code(0x30); agesawrapper_amdinitmmio(); post_code(0x31); /* Halt if there was a built in self test failure */ post_code(0x33); report_bist_failure(bist); sb7xx_51xx_enable_wideio(0, 0x1600); /* though UARTs are on the NUVOTON BMC */ w83627dhg_set_clksel_48(DUMMY_DEV); w83627dhg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); sb7xx_51xx_disable_wideio(0); post_code(0x34); uart_init(); post_code(0x35); console_init(); val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); post_code(0x37); val = agesawrapper_amdinitreset(); if (val) { printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val); } else { printk(BIOS_DEBUG, "agesawrapper_amdinitreset passed\n"); } if (!cpu_init_detectedx && boot_cpu()) { post_code(0x38); /* * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR, * Disable all Pcie Bridges to work around It. */ sr56x0_rd890_disable_pcie_bridge(); post_code(0x39); nb_Poweron_Init(); post_code(0x3A); sb_Poweron_Init(); } post_code(0x3B); val = agesawrapper_amdinitearly(); if(val) { printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val); } else { printk(BIOS_DEBUG, "agesawrapper_amdinitearly passed\n"); } post_code(0x3C); /* W83627DHG pin89,90 function select is RSTOUT3#, RSTOUT2# by default. * In order to access W83795G/ADG HWM using I2C protocol, * we select function to SDA, SCL function (or GP33, GP32 function). */ w83627dhg_enable_i2c(PNP_DEV(0x2E, W83627DHG_SPI)); nb_Ht_Init(); post_code(0x3D); /* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */ if (!warm_reset_detect(0)) { print_info("...WARM RESET...\n\n\n"); distinguish_cpu_resets(0); soft_reset(); die("After soft_reset_x - shouldn't see this message!!!\n"); } post_code(0x40); val = agesawrapper_amdinitpost(); if (val) { printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val); } else { printk(BIOS_DEBUG, "agesawrapper_amdinitpost passed\n"); } post_code(0x41); val = agesawrapper_amdinitenv(); if(val) { printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val); } printk(BIOS_DEBUG, "agesawrapper_amdinitenv passed\n"); post_code(0x42); post_code(0x50); print_debug("Disabling cache as ram "); disable_cache_as_ram(); print_debug("done\n"); post_code(0x51); setup_i8259 (); setup_i8254 (); copy_and_run(); /* We will not return, Should never see this message and post code. */ print_debug("should not be here -\n"); post_code(0x54); }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; post_code(0x30); agesawrapper_amdinitmmio(); post_code(0x31); /* Halt if there was a built in self test failure */ post_code(0x33); report_bist_failure(bist); sb7xx_51xx_enable_wideio(0, 0x1600); /* though UARTs are on the NUVOTON BMC */ wpcm450_enable_dev(WPCM450_SP1, 0x164E, CONFIG_TTYS0_BASE); sb7xx_51xx_disable_wideio(0); post_code(0x34); uart_init(); post_code(0x35); console_init(); val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); post_code(0x37); val = agesawrapper_amdinitreset(); if (val) { printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val); } else { printk(BIOS_DEBUG, "agesawrapper_amdinitreset passed\n"); } if (!cpu_init_detectedx && boot_cpu()) { post_code(0x38); /* * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR, * Disable all Pcie Bridges to work around It. */ sr56x0_rd890_disable_pcie_bridge(); post_code(0x39); nb_Poweron_Init(); post_code(0x3A); sb_Poweron_Init(); } post_code(0x3B); val = agesawrapper_amdinitearly(); if(val) { printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val); } else { printk(BIOS_DEBUG, "agesawrapper_amdinitearly passed\n"); } post_code(0x3C); nb_Ht_Init(); post_code(0x3D); /* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */ if (!warm_reset_detect(0)) { print_info("...WARM RESET...\n\n\n"); distinguish_cpu_resets(0); soft_reset(); die("After soft_reset_x - shouldn't see this message!!!\n"); } post_code(0x40); val = agesawrapper_amdinitpost(); if (val) { printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val); } else { printk(BIOS_DEBUG, "agesawrapper_amdinitpost passed\n"); } post_code(0x41); val = agesawrapper_amdinitenv(); if(val) { printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val); } printk(BIOS_DEBUG, "agesawrapper_amdinitenv passed\n"); post_code(0x42); /* Initialize i8259 pic */ post_code(0x41); setup_i8259 (); /* Initialize i8254 timers */ post_code(0x42); setup_i8254 (); post_code(0x50); print_debug("Disabling cache as ram "); disable_cache_as_ram(); print_debug("done\n"); post_code(0x51); copy_and_run(0); /* We will not return, Should never see this message and post code. */ print_debug("should not be here -\n"); post_code(0x54); }