int __init add_bridge(struct device_node *dev) { int len; struct pci_controller *hose; struct resource rsrc; const int *bus_range; int primary = 1, has_address = 0; phys_addr_t immr = get_immrbase(); DBG("Adding PCI host bridge %s\n", dev->full_name); /* Fetch host bridge registers address */ has_address = (of_address_to_resource(dev, 0, &rsrc) == 0); /* Get bus range if any */ bus_range = get_property(dev, "bus-range", &len); if (bus_range == NULL || len < 2 * sizeof(int)) { printk(KERN_WARNING "Can't get bus-range for %s, assume" " bus 0\n", dev->full_name); } hose = pcibios_alloc_controller(); if (!hose) return -ENOMEM; hose->arch_data = dev; hose->set_cfg_type = 1; hose->first_busno = bus_range ? bus_range[0] : 0; hose->last_busno = bus_range ? bus_range[1] : 0xff; /* MPC83xx supports up to two host controllers one at 0x8500 from immrbar * the other at 0x8600, we consider the 0x8500 the primary controller */ /* PCI 1 */ if ((rsrc.start & 0xfffff) == 0x8500) { setup_indirect_pci(hose, immr + 0x8300, immr + 0x8304); } /* PCI 2 */ if ((rsrc.start & 0xfffff) == 0x8600) { setup_indirect_pci(hose, immr + 0x8380, immr + 0x8384); primary = 0; hose->bus_offset = hose->first_busno; mpc83xx_pci2_busno = hose->first_busno; } printk(KERN_INFO "Found MPC83xx PCI host bridge at 0x%016llx. " "Firmware bus number: %d->%d\n", (unsigned long long)rsrc.start, hose->first_busno, hose->last_busno); DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", hose, hose->cfg_addr, hose->cfg_data); /* Interpret the "ranges" property */ /* This also maps the I/O region and sets isa_io/mem_base */ pci_process_bridge_OF_ranges(hose, dev, primary); return 0; }
void __init pplus_setup_hose(void) { struct pci_controller* hose; hose = pcibios_alloc_controller(); if (!hose) return; hose->first_busno = 0; hose->last_busno = 0xff; hose->pci_mem_offset = PREP_ISA_MEM_BASE; hose->io_base_virt = (void *)PREP_ISA_IO_BASE; pplus_init_resource(&hose->io_resource, 0x00000000, 0x0fffffff, IORESOURCE_IO); pplus_init_resource(&hose->mem_resources[0], 0xc0000000, 0xfdffffff, IORESOURCE_MEM); hose->io_space.start = 0x00000000; hose->io_space.end = 0x0fffffff; hose->mem_space.start = 0x00000000; hose->mem_space.end = 0x3cfbffff; /* MPIC at 0x3cfc0000-0x3dffffff */ setup_indirect_pci(hose, 0x80000cf8, 0x80000cfc); pplus_set_VIA_IDE_legacy(); hose->last_busno = pciauto_bus_scan(hose, hose->first_busno); ppc_md.pcibios_fixup = pplus_pcibios_fixup; ppc_md.pci_swizzle = common_swizzle; pplus_set_board_type(); }
static void __init yosemite_setup_hose(void) { unsigned int bar_response, bar; struct pci_controller *hose; yosemite_setup_pci(); hose = pcibios_alloc_controller(); if (!hose) return; hose->first_busno = 0; hose->last_busno = 0xff; hose->pci_mem_offset = YOSEMITE_PCI_MEM_OFFSET; pci_init_resource(&hose->io_resource, YOSEMITE_PCI_LOWER_IO, YOSEMITE_PCI_UPPER_IO, IORESOURCE_IO, "PCI host bridge"); pci_init_resource(&hose->mem_resources[0], YOSEMITE_PCI_LOWER_MEM, YOSEMITE_PCI_UPPER_MEM, IORESOURCE_MEM, "PCI host bridge"); ppc_md.pci_exclude_device = yosemite_exclude_device; hose->io_space.start = YOSEMITE_PCI_LOWER_IO; hose->io_space.end = YOSEMITE_PCI_UPPER_IO; hose->mem_space.start = YOSEMITE_PCI_LOWER_MEM; hose->mem_space.end = YOSEMITE_PCI_UPPER_MEM; isa_io_base = (unsigned long)ioremap64(YOSEMITE_PCI_IO_BASE, YOSEMITE_PCI_IO_SIZE); hose->io_base_virt = (void *)isa_io_base; setup_indirect_pci(hose, YOSEMITE_PCI_CFGA_PLB32, YOSEMITE_PCI_CFGD_PLB32); hose->set_cfg_type = 1; /* Zero config bars */ for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) { early_write_config_dword(hose, hose->first_busno, PCI_FUNC(hose->first_busno), bar, 0x00000000); early_read_config_dword(hose, hose->first_busno, PCI_FUNC(hose->first_busno), bar, &bar_response); } hose->last_busno = pciauto_bus_scan(hose, hose->first_busno); ppc_md.pci_swizzle = common_swizzle; ppc_md.pci_map_irq = yosemite_map_irq; }
static int __init storcenter_add_bridge(struct device_node *dev) { #ifdef CONFIG_PCI int len; struct pci_controller *hose; const int *bus_range; printk("Adding PCI host bridge %s\n", dev->full_name); hose = pcibios_alloc_controller(dev); if (hose == NULL) return -ENOMEM; bus_range = of_get_property(dev, "bus-range", &len); hose->first_busno = bus_range ? bus_range[0] : 0; hose->last_busno = bus_range ? bus_range[1] : 0xff; setup_indirect_pci(hose, MPC10X_MAPB_CNFG_ADDR, MPC10X_MAPB_CNFG_DATA, 0); /* Interpret the "ranges" property */ /* This also maps the I/O region and sets isa_io/mem_base */ pci_process_bridge_OF_ranges(hose, dev, 1); #endif return 0; }
static int __init linkstation_add_bridge(struct device_node *dev) { #ifdef CONFIG_PCI int len; struct pci_controller *hose; const int *bus_range; printk("Adding PCI host bridge %s\n", dev->full_name); bus_range = of_get_property(dev, "bus-range", &len); if (bus_range == NULL || len < 2 * sizeof(int)) printk(KERN_WARNING "Can't get bus-range for %s, assume" " bus 0\n", dev->full_name); hose = pcibios_alloc_controller(dev); if (hose == NULL) return -ENOMEM; hose->first_busno = bus_range ? bus_range[0] : 0; hose->last_busno = bus_range ? bus_range[1] : 0xff; setup_indirect_pci(hose, 0xfec00000, 0xfee00000, 0); /* Interpret the "ranges" property */ /* This also maps the I/O region and sets isa_io/mem_base */ pci_process_bridge_OF_ranges(hose, dev, 1); #endif return 0; }
static int __init amigaone_add_bridge(struct device_node *dev) { const u32 *cfg_addr, *cfg_data; int len; const int *bus_range; struct pci_controller *hose; printk(KERN_INFO "Adding PCI host bridge %s\n", dev->full_name); cfg_addr = of_get_address(dev, 0, NULL, NULL); cfg_data = of_get_address(dev, 1, NULL, NULL); if ((cfg_addr == NULL) || (cfg_data == NULL)) return -ENODEV; bus_range = of_get_property(dev, "bus-range", &len); if ((bus_range == NULL) || (len < 2 * sizeof(int))) printk(KERN_WARNING "Can't get bus-range for %s, assume" " bus 0\n", dev->full_name); hose = pcibios_alloc_controller(dev); if (hose == NULL) return -ENOMEM; hose->first_busno = bus_range ? bus_range[0] : 0; hose->last_busno = bus_range ? bus_range[1] : 0xff; setup_indirect_pci(hose, cfg_addr[0], cfg_data[0], 0); /* Interpret the "ranges" property */ /* This also maps the I/O region and sets isa_io/mem_base */ pci_process_bridge_OF_ranges(hose, dev, 1); return 0; }
void __init setup_grackle(struct pci_controller *hose) { setup_indirect_pci(hose, 0xfec00000, 0xfee00000); if (machine_is_compatible("AAPL,PowerBook1998")) grackle_set_loop_snoop(hose, 1); #if 0 /* Disabled for now, HW problems ??? */ grackle_set_stg(hose, 1); #endif }
void __init setup_grackle(struct pci_controller *hose) { setup_indirect_pci(hose, 0xfec00000, 0xfee00000, 0); if (of_machine_is_compatible("PowerMac1,1")) pci_add_flags(PCI_REASSIGN_ALL_BUS); if (of_machine_is_compatible("AAPL,PowerBook1998")) grackle_set_loop_snoop(hose, 1); #if 0 /* Disabled for now, HW problems ??? */ grackle_set_stg(hose, 1); #endif }
/* The "bootloader" for Synergy boards does none of this for us, so we need to lay it all out ourselves... --Dan */ void __init gemini_find_bridges(void) { struct pci_controller* hose; ppc_md.pcibios_fixup = gemini_pcibios_fixup; hose = pcibios_alloc_controller(); if (!hose) return; setup_indirect_pci(hose, 0xfec00000, 0xfee00000); }
static void __init p3p440_setup_hose(void) { struct pci_controller *hose; if (!is_monarch()) { /* * REMARK: This Non-Monarch mode need perhaps some changes. * It's not tested at all, because of lack of hardware. --sr */ printk("P3P440-PCI: Non-Monarch detected, skipping PCI init!\n"); return; } /* Configure windows on the PCI-X host bridge */ p3p440_setup_pcix(); hose = pcibios_alloc_controller(); if (!hose) return; hose->first_busno = 0; hose->last_busno = 0xff; hose->pci_mem_offset = P3P440_PCI_MEM_OFFSET; pci_init_resource(&hose->io_resource, P3P440_PCI_LOWER_IO, P3P440_PCI_UPPER_IO, IORESOURCE_IO, "PCI host bridge"); pci_init_resource(&hose->mem_resources[0], P3P440_PCI_LOWER_MEM, P3P440_PCI_UPPER_MEM, IORESOURCE_MEM, "PCI host bridge"); hose->io_space.start = P3P440_PCI_LOWER_IO; hose->io_space.end = P3P440_PCI_UPPER_IO; hose->mem_space.start = P3P440_PCI_LOWER_MEM; hose->mem_space.end = P3P440_PCI_UPPER_MEM; hose->io_base_virt = ioremap64(P3P440_PCI_IO_BASE, P3P440_PCI_IO_SIZE); isa_io_base = (unsigned long)hose->io_base_virt; setup_indirect_pci(hose, PCIX0_CFGA, PCIX0_CFGD); hose->set_cfg_type = 1; hose->last_busno = pciauto_bus_scan(hose, hose->first_busno); ppc_md.pci_swizzle = common_swizzle; ppc_md.pci_map_irq = p3p440_map_irq; }
/** * xilinx_pci_init - Find and register a Xilinx PCI host bridge */ void __init xilinx_pci_init(void) { struct pci_controller *hose; struct resource r; void __iomem *pci_reg; struct device_node *pci_node; pci_node = of_find_matching_node(NULL, xilinx_pci_match); if(!pci_node) return; if (of_address_to_resource(pci_node, 0, &r)) { pr_err("xilinx-pci: cannot resolve base address\n"); return; } hose = pcibios_alloc_controller(pci_node); if (!hose) { pr_err("xilinx-pci: pcibios_alloc_controller() failed\n"); return; } /* Setup config space */ setup_indirect_pci(hose, r.start + XPLB_PCI_ADDR, r.start + XPLB_PCI_DATA, PPC_INDIRECT_TYPE_SET_CFG_TYPE); /* According to the xilinx plbv46_pci documentation the soft-core starts * a self-init when the bus master enable bit is set. Without this bit * set the pci bus can't be scanned. */ early_write_config_word(hose, 0, 0, PCI_COMMAND, PCI_HOST_ENABLE_CMD); /* Set the max latency timer to 255 */ early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0xff); /* Set the max bus number to 255 */ pci_reg = of_iomap(pci_node, 0); out_8(pci_reg + XPLB_PCI_BUS, 0xff); iounmap(pci_reg); /* Nothing past the root bridge is working right now. By default * exclude config access to anything except bus 0 */ if (!ppc_md.pci_exclude_device) ppc_md.pci_exclude_device = xilinx_pci_exclude_device; /* Register the host bridge with the linux kernel! */ pci_process_bridge_OF_ranges(hose, pci_node, 1); pr_info("xilinx-pci: Registered PCI host bridge\n"); }
static void __init ebony_setup_hose(void) { struct pci_controller *hose; /* Configure windows on the PCI-X host bridge */ ebony_setup_pcix(); hose = pcibios_alloc_controller(); if (!hose) return; hose->first_busno = 0; hose->last_busno = 0xff; hose->pci_mem_offset = EBONY_PCI_MEM_OFFSET; pci_init_resource(&hose->io_resource, EBONY_PCI_LOWER_IO, EBONY_PCI_UPPER_IO, IORESOURCE_IO, "PCI host bridge"); pci_init_resource(&hose->mem_resources[0], EBONY_PCI_LOWER_MEM, EBONY_PCI_UPPER_MEM, IORESOURCE_MEM, "PCI host bridge"); hose->io_space.start = EBONY_PCI_LOWER_IO; hose->io_space.end = EBONY_PCI_UPPER_IO; hose->mem_space.start = EBONY_PCI_LOWER_MEM; hose->mem_space.end = EBONY_PCI_UPPER_MEM; isa_io_base = (unsigned long)ioremap64(EBONY_PCI_IO_BASE, EBONY_PCI_IO_SIZE); hose->io_base_virt = (void *)isa_io_base; setup_indirect_pci(hose, EBONY_PCI_CFGA_PLB32, EBONY_PCI_CFGD_PLB32); hose->set_cfg_type = 1; hose->last_busno = pciauto_bus_scan(hose, hose->first_busno); ppc_md.pci_swizzle = common_swizzle; ppc_md.pci_map_irq = ebony_map_irq; }
void __init add_bridge(struct device_node *np) { int len; struct pci_controller *hose; struct resource r; const int *bus_range; const uint *ptr; memset(&r, 0, sizeof(r)); if (of_address_to_resource(np, 0, &r)) { printk(KERN_INFO "No PCI reg property in device tree\n"); return; } if (!(ptr = of_get_property(np, "clock-frequency", NULL))) { printk(KERN_INFO "No clock-frequency property in PCI node"); return; } pci_clk_frq = *ptr; of_node_put(np); bus_range = of_get_property(np, "bus-range", &len); if (bus_range == NULL || len < 2 * sizeof(int)) { printk(KERN_WARNING "Can't get bus-range for %s, assume" " bus 0\n", np->full_name); } pci_assign_all_buses = 1; hose = pcibios_alloc_controller(); if (!hose) return; hose->arch_data = np; hose->set_cfg_type = 1; hose->first_busno = bus_range ? bus_range[0] : 0; hose->last_busno = bus_range ? bus_range[1] : 0xff; hose->bus_offset = 0; hose->set_cfg_type = 1; setup_indirect_pci(hose, r.start + offsetof(pci_cpm2_t, pci_cfg_addr), r.start + offsetof(pci_cpm2_t, pci_cfg_data)); pci_process_bridge_OF_ranges(hose, np, 1); }
static int __init mv64x60_add_bridge(struct device_node *dev) { int len; struct pci_controller *hose; struct resource rsrc; const int *bus_range; int primary; memset(&rsrc, 0, sizeof(rsrc)); /* Fetch host bridge registers address */ if (of_address_to_resource(dev, 0, &rsrc)) { printk(KERN_ERR "No PCI reg property in device tree\n"); return -ENODEV; } /* Get bus range if any */ bus_range = of_get_property(dev, "bus-range", &len); if (bus_range == NULL || len < 2 * sizeof(int)) printk(KERN_WARNING "Can't get bus-range for %s, assume" " bus 0\n", dev->full_name); hose = pcibios_alloc_controller(dev); if (!hose) return -ENOMEM; hose->set_cfg_type = 1; hose->first_busno = bus_range ? bus_range[0] : 0; hose->last_busno = bus_range ? bus_range[1] : 0xff; setup_indirect_pci(hose, rsrc.start, rsrc.start + 4, 0); hose->bus_offset = hose->first_busno; printk(KERN_INFO "Found MV64x60 PCI host bridge at 0x%016llx. " "Firmware bus number: %d->%d\n", (unsigned long long)rsrc.start, hose->first_busno, hose->last_busno); /* Interpret the "ranges" property */ /* This also maps the I/O region and sets isa_io/mem_base */ primary = (hose->first_busno == 0); pci_process_bridge_OF_ranges(hose, dev, primary); return 0; }
static void __init setup_python(struct pci_controller *hose, struct device_node *dev) { u32 __iomem *reg; u32 val; unsigned long addr = dev->addrs[0].address; setup_indirect_pci(hose, addr + 0xf8000, addr + 0xf8010); /* Clear the magic go-slow bit */ reg = ioremap(dev->addrs[0].address + 0xf6000, 0x40); val = in_be32(®[12]); if (val & PRG_CL_RESET_VALID) { out_be32(®[12], val & ~PRG_CL_RESET_VALID); in_be32(®[12]); } iounmap(reg); }
void __init mvme5100_setup_bridge(void) { struct pci_controller* hose; hose = pcibios_alloc_controller(); if (!hose) return; hose->first_busno = 0; hose->last_busno = 0xff; hose->pci_mem_offset = MVME5100_PCI_MEM_OFFSET; pci_init_resource(&hose->io_resource, MVME5100_PCI_LOWER_IO, MVME5100_PCI_UPPER_IO, IORESOURCE_IO, "PCI host bridge"); pci_init_resource(&hose->mem_resources[0], MVME5100_PCI_LOWER_MEM, MVME5100_PCI_UPPER_MEM, IORESOURCE_MEM, "PCI host bridge"); hose->io_space.start = MVME5100_PCI_LOWER_IO; hose->io_space.end = MVME5100_PCI_UPPER_IO; hose->mem_space.start = MVME5100_PCI_LOWER_MEM; hose->mem_space.end = MVME5100_PCI_UPPER_MEM; hose->io_base_virt = (void *)MVME5100_ISA_IO_BASE; /* Use indirect method of Hawk */ setup_indirect_pci(hose, MVME5100_PCI_CONFIG_ADDR, MVME5100_PCI_CONFIG_DATA); hose->last_busno = pciauto_bus_scan(hose, hose->first_busno); ppc_md.pcibios_fixup_resources = mvme5100_pcibios_fixup_resources; ppc_md.pci_swizzle = common_swizzle; ppc_md.pci_map_irq = mvme5100_map_irq; }
static int __init mvme5100_add_bridge(struct device_node *dev) { const int *bus_range; int len; struct pci_controller *hose; unsigned short devid; pr_info("Adding PCI host bridge %s\n", dev->full_name); bus_range = of_get_property(dev, "bus-range", &len); hose = pcibios_alloc_controller(dev); if (hose == NULL) return -ENOMEM; hose->first_busno = bus_range ? bus_range[0] : 0; hose->last_busno = bus_range ? bus_range[1] : 0xff; setup_indirect_pci(hose, 0xfe000cf8, 0xfe000cfc, 0); pci_process_bridge_OF_ranges(hose, dev, 1); early_read_config_word(hose, 0, 0, PCI_DEVICE_ID, &devid); if (devid != PCI_DEVICE_ID_MOTOROLA_HAWK) { pr_err("HAWK PHB not present?\n"); return 0; } early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_1, &pci_membase); if (pci_membase == 0) { pr_err("HAWK PHB mibar not correctly set?\n"); return 0; } pr_info("mvme5100_pic_init: pci_membase: %x\n", pci_membase); return 0; }
void __init spruce_setup_hose(void) { struct pci_controller *hose; /* Setup hose */ hose = pcibios_alloc_controller(); if (!hose) return; hose->first_busno = 0; hose->last_busno = 0xff; pci_init_resource(&hose->io_resource, SPRUCE_PCI_LOWER_IO, SPRUCE_PCI_UPPER_IO, IORESOURCE_IO, "PCI host bridge"); pci_init_resource(&hose->mem_resources[0], SPRUCE_PCI_LOWER_MEM, SPRUCE_PCI_UPPER_MEM, IORESOURCE_MEM, "PCI host bridge"); hose->io_space.start = SPRUCE_PCI_LOWER_IO; hose->io_space.end = SPRUCE_PCI_UPPER_IO; hose->mem_space.start = SPRUCE_PCI_LOWER_MEM; hose->mem_space.end = SPRUCE_PCI_UPPER_MEM; hose->io_base_virt = (void *)SPRUCE_ISA_IO_BASE; setup_indirect_pci(hose, SPRUCE_PCI_CONFIG_ADDR, SPRUCE_PCI_CONFIG_DATA); hose->last_busno = pciauto_bus_scan(hose, hose->first_busno); ppc_md.pci_swizzle = common_swizzle; ppc_md.pci_map_irq = spruce_map_irq; }
void __init pal4_find_bridges(void) { struct pci_controller *hose; hose = pcibios_alloc_controller(); if (!hose) return; hose->first_busno = 0; hose->last_busno = 0xff; hose->pci_mem_offset = 0; /* Could snatch these from the CPC700.... */ pci_init_resource(&hose->io_resource, 0x0, 0x03ffffff, IORESOURCE_IO, "PCI host bridge"); pci_init_resource(&hose->mem_resources[0], 0x90000000, 0x9fffffff, IORESOURCE_MEM, "PCI host bridge"); hose->io_space.start = 0x00800000; hose->io_space.end = 0x03ffffff; hose->mem_space.start = 0x90000000; hose->mem_space.end = 0x9fffffff; hose->io_base_virt = (void *) 0xf8000000; setup_indirect_pci(hose, CPC700_PCI_CONFIG_ADDR, CPC700_PCI_CONFIG_DATA); hose->last_busno = pciauto_bus_scan(hose, hose->first_busno); ppc_md.pci_swizzle = common_swizzle; ppc_md.pci_map_irq = pal4_map_irq; }
static void __init luan_setup_hose(struct pci_controller *hose, int lower_mem, int upper_mem, int cfga, int cfgd, u64 pcix_io_base) { char name[20]; sprintf(name, "PCIX%d host bridge", hose->index); hose->pci_mem_offset = LUAN_PCIX_MEM_OFFSET; pci_init_resource(&hose->io_resource, LUAN_PCIX_LOWER_IO, LUAN_PCIX_UPPER_IO, IORESOURCE_IO, name); pci_init_resource(&hose->mem_resources[0], lower_mem, upper_mem, IORESOURCE_MEM, name); hose->io_space.start = LUAN_PCIX_LOWER_IO; hose->io_space.end = LUAN_PCIX_UPPER_IO; hose->mem_space.start = lower_mem; hose->mem_space.end = upper_mem; isa_io_base = (unsigned long)ioremap64(pcix_io_base, PCIX_IO_SIZE); hose->io_base_virt = (void *)isa_io_base; setup_indirect_pci(hose, cfga, cfgd); hose->set_cfg_type = 1; }
static void __init setup_python(struct pci_controller *hose, struct device_node *dev) { u32 __iomem *reg; u32 val; struct resource r; if (of_address_to_resource(dev, 0, &r)) { printk(KERN_ERR "No address for Python PCI controller\n"); return; } /* Clear the magic go-slow bit */ reg = ioremap(r.start + 0xf6000, 0x40); BUG_ON(!reg); val = in_be32(®[12]); if (val & PRG_CL_RESET_VALID) { out_be32(®[12], val & ~PRG_CL_RESET_VALID); in_be32(®[12]); } iounmap(reg); setup_indirect_pci(hose, r.start + 0xf8000, r.start + 0xf8010); }
static void __init pq2_pci_add_bridge(struct device_node *np) { struct pci_controller *hose; struct resource r; if (of_address_to_resource(np, 0, &r) || r.end - r.start < 0x10b) goto err; pci_add_flags(PCI_REASSIGN_ALL_BUS); hose = pcibios_alloc_controller(np); if (!hose) return; hose->dn = np; setup_indirect_pci(hose, r.start + 0x100, r.start + 0x104, 0); pci_process_bridge_OF_ranges(hose, np, 1); return; err: printk(KERN_ERR "No valid PCI reg property in device tree\n"); }
static void __init ppc4xx_probe_pcix_bridge(struct device_node *np) { struct resource rsrc_cfg; struct resource rsrc_reg; struct resource dma_window; struct pci_controller *hose = NULL; void __iomem *reg = NULL; const int *bus_range; int big_pim = 0, msi = 0, primary = 0; /* Fetch config space registers address */ if (of_address_to_resource(np, 0, &rsrc_cfg)) { printk(KERN_ERR "%s:Can't get PCI-X config register base !", np->full_name); return; } /* Fetch host bridge internal registers address */ if (of_address_to_resource(np, 3, &rsrc_reg)) { printk(KERN_ERR "%s: Can't get PCI-X internal register base !", np->full_name); return; } /* Check if it supports large PIMs (440GX) */ if (of_get_property(np, "large-inbound-windows", NULL)) big_pim = 1; /* Check if we should enable MSIs inbound hole */ if (of_get_property(np, "enable-msi-hole", NULL)) msi = 1; /* Check if primary bridge */ if (of_get_property(np, "primary", NULL)) primary = 1; /* Get bus range if any */ bus_range = of_get_property(np, "bus-range", NULL); /* Map registers */ reg = ioremap(rsrc_reg.start, rsrc_reg.end + 1 - rsrc_reg.start); if (reg == NULL) { printk(KERN_ERR "%s: Can't map registers !", np->full_name); goto fail; } /* Allocate the host controller data structure */ hose = pcibios_alloc_controller(np); if (!hose) goto fail; hose->first_busno = bus_range ? bus_range[0] : 0x0; hose->last_busno = bus_range ? bus_range[1] : 0xff; /* Setup config space */ setup_indirect_pci(hose, rsrc_cfg.start, rsrc_cfg.start + 0x4, PPC_INDIRECT_TYPE_SET_CFG_TYPE); /* Disable all windows */ writel(0, reg + PCIX0_POM0SA); writel(0, reg + PCIX0_POM1SA); writel(0, reg + PCIX0_POM2SA); writel(0, reg + PCIX0_PIM0SA); writel(0, reg + PCIX0_PIM1SA); writel(0, reg + PCIX0_PIM2SA); if (big_pim) { writel(0, reg + PCIX0_PIM0SAH); writel(0, reg + PCIX0_PIM2SAH); } /* Parse outbound mapping resources */ pci_process_bridge_OF_ranges(hose, np, primary); /* Parse inbound mapping resources */ if (ppc4xx_parse_dma_ranges(hose, reg, &dma_window) != 0) goto fail; /* Configure outbound ranges POMs */ ppc4xx_configure_pcix_POMs(hose, reg); /* Configure inbound ranges PIMs */ ppc4xx_configure_pcix_PIMs(hose, reg, &dma_window, big_pim, msi); /* We don't need the registers anymore */ iounmap(reg); return; fail: if (hose) pcibios_free_controller(hose); if (reg) iounmap(reg); }
static void __init ppc4xx_probe_pci_bridge(struct device_node *np) { /* NYI */ struct resource rsrc_cfg; struct resource rsrc_reg; struct resource dma_window; struct pci_controller *hose = NULL; void __iomem *reg = NULL; const int *bus_range; int primary = 0; /* Check if device is enabled */ if (!of_device_is_available(np)) { printk(KERN_INFO "%s: Port disabled via device-tree\n", np->full_name); return; } /* Fetch config space registers address */ if (of_address_to_resource(np, 0, &rsrc_cfg)) { printk(KERN_ERR "%s: Can't get PCI config register base !", np->full_name); return; } /* Fetch host bridge internal registers address */ if (of_address_to_resource(np, 3, &rsrc_reg)) { printk(KERN_ERR "%s: Can't get PCI internal register base !", np->full_name); return; } /* Check if primary bridge */ if (of_get_property(np, "primary", NULL)) primary = 1; /* Get bus range if any */ bus_range = of_get_property(np, "bus-range", NULL); /* Map registers */ reg = ioremap(rsrc_reg.start, rsrc_reg.end + 1 - rsrc_reg.start); if (reg == NULL) { printk(KERN_ERR "%s: Can't map registers !", np->full_name); goto fail; } /* Allocate the host controller data structure */ hose = pcibios_alloc_controller(np); if (!hose) goto fail; hose->first_busno = bus_range ? bus_range[0] : 0x0; hose->last_busno = bus_range ? bus_range[1] : 0xff; /* Setup config space */ setup_indirect_pci(hose, rsrc_cfg.start, rsrc_cfg.start + 0x4, 0); /* Disable all windows */ writel(0, reg + PCIL0_PMM0MA); writel(0, reg + PCIL0_PMM1MA); writel(0, reg + PCIL0_PMM2MA); writel(0, reg + PCIL0_PTM1MS); writel(0, reg + PCIL0_PTM2MS); /* Parse outbound mapping resources */ pci_process_bridge_OF_ranges(hose, np, primary); /* Parse inbound mapping resources */ if (ppc4xx_parse_dma_ranges(hose, reg, &dma_window) != 0) goto fail; /* Configure outbound ranges POMs */ ppc4xx_configure_pci_PMMs(hose, reg); /* Configure inbound ranges PIMs */ ppc4xx_configure_pci_PTMs(hose, reg, &dma_window); /* We don't need the registers anymore */ iounmap(reg); return; fail: if (hose) pcibios_free_controller(hose); if (reg) iounmap(reg); }
void __init mpc85xx_setup_hose(void) { struct pci_controller *hose_a; #ifdef CONFIG_85xx_PCI2 struct pci_controller *hose_b; #endif bd_t *binfo = (bd_t *) __res; hose_a = pcibios_alloc_controller(); if (!hose_a) return; ppc_md.pci_swizzle = common_swizzle; ppc_md.pci_map_irq = mpc85xx_map_irq; hose_a->first_busno = 0; hose_a->bus_offset = 0; hose_a->last_busno = 0xff; setup_indirect_pci(hose_a, binfo->bi_immr_base + PCI1_CFG_ADDR_OFFSET, binfo->bi_immr_base + PCI1_CFG_DATA_OFFSET); hose_a->set_cfg_type = 1; mpc85xx_setup_pci1(hose_a); hose_a->pci_mem_offset = MPC85XX_PCI1_MEM_OFFSET; hose_a->mem_space.start = MPC85XX_PCI1_LOWER_MEM; hose_a->mem_space.end = MPC85XX_PCI1_UPPER_MEM; hose_a->io_space.start = MPC85XX_PCI1_LOWER_IO; hose_a->io_space.end = MPC85XX_PCI1_UPPER_IO; hose_a->io_base_phys = MPC85XX_PCI1_IO_BASE; #ifdef CONFIG_85xx_PCI2 hose_a->io_base_virt = ioremap(MPC85XX_PCI1_IO_BASE, MPC85XX_PCI1_IO_SIZE + MPC85XX_PCI2_IO_SIZE); #else hose_a->io_base_virt = ioremap(MPC85XX_PCI1_IO_BASE, MPC85XX_PCI1_IO_SIZE); #endif isa_io_base = (unsigned long)hose_a->io_base_virt; /* setup resources */ pci_init_resource(&hose_a->mem_resources[0], MPC85XX_PCI1_LOWER_MEM, MPC85XX_PCI1_UPPER_MEM, IORESOURCE_MEM, "PCI1 host bridge"); pci_init_resource(&hose_a->io_resource, MPC85XX_PCI1_LOWER_IO, MPC85XX_PCI1_UPPER_IO, IORESOURCE_IO, "PCI1 host bridge"); ppc_md.pci_exclude_device = mpc85xx_exclude_device; #if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS) /* Pre pciauto_bus_scan VIA init */ mpc85xx_cds_enable_via(hose_a); #endif hose_a->last_busno = pciauto_bus_scan(hose_a, hose_a->first_busno); #if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS) /* Post pciauto_bus_scan VIA fixup */ mpc85xx_cds_fixup_via(hose_a); #endif #ifdef CONFIG_85xx_PCI2 hose_b = pcibios_alloc_controller(); if (!hose_b) return; hose_b->bus_offset = hose_a->last_busno + 1; hose_b->first_busno = hose_a->last_busno + 1; hose_b->last_busno = 0xff; setup_indirect_pci(hose_b, binfo->bi_immr_base + PCI2_CFG_ADDR_OFFSET, binfo->bi_immr_base + PCI2_CFG_DATA_OFFSET); hose_b->set_cfg_type = 1; mpc85xx_setup_pci2(hose_b); hose_b->pci_mem_offset = MPC85XX_PCI2_MEM_OFFSET; hose_b->mem_space.start = MPC85XX_PCI2_LOWER_MEM; hose_b->mem_space.end = MPC85XX_PCI2_UPPER_MEM; hose_b->io_space.start = MPC85XX_PCI2_LOWER_IO; hose_b->io_space.end = MPC85XX_PCI2_UPPER_IO; hose_b->io_base_phys = MPC85XX_PCI2_IO_BASE; hose_b->io_base_virt = hose_a->io_base_virt + MPC85XX_PCI1_IO_SIZE; /* setup resources */ pci_init_resource(&hose_b->mem_resources[0], MPC85XX_PCI2_LOWER_MEM, MPC85XX_PCI2_UPPER_MEM, IORESOURCE_MEM, "PCI2 host bridge"); pci_init_resource(&hose_b->io_resource, MPC85XX_PCI2_LOWER_IO, MPC85XX_PCI2_UPPER_IO, IORESOURCE_IO, "PCI2 host bridge"); hose_b->last_busno = pciauto_bus_scan(hose_b, hose_b->first_busno); /* let board code know what the last bus number was on PCI1 */ mpc85xx_pci1_last_busno = hose_a->last_busno; #endif return; }
static void __init yucca_setup_hoses(void) { struct pci_controller *hose; char name[20]; enum yucca_hoses hs; int bus_no = 0; for (hs = HOSE_PCIX; hs < HOSE_MAX; ++hs) { if (is_pcie_hose(hs)) { if (!yucca_pcie_card_present(pcie_hose_num(hs))) continue; pr_debug("PCIE%d: card present\n", pcie_hose_num(hs)); yucca_setup_pcie_fpga_root_or_endpoint(pcie_hose_num(hs)); if (ppc440spe_init_pcie_root_or_endport(pcie_hose_num(hs))) { printk(KERN_ERR "PCIE%d: initialization " "failed\n", pcie_hose_num(hs)); continue; } } hose = pcibios_alloc_controller(); if (!hose) return; sprintf(name, "PCI%s%d host bridge", is_pcix_hose(hs) ? "X" : "E", is_pcie_hose(hs) ? pcie_hose_num(hs) : 0 ); pci_init_resource(&hose->io_resource, YUCCA_PCIX_LOWER_IO, YUCCA_PCIX_UPPER_IO, IORESOURCE_IO, name); if (is_pcix_hose(hs)) { hose->mem_space.start = YUCCA_PCIX_LOWER_MEM; hose->mem_space.end = hose->mem_space.start + YUCCA_PCIX_MEM_SIZE - 1; } else { hose->mem_space.start = YUCCA_PCIE_LOWER_MEM + pcie_hose_num(hs) * YUCCA_PCIE_MEM_SIZE; hose->mem_space.end = hose->mem_space.start + YUCCA_PCIE_MEM_SIZE - 1; } pci_init_resource(&hose->mem_resources[0], hose->mem_space.start, hose->mem_space.end, IORESOURCE_MEM, name); hose->first_busno = bus_no; hose->last_busno = 0xFF; hose_type[hose->index] = hs; if (is_pcix_hose(hs)) { hose->io_space.start = YUCCA_PCIX_LOWER_IO; hose->io_space.end = YUCCA_PCIX_UPPER_IO; isa_io_base = (unsigned long) ioremap64(PCIX0_IO_BASE, PCIX_IO_SIZE); hose->io_base_virt = (void *)isa_io_base; ppc440spe_setup_pcix(hose); setup_indirect_pci(hose, PCIX0_CFGA, PCIX0_CFGD); hose->set_cfg_type = 1; } else { if(ppc440spe_setup_pcie(hose, pcie_hose_num(hs)) != 0) { printk(KERN_WARNING"PCIE setup failed for hose no %d\n", pcie_hose_num(hs)); continue; } } hose->last_busno = pciauto_bus_scan(hose, hose->first_busno); bus_no = hose->last_busno + 1; pr_debug("%s: resources allocated\n", name); } ppc_md.pci_swizzle = common_swizzle; ppc_md.pci_map_irq = yucca_map_irq; }
void __init chrp_find_bridges(void) { struct device_node *dev; int *bus_range; int len, index = -1; struct pci_controller *hose; unsigned int *dma; char *model, *machine; int is_longtrail = 0, is_mot = 0, is_pegasos = 0; struct device_node *root = find_path_device("/"); /* * The PCI host bridge nodes on some machines don't have * properties to adequately identify them, so we have to * look at what sort of machine this is as well. */ machine = get_property(root, "model", NULL); if (machine != NULL) { is_longtrail = strncmp(machine, "IBM,LongTrail", 13) == 0; is_mot = strncmp(machine, "MOT", 3) == 0; if (strncmp(machine, "Pegasos2", 8) == 0) is_pegasos = 2; else if (strncmp(machine, "Pegasos", 7) == 0) is_pegasos = 1; } for (dev = root->child; dev != NULL; dev = dev->sibling) { if (dev->type == NULL || strcmp(dev->type, "pci") != 0) continue; ++index; /* The GG2 bridge on the LongTrail doesn't have an address */ if (dev->n_addrs < 1 && !is_longtrail) { printk(KERN_WARNING "Can't use %s: no address\n", dev->full_name); continue; } bus_range = (int *) get_property(dev, "bus-range", &len); if (bus_range == NULL || len < 2 * sizeof(int)) { printk(KERN_WARNING "Can't get bus-range for %s\n", dev->full_name); continue; } if (bus_range[1] == bus_range[0]) printk(KERN_INFO "PCI bus %d", bus_range[0]); else printk(KERN_INFO "PCI buses %d..%d", bus_range[0], bus_range[1]); printk(" controlled by %s", dev->type); if (dev->n_addrs > 0) printk(" at %lx", dev->addrs[0].address); printk("\n"); hose = pcibios_alloc_controller(); if (!hose) { printk("Can't allocate PCI controller structure for %s\n", dev->full_name); continue; } hose->arch_data = dev; hose->first_busno = bus_range[0]; hose->last_busno = bus_range[1]; model = get_property(dev, "model", NULL); if (model == NULL) model = "<none>"; if (device_is_compatible(dev, "IBM,python")) { setup_python(hose, dev); } else if (is_mot || strncmp(model, "Motorola, Grackle", 17) == 0) { setup_grackle(hose); } else if (is_longtrail) { void __iomem *p = ioremap(GG2_PCI_CONFIG_BASE, 0x80000); hose->ops = &gg2_pci_ops; hose->cfg_data = p; gg2_pci_config_base = p; } else if (is_pegasos == 1) { setup_indirect_pci(hose, 0xfec00cf8, 0xfee00cfc); } else if (is_pegasos == 2) { setup_peg2(hose, dev); } else { printk("No methods for %s (model %s), using RTAS\n", dev->full_name, model); hose->ops = &rtas_pci_ops; } pci_process_bridge_OF_ranges(hose, dev, index == 0); /* check the first bridge for a property that we can use to set pci_dram_offset */ dma = (unsigned int *) get_property(dev, "ibm,dma-ranges", &len); if (index == 0 && dma != NULL && len >= 6 * sizeof(*dma)) { pci_dram_offset = dma[2] - dma[3]; printk("pci_dram_offset = %lx\n", pci_dram_offset); } } /* Do not fixup interrupts from OF tree on pegasos */ if (is_pegasos == 0) ppc_md.pcibios_fixup = chrp_pcibios_fixup; }
void ppc4xx_find_bridges(void) { struct pci_controller *hose_a; struct pcil0_regs *pcip; unsigned int new_pmm_max; unsigned int new_pmm_min; isa_io_base = 0; isa_mem_base = 0; pci_dram_offset = 0; #if (PSR_PCI_ARBIT_EN > 1) /* Check if running in slave mode */ if ((mfdcr(DCRN_CHPSR) & PSR_PCI_ARBIT_EN) == 0) { printk("Running as PCI slave, kernel PCI disabled !\n"); return; } #endif /* Setup PCI32 hose */ hose_a = pcibios_alloc_controller(); if (!hose_a) return; setup_indirect_pci(hose_a, PPC405_PCI_CONFIG_ADDR, PPC405_PCI_CONFIG_DATA); #ifdef CONFIG_XILINX_OCP /* Eliminate "unused variable" warning for pcip. Optimizer removes. */ pcip = NULL; new_pmm_min = PPC405_PCI_LOWER_MEM; new_pmm_max = PPC405_PCI_UPPER_MEM; #else /* Must be IBM */ pcip = ioremap(PPC4xx_PCI_LCFG_PADDR, PAGE_SIZE); if (pcip != NULL) { unsigned int tmp_addr; unsigned int tmp_size; unsigned int reg_index; #if defined(CONFIG_BIOS_FIXUP) bios_fixup(hose_a, pcip); #endif new_pmm_min = 0xffffffff; for (reg_index = 0; reg_index < 3; reg_index++) { tmp_size = in_le32((void *) &(pcip->pmm[reg_index].ma)); // *_PMM0MA if (tmp_size & 0x1) { tmp_addr = in_le32((void *) &(pcip->pmm[reg_index].pcila)); // *_PMM0PCILA if (tmp_addr < PPC405_PCI_PHY_MEM_BASE) { printk(KERN_DEBUG "Disabling mapping to PCI mem addr 0x%8.8x\n", tmp_addr); out_le32((void *) &(pcip->pmm[reg_index].ma), tmp_size & ~1); // *_PMMOMA } else { tmp_addr = in_le32((void *) &(pcip->pmm[reg_index].la)); // *_PMMOLA if (tmp_addr < new_pmm_min) new_pmm_min = tmp_addr; tmp_addr = tmp_addr + (0xffffffff - (tmp_size & 0xffffc000)); if (tmp_addr > PPC405_PCI_UPPER_MEM) { new_pmm_max = tmp_addr; // PPC405_PCI_UPPER_MEM } else { new_pmm_max = PPC405_PCI_UPPER_MEM; } } } } // for iounmap(pcip); } #endif hose_a->first_busno = 0; hose_a->last_busno = 0xff; hose_a->pci_mem_offset = 0; /* Setup bridge memory/IO ranges & resources * TODO: Handle firmwares setting up a legacy ISA mem base */ hose_a->io_space.start = PPC405_PCI_LOWER_IO; hose_a->io_space.end = PPC405_PCI_UPPER_IO; hose_a->mem_space.start = new_pmm_min; hose_a->mem_space.end = new_pmm_max; hose_a->io_base_phys = PPC405_PCI_PHY_IO_BASE; hose_a->io_base_virt = ioremap(hose_a->io_base_phys, 0x10000); hose_a->io_resource.start = 0; hose_a->io_resource.end = PPC405_PCI_UPPER_IO - PPC405_PCI_LOWER_IO; hose_a->io_resource.flags = IORESOURCE_IO; hose_a->io_resource.name = "PCI I/O"; hose_a->mem_resources[0].start = new_pmm_min; hose_a->mem_resources[0].end = new_pmm_max; hose_a->mem_resources[0].flags = IORESOURCE_MEM; hose_a->mem_resources[0].name = "PCI Memory"; isa_io_base = (int) hose_a->io_base_virt; isa_mem_base = 0; /* ISA not implemented */ ISA_DMA_THRESHOLD = 0x00ffffff; /* ??? ISA not implemented */ /* Scan busses & initial setup by pci_auto */ hose_a->last_busno = pciauto_bus_scan(hose_a, hose_a->first_busno); /* Setup ppc_md */ ppc_md.pcibios_fixup = NULL; ppc_md.pci_exclude_device = ppc4xx_exclude_device; ppc_md.pcibios_fixup_resources = ppc405_pcibios_fixup_resources; ppc_md.pci_swizzle = common_swizzle; ppc_md.pci_map_irq = ppc405_map_irq; }
void __init mpc83xx_setup_hose(void) { u32 val32; volatile immr_clk_t * clk; struct pci_controller * hose1; #ifdef CONFIG_MPC83xx_PCI2 struct pci_controller * hose2; #endif bd_t * binfo = (bd_t *)__res; clk = ioremap(binfo->bi_immr_base + 0xA00, sizeof(immr_clk_t)); /* * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode */ val32 = clk->occr; udelay(2000); clk->occr = 0xff000000; udelay(2000); iounmap(clk); hose1 = pcibios_alloc_controller(); if(!hose1) return; ppc_md.pci_swizzle = common_swizzle; ppc_md.pci_map_irq = mpc83xx_map_irq; hose1->bus_offset = 0; hose1->first_busno = 0; hose1->last_busno = 0xff; setup_indirect_pci(hose1, binfo->bi_immr_base + PCI1_CFG_ADDR_OFFSET, binfo->bi_immr_base + PCI1_CFG_DATA_OFFSET); hose1->set_cfg_type = 1; mpc83xx_setup_pci1(hose1); hose1->pci_mem_offset = MPC83xx_PCI1_MEM_OFFSET; hose1->mem_space.start = MPC83xx_PCI1_LOWER_MEM; hose1->mem_space.end = MPC83xx_PCI1_UPPER_MEM; hose1->io_base_phys = MPC83xx_PCI1_IO_BASE; hose1->io_space.start = MPC83xx_PCI1_LOWER_IO; hose1->io_space.end = MPC83xx_PCI1_UPPER_IO; #ifdef CONFIG_MPC83xx_PCI2 isa_io_base = (unsigned long)ioremap(MPC83xx_PCI1_IO_BASE, MPC83xx_PCI1_IO_SIZE + MPC83xx_PCI2_IO_SIZE); #else isa_io_base = (unsigned long)ioremap(MPC83xx_PCI1_IO_BASE, MPC83xx_PCI1_IO_SIZE); #endif /* CONFIG_MPC83xx_PCI2 */ hose1->io_base_virt = (void *)isa_io_base; /* setup resources */ pci_init_resource(&hose1->io_resource, MPC83xx_PCI1_LOWER_IO, MPC83xx_PCI1_UPPER_IO, IORESOURCE_IO, "PCI host bridge 1"); pci_init_resource(&hose1->mem_resources[0], MPC83xx_PCI1_LOWER_MEM, MPC83xx_PCI1_UPPER_MEM, IORESOURCE_MEM, "PCI host bridge 1"); ppc_md.pci_exclude_device = mpc83xx_exclude_device; hose1->last_busno = pciauto_bus_scan(hose1, hose1->first_busno); #ifdef CONFIG_MPC83xx_PCI2 hose2 = pcibios_alloc_controller(); if(!hose2) return; hose2->bus_offset = hose1->last_busno + 1; hose2->first_busno = hose1->last_busno + 1; hose2->last_busno = 0xff; setup_indirect_pci(hose2, binfo->bi_immr_base + PCI2_CFG_ADDR_OFFSET, binfo->bi_immr_base + PCI2_CFG_DATA_OFFSET); hose2->set_cfg_type = 1; mpc83xx_setup_pci2(hose2); hose2->pci_mem_offset = MPC83xx_PCI2_MEM_OFFSET; hose2->mem_space.start = MPC83xx_PCI2_LOWER_MEM; hose2->mem_space.end = MPC83xx_PCI2_UPPER_MEM; hose2->io_base_phys = MPC83xx_PCI2_IO_BASE; hose2->io_space.start = MPC83xx_PCI2_LOWER_IO; hose2->io_space.end = MPC83xx_PCI2_UPPER_IO; hose2->io_base_virt = (void *)(isa_io_base + MPC83xx_PCI1_IO_SIZE); /* setup resources */ pci_init_resource(&hose2->io_resource, MPC83xx_PCI2_LOWER_IO, MPC83xx_PCI2_UPPER_IO, IORESOURCE_IO, "PCI host bridge 2"); pci_init_resource(&hose2->mem_resources[0], MPC83xx_PCI2_LOWER_MEM, MPC83xx_PCI2_UPPER_MEM, IORESOURCE_MEM, "PCI host bridge 2"); hose2->last_busno = pciauto_bus_scan(hose2, hose2->first_busno); #endif /* CONFIG_MPC83xx_PCI2 */ }
void ppc4xx_find_bridges(void) { struct pci_controller *hose_a; struct pcil0_regs *pcip; unsigned int tmp_addr; unsigned int tmp_size; unsigned int reg_index; unsigned int new_pmm_max = 0; unsigned int new_pmm_min = 0; isa_io_base = 0; isa_mem_base = 0; pci_dram_offset = 0; /* Setup PCI32 hose */ hose_a = pcibios_alloc_controller(); if (!hose_a) return; setup_indirect_pci(hose_a, PPC405_PCI_CONFIG_ADDR, PPC405_PCI_CONFIG_DATA); pcip = ioremap(PPC4xx_PCI_LCFG_PADDR, PAGE_SIZE); if (pcip != NULL) { #if defined(CONFIG_BIOS_FIXUP) bios_fixup(hose_a, pcip); #endif new_pmm_min = 0xffffffff; for (reg_index = 0; reg_index < 3; reg_index++) { tmp_size = in_le32(&pcip->pmm[reg_index].ma); // mask & attrs /* test the enable bit */ if ((tmp_size & 0x1) == 0) continue; tmp_addr = in_le32(&pcip->pmm[reg_index].pcila); // PCI addr if (tmp_addr < PPC405_PCI_PHY_MEM_BASE) { printk(KERN_DEBUG "Disabling mapping to PCI mem addr 0x%8.8x\n", tmp_addr); out_le32(&pcip->pmm[reg_index].ma, tmp_size & ~1); // *_PMMOMA continue; } tmp_addr = in_le32(&pcip->pmm[reg_index].la); // *_PMMOLA if (tmp_addr < new_pmm_min) new_pmm_min = tmp_addr; tmp_addr = tmp_addr + (0xffffffff - (tmp_size & 0xffffc000)); if (tmp_addr > PPC405_PCI_UPPER_MEM) { new_pmm_max = tmp_addr; // PPC405_PCI_UPPER_MEM } else { new_pmm_max = PPC405_PCI_UPPER_MEM; } } // for iounmap(pcip); } hose_a->first_busno = 0; hose_a->last_busno = 0xff; hose_a->pci_mem_offset = 0; /* Setup bridge memory/IO ranges & resources * TODO: Handle firmwares setting up a legacy ISA mem base */ hose_a->io_space.start = PPC405_PCI_LOWER_IO; hose_a->io_space.end = PPC405_PCI_UPPER_IO; hose_a->mem_space.start = new_pmm_min; hose_a->mem_space.end = new_pmm_max; hose_a->io_base_phys = PPC405_PCI_PHY_IO_BASE; hose_a->io_base_virt = ioremap(hose_a->io_base_phys, 0x10000); hose_a->io_resource.start = 0; hose_a->io_resource.end = PPC405_PCI_UPPER_IO - PPC405_PCI_LOWER_IO; hose_a->io_resource.flags = IORESOURCE_IO; hose_a->io_resource.name = "PCI I/O"; hose_a->mem_resources[0].start = new_pmm_min; hose_a->mem_resources[0].end = new_pmm_max; hose_a->mem_resources[0].flags = IORESOURCE_MEM; hose_a->mem_resources[0].name = "PCI Memory"; isa_io_base = (int) hose_a->io_base_virt; isa_mem_base = 0; /* ISA not implemented */ ISA_DMA_THRESHOLD = 0x00ffffff; /* ??? ISA not implemented */ /* Scan busses & initial setup by pci_auto */ hose_a->last_busno = pciauto_bus_scan(hose_a, hose_a->first_busno); hose_a->last_busno = 0; /* Setup ppc_md */ ppc_md.pcibios_fixup = NULL; ppc_md.pci_exclude_device = ppc4xx_exclude_device; ppc_md.pcibios_fixup_resources = ppc405_pcibios_fixup_resources; ppc_md.pci_swizzle = common_swizzle; ppc_md.pci_map_irq = ppc405_map_irq; }