static void ioapic_init(struct device *dev)
{
void *ioapic_base;
pci_write_config32(dev, 0xF8, 0x1);
ioapic_base = (void *)(pci_read_config32(dev, 0xFC) & 0xfffffff0);
clear_ioapic(ioapic_base);
setup_ioapic(ioapic_base, 1);
}
static void lpc_common_init(device_t dev)
{
uint8_t byte;
uint32_t ioapic_base;
/* IO APIC initialization */
byte = pci_read_config8(dev, 0x74);
byte |= (1<<0); // enable APIC
pci_write_config8(dev, 0x74, byte);
ioapic_base = pci_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14
setup_ioapic(ioapic_base, 0); // Don't rename IO APIC ID
}
static void lpc_common_init(device_t dev)
{
u32 dword;
struct resource *res;
/* I/O APIC initialization. */
res = find_resource(dev, PCI_BASE_ADDRESS_1); /* IOAPIC */
ASSERT(res != NULL);
setup_ioapic(res->base, 0); /* Don't rename IOAPIC ID. */
#if 1
dword = pci_read_config32(dev, 0xe4);
dword |= (1 << 23);
pci_write_config32(dev, 0xe4, dword);
#endif
}
static void lpc_init(struct device *dev)
{
uint8_t byte;
int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
i82801ex_general_cntl(dev);
/* IO APIC initialization. */
setup_ioapic(VIO_APIC_VADDR, 0); // Don't rename IO APIC ID.
i82801ex_enable_serial_irqs(dev);
i82801ex_pci_dma_cfg(dev);
i82801ex_enable_lpc(dev);
/* Clear SATA to non raid */
pci_write_config8(dev, 0xae, 0x00);
get_option(&pwr_on, "power_on_after_fail");
byte = pci_read_config8(dev, 0xa4);
byte &= 0xfe;
if (!pwr_on) {
byte |= 1;
}
pci_write_config8(dev, 0xa4, byte);
printk(BIOS_INFO, "set power %s after power fail\n", pwr_on?"on":"off");
/* Set up the PIRQ */
i82801ex_pirq_init(dev);
/* Set the state of the gpio lines */
i82801ex_gpio_init(dev);
/* Initialize the real time clock */
cmos_init(0);
/* Initialize isa dma */
isa_dma_init();
/* Disable IDE (needed when sata is enabled) */
pci_write_config8(dev, 0xf2, 0x60);
enable_hpet(dev);
}
static void i82801ix_enable_apic(struct device *dev)
{
u32 reg32;
volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR);
volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
/* Enable IOAPIC. Keep APIC Range Select at zero. */
RCBA8(0x31ff) = 0x03;
/* We have to read 0x31ff back if bit0 changed. */
RCBA8(0x31ff);
/* Lock maximum redirection entries (MRE), R/WO register. */
*ioapic_index = 0x01;
reg32 = *ioapic_data;
*ioapic_index = 0x01;
*ioapic_data = reg32;
setup_ioapic(IO_APIC_ADDR, 2); /* ICH7 code uses id 2. */
}
static void lpc_common_init(device_t dev)
{
u8 byte;
u32 dword;
/* I/O APIC initialization. */
byte = pci_read_config8(dev, 0x74);
byte |= (1 << 0); /* Enable APIC. */
pci_write_config8(dev, 0x74, byte);
dword = pci_read_config32(dev, PCI_BASE_ADDRESS_1); /* 0x14 */
setup_ioapic(dword, 0); /* Don't rename IOAPIC ID. */
#if 1
dword = pci_read_config32(dev, 0xe4);
dword |= (1 << 23);
pci_write_config32(dev, 0xe4, dword);
#endif
}
static void sb700_enable(device_t dev)
{
struct southbridge_amd_cimx_sb700_config *sb_chip =
(struct southbridge_amd_cimx_sb700_config *)(dev->chip_info);
printk(BIOS_DEBUG, "sb700_enable() ");
switch (dev->path.pci.devfn) {
case (0x11 << 3) | 0: /* 0:11.0 SATA */
sb700_cimx_config(sb_config);
if (dev->enabled) {
sb_config->SataController = CIMX_OPTION_ENABLED;
if (1 == sb_chip->boot_switch_sata_ide)
sb_config->SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary.
else if (0 == sb_chip->boot_switch_sata_ide)
sb_config->SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary.
} else {
sb_config->SataController = CIMX_OPTION_DISABLED;
}
break;
case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */
case (0x12 << 3) | 2: /* 0:12:2 EHCI-USB1 */
case (0x13 << 3) | 0: /* 0:13:0 OHCI-USB2 */
case (0x13 << 3) | 2: /* 0:13:2 EHCI-USB2 */
break;
case (0x14 << 3) | 0: /* 0:14:0 SMBUS */
{
u32 ioapic_base;
printk(BIOS_DEBUG, "sm_init().\n");
ioapic_base = IO_APIC_ADDR;
clear_ioapic(ioapic_base);
/* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */
if (CONFIG_MAX_CPUS >= 16)
setup_ioapic(ioapic_base, 0);
else
setup_ioapic(ioapic_base, CONFIG_MAX_CPUS + 1);
}
break;
case (0x14 << 3) | 1: /* 0:14:1 IDE */
break;
case (0x14 << 3) | 2: /* 0:14:2 HDA */
if (dev->enabled) {
if (AZALIA_DISABLE == sb_config->AzaliaController) {
sb_config->AzaliaController = AZALIA_AUTO;
}
printk(BIOS_DEBUG, "hda enabled\n");
} else {
sb_config->AzaliaController = AZALIA_DISABLE;
printk(BIOS_DEBUG, "hda disabled\n");
}
break;
case (0x14 << 3) | 3: /* 0:14:3 LPC */
break;
case (0x14 << 3) | 4: /* 0:14:4 PCI */
break;
case (0x14 << 3) | 5: /* 0:14:5 OHCI-USB4 */
/* call CIMX entry after last device enable */
sb_Before_Pci_Init();
break;
default:
break;
}
}
/**
* @brief SB Cimx entry point sbBeforePciInit wrapper
*/
static void sb800_enable(device_t dev)
{
struct southbridge_amd_cimx_sb800_config *sb_chip =
(struct southbridge_amd_cimx_sb800_config *)(dev->chip_info);
printk(BIOS_DEBUG, "sb800_enable() ");
switch (dev->path.pci.devfn) {
case (0x11 << 3) | 0: /* 0:11.0 SATA */
/* the first sb800 device */
switch (GPP_CFGMODE) { /* config the GPP PCIe ports */
case GPP_CFGMODE_X2200:
abcfg_reg(0xc0, 0x01FF, 0x032); /* x2 Port_0, x2 Port_1 */
break;
case GPP_CFGMODE_X2110:
abcfg_reg(0xc0, 0x01FF, 0x073); /* x2 Port_0, x1 Port_1&2 */
break;
case GPP_CFGMODE_X1111:
abcfg_reg(0xc0, 0x01FF, 0x0F4); /* x1 Port_0&1&2&3 */
break;
case GPP_CFGMODE_X4000:
default:
abcfg_reg(0xc0, 0x01FF, 0x010); /* x4 Port_0 */
break;
}
sb800_cimx_config(sb_config);
if (dev->enabled) {
sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_ENABLED;
if (1 == sb_chip->boot_switch_sata_ide)
sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary.
else if (0 == sb_chip->boot_switch_sata_ide)
sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary.
} else {
sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_DISABLED;
}
break;
case (0x14 << 3) | 0: /* 0:14:0 SMBUS */
printk(BIOS_INFO, "sm_init().\n");
clear_ioapic(IO_APIC_ADDR);
#if CONFIG_CPU_AMD_AGESA
/* Assign the ioapic ID the next available number after the processor core local APIC IDs */
setup_ioapic(IO_APIC_ADDR, CONFIG_MAX_CPUS);
#else
/* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */
#if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS < 16)
/* Assign the ioapic ID the next available number after the processor core local APIC IDs */
setup_ioapic(IO_APIC_ADDR, CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS);
#elif (CONFIG_APIC_ID_OFFSET > 0)
/* Assign the ioapic ID the value 0. Processor APIC IDs follow. */
setup_ioapic(IO_APIC_ADDR, 0);
#else
#error "The processor APIC IDs must be lifted to make room for the I/O APIC ID"
#endif
#endif
break;
case (0x14 << 3) | 1: /* 0:14:1 IDE */
break;
case (0x14 << 3) | 2: /* 0:14:2 HDA */
if (dev->enabled) {
if (AZALIA_DISABLE == sb_config->AzaliaController) {
sb_config->AzaliaController = AZALIA_AUTO;
}
printk(BIOS_DEBUG, "hda enabled\n");
} else {
sb_config->AzaliaController = AZALIA_DISABLE;
printk(BIOS_DEBUG, "hda disabled\n");
}
break;
case (0x14 << 3) | 3: /* 0:14:3 LPC */
/* Initialize the fans */
#if CONFIG_SB800_IMC_FAN_CONTROL
init_sb800_IMC_fans(dev);
#elif CONFIG_SB800_MANUAL_FAN_CONTROL
init_sb800_MANUAL_fans(dev);
#endif
break;
case (0x14 << 3) | 4: /* 0:14:4 PCI */
break;
case (0x14 << 3) | 6: /* 0:14:6 GEC */
if (dev->enabled) {
sb_config->GecConfig = 0;
printk(BIOS_DEBUG, "gec enabled\n");
} else {
sb_config->GecConfig = 1;
printk(BIOS_DEBUG, "gec disabled\n");
}
break;
case (0x15 << 3) | 0: /* 0:15:0 PCIe PortA */
{
device_t device;
for (device = dev; device; device = device->next) {
if (dev->path.type != DEVICE_PATH_PCI) continue;
if ((device->path.pci.devfn & ~7) != PCI_DEVFN(0x15,0)) break;
sb_config->PORTCONFIG[device->path.pci.devfn & 3].PortCfg.PortPresent = device->enabled;
}
/*
* GPP_CFGMODE_X4000: PortA Lanes[3:0]
* GPP_CFGMODE_X2200: PortA Lanes[1:0], PortB Lanes[3:2]
* GPP_CFGMODE_X2110: PortA Lanes[1:0], PortB Lane2, PortC Lane3
* GPP_CFGMODE_X1111: PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3
*/
sb_config->GppLinkConfig = sb_chip->gpp_configuration;
}
break;
case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */
sb_config->USBMODE.UsbMode.Ohci1 = dev->enabled;
break;
case (0x12 << 3) | 2: /* 0:12:2 EHCI-USB1 */
sb_config->USBMODE.UsbMode.Ehci1 = dev->enabled;
break;
case (0x13 << 3) | 0: /* 0:13:0 OHCI-USB2 */
sb_config->USBMODE.UsbMode.Ohci2 = dev->enabled;
break;
case (0x13 << 3) | 2: /* 0:13:2 EHCI-USB2 */
sb_config->USBMODE.UsbMode.Ehci2 = dev->enabled;
break;
case (0x14 << 3) | 5: /* 0:14:5 OHCI-USB4 */
sb_config->USBMODE.UsbMode.Ohci4 = dev->enabled;
break;
case (0x16 << 3) | 0: /* 0:16:0 OHCI-USB3 */
sb_config->USBMODE.UsbMode.Ohci3 = dev->enabled;
break;
case (0x16 << 3) | 2: /* 0:16:2 EHCI-USB3 */
sb_config->USBMODE.UsbMode.Ehci3 = dev->enabled;
/* call the CIMX entry at the last sb800 device,
* so make sure the mainboard devicetree is complete
*/
if (!acpi_is_wakeup_s3())
sb_Before_Pci_Init();
else
sb_Before_Pci_Restore_Init();
break;
default:
break;
}
}
/**
* @brief SB Cimx entry point sbBeforePciInit wrapper
*/
static void sb800_enable(device_t dev)
{
struct southbridge_amd_cimx_sb800_config *sb_chip =
(struct southbridge_amd_cimx_sb800_config *)(dev->chip_info);
switch (dev->path.pci.devfn) {
case (0x11 << 3) | 0: /* 0:11.0 SATA */
if (dev->enabled) {
sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_ENABLED;
if (1 == sb_chip->boot_switch_sata_ide)
sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary.
else if (0 == sb_chip->boot_switch_sata_ide)
sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary.
} else {
sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_DISABLED;
}
break;
case (0x14 << 3) | 0: /* 0:14:0 SMBUS */
clear_ioapic(VIO_APIC_VADDR);
#if CONFIG_CPU_AMD_AGESA
/* Assign the ioapic ID the next available number after the processor core local APIC IDs */
setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS);
#else
/* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */
#if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS < 16)
/* Assign the ioapic ID the next available number after the processor core local APIC IDs */
setup_ioapic(VIO_APIC_VADDR,
CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS);
#elif (CONFIG_APIC_ID_OFFSET > 0)
/* Assign the ioapic ID the value 0. Processor APIC IDs follow. */
setup_ioapic(VIO_APIC_VADDR, 0);
#else
#error "The processor APIC IDs must be lifted to make room for the I/O APIC ID"
#endif
#endif
break;
case (0x14 << 3) | 1: /* 0:14:1 IDE */
break;
case (0x14 << 3) | 2: /* 0:14:2 HDA */
if (dev->enabled) {
if (AZALIA_DISABLE == sb_config->AzaliaController) {
sb_config->AzaliaController = AZALIA_AUTO;
}
} else {
sb_config->AzaliaController = AZALIA_DISABLE;
}
break;
case (0x14 << 3) | 3: /* 0:14:3 LPC */
/* Initialize the fans */
#if CONFIG_SB800_IMC_FAN_CONTROL
init_sb800_IMC_fans(dev);
#elif CONFIG_SB800_MANUAL_FAN_CONTROL
init_sb800_MANUAL_fans(dev);
#endif
break;
case (0x14 << 3) | 4: /* 0:14:4 PCI */
/* PcibConfig [PM_Reg: EAh], PCIDisable [Bit0]
* 'PCIDisable' set to 0 to enable P2P bridge.
* 'PCIDisable' set to 1 to disable P2P bridge and enable PCI interface pins
* to function as GPIO {GPIO 35:0}.
*/
if (!sb_chip->disconnect_pcib && dev->enabled)
RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 0);
else
RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, BIT0);
break;
case (0x14 << 3) | 6: /* 0:14:6 GEC */
if (dev->enabled) {
sb_config->GecConfig = 0;
} else {
sb_config->GecConfig = 1;
}
break;
case (0x15 << 3) | 0: /* 0:15:0 PCIe PortA */
{
device_t device;
for (device = dev; device; device = device->next) {
if (dev->path.type != DEVICE_PATH_PCI) continue;
if ((device->path.pci.devfn & ~7) != PCI_DEVFN(0x15,0)) break;
sb_config->PORTCONFIG[device->path.pci.devfn & 3].PortCfg.PortPresent = device->enabled;
}
/*
* GPP_CFGMODE_X4000: PortA Lanes[3:0]
* GPP_CFGMODE_X2200: PortA Lanes[1:0], PortB Lanes[3:2]
* GPP_CFGMODE_X2110: PortA Lanes[1:0], PortB Lane2, PortC Lane3
* GPP_CFGMODE_X1111: PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3
*/
sb_config->GppLinkConfig = sb_chip->gpp_configuration;
}
break;
case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */
sb_config->USBMODE.UsbMode.Ohci1 = dev->enabled;
break;
case (0x12 << 3) | 2: /* 0:12:2 EHCI-USB1 */
sb_config->USBMODE.UsbMode.Ehci1 = dev->enabled;
break;
case (0x13 << 3) | 0: /* 0:13:0 OHCI-USB2 */
sb_config->USBMODE.UsbMode.Ohci2 = dev->enabled;
break;
case (0x13 << 3) | 2: /* 0:13:2 EHCI-USB2 */
sb_config->USBMODE.UsbMode.Ehci2 = dev->enabled;
break;
case (0x14 << 3) | 5: /* 0:14:5 OHCI-USB4 */
sb_config->USBMODE.UsbMode.Ohci4 = dev->enabled;
break;
case (0x16 << 3) | 0: /* 0:16:0 OHCI-USB3 */
sb_config->USBMODE.UsbMode.Ohci3 = dev->enabled;
break;
case (0x16 << 3) | 2: /* 0:16:2 EHCI-USB3 */
sb_config->USBMODE.UsbMode.Ehci3 = dev->enabled;
/* call the CIMX entry at the last sb800 device,
* so make sure the mainboard devicetree is complete
*/
if (!acpi_is_wakeup_s3())
sb_Before_Pci_Init();
else
sb_Before_Pci_Restore_Init();
break;
default:
break;
}
}
static void sm_init(device_t dev)
{
setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS);
}
/*
* SB700 enables all USB controllers by default in SMBUS Control.
* SB700 enables SATA by default in SMBUS Control.
*/
static void sm_init(device_t dev)
{
u8 byte;
u8 byte_old;
u8 rev;
u32 dword;
void *ioapic_base;
uint32_t power_state;
uint32_t enable_legacy_usb;
u32 nmi_option;
printk(BIOS_INFO, "sm_init().\n");
rev = get_sb700_revision(dev);
/* This works in a similar fashion to a memory resource, but without an enable bit */
ioapic_base = (void *)(pci_read_config32(dev, 0x74) & (0xffffffe0));
setup_ioapic(ioapic_base, 0); /* Don't rename IOAPIC ID. */
enable_legacy_usb = 1;
get_option(&enable_legacy_usb, "enable_legacy_usb");
/* 2.10 Interrupt Routing/Filtering */
byte = pci_read_config8(dev, 0x62);
if (enable_legacy_usb)
byte |= 0x3;
else
byte &= ~0x3;
pci_write_config8(dev, 0x62, byte);
byte = pci_read_config8(dev, 0x67);
if (enable_legacy_usb)
byte |= 0x1 << 7;
else
byte &= ~(0x1 << 7);
pci_write_config8(dev, 0x67, byte);
/* Delay back to back interrupts to the CPU. */
dword = pci_read_config16(dev, 0x64);
dword |= 1 << 13;
pci_write_config16(dev, 0x64, dword);
/* rrg:K8 INTR Enable (BIOS should set this bit after PIC initialization) */
/* rpr 2.1 Enabling Legacy Interrupt */
dword = pci_read_config8(dev, 0x62);
dword |= 1 << 2;
pci_write_config8(dev, 0x62, dword);
dword = pci_read_config32(dev, 0x78);
dword |= 1 << 9;
pci_write_config32(dev, 0x78, dword); /* enable 0xCD6 0xCD7 */
/* bit 10: MultiMediaTimerIrqEn */
dword = pci_read_config8(dev, 0x64);
dword |= 1 << 10;
pci_write_config8(dev, 0x64, dword);
/* enable serial irq */
byte = pci_read_config8(dev, 0x69);
byte |= 1 << 7; /* enable serial irq function */
byte &= ~(0xF << 2);
byte |= 4 << 2; /* set NumSerIrqBits=4 */
pci_write_config8(dev, 0x69, byte);
/* Sx State Settings
* Note: These 2 registers need to be set correctly for the S-state
* to work properly. Otherwise the system may hang during resume
* from the S-state.
*/
/*Use 8us clock for delays in the S-state resume timing sequence.*/
byte = pm_ioread(0x65);
byte &= ~(1 << 7);
pm_iowrite(0x65, byte);
/* Delay the APIC interrupt to the CPU until the system has fully resumed from the S-state. */
byte = pm_ioread(0x68);
byte |= 1 << 2;
pm_iowrite(0x68, byte);
/* IRQ0From8254 */
byte = pci_read_config8(dev, 0x41);
byte &= ~(1 << 7);
pci_write_config8(dev, 0x41, byte);
byte = pm_ioread(0x61);
if (IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX))
byte &= ~(1 << 1); /* Clear for non-K8 CPUs */
else
byte |= 1 << 1; /* Set to enable NB/SB handshake during IOAPIC interrupt for AMD K8/K7 */
pm_iowrite(0x61, byte);
/* disable SMI */
byte = pm_ioread(0x53);
byte |= 1 << 3;
pm_iowrite(0x53, byte);
/* power after power fail */
power_state = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
get_option(&power_state, "power_on_after_fail");
if (power_state > 2) {
printk(BIOS_WARNING, "Invalid power_on_after_fail setting, using default\n");
power_state = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
}
byte = pm_ioread(0x74);
byte &= ~0x03;
if (power_state == POWER_MODE_OFF)
byte |= 0x0;
else if (power_state == POWER_MODE_ON)
byte |= 0x1;
else if (power_state == POWER_MODE_LAST)
byte |= 0x2;
byte |= 1 << 2;
pm_iowrite(0x74, byte);
printk(BIOS_INFO, "set power \"%s\" after power fail\n", power_mode_names[power_state]);
byte = pm_ioread(0x68);
byte &= ~(1 << 1);
/* 2.7 */
byte |= 1 << 2;
pm_iowrite(0x68, byte);
/* 2.7 */
byte = pm_ioread(0x65);
byte &= ~(1 << 7);
pm_iowrite(0x65, byte);
/* 2.16 */
byte = pm_ioread(0x55);
byte |= 1 << 5;
pm_iowrite(0x55, byte);
byte = pm_ioread(0xD7);
byte |= 1 << 6 | 1 << 1;
pm_iowrite(0xD7, byte);
/* 2.15 */
byte = pm_ioread(0x42);
byte &= ~(1 << 2);
pm_iowrite(0x42, byte);
/* Set up NMI on errors */
byte = inb(0x70); /* RTC70 */
byte_old = byte;
nmi_option = NMI_OFF;
get_option(&nmi_option, "nmi");
if (nmi_option) {
byte &= ~(1 << 7); /* set NMI */
printk(BIOS_INFO, "++++++++++set NMI+++++\n");
} else {
byte |= (1 << 7); /* Can not mask NMI from PCI-E and NMI_NOW */
printk(BIOS_INFO, "++++++++++no set NMI+++++\n");
}
byte &= ~(1 << 7);
if (byte != byte_old) {
outb(byte, 0x70);
}
/*rpr v2.13 2.22 SMBUS PCI Config */
byte = pci_read_config8(dev, 0xE1);
if ((REV_SB700_A11 == rev) || REV_SB700_A12 == rev) {
byte |= 1 << 0;
}
/*Set bit2 to 1, enable Io port 60h read/write SMi trapping and
*Io port 64h write Smi trapping. conflict with ps2 keyboard
*/
//byte |= 1 << 2 | 1 << 3 | 1 << 4;
byte |= 1 << 3 | 1 << 4;
pci_write_config8(dev, 0xE1, byte);
/* 2.5 Enabling Non-Posted Memory Write */
axindxc_reg(0x10, 1 << 9, 1 << 9);
/* 2.11 IO Trap Settings */
abcfg_reg(0x10090, 1 << 16, 1 << 16);
/* ab index */
pci_write_config32(dev, 0xF0, AB_INDX);
/* Initialize the real time clock */
cmos_init(0);
/* 4.3 Enabling Upstream DMA Access */
axcfg_reg(0x04, 1 << 2, 1 << 2);
/* 4.4 Enabling IDE/PCIB Prefetch for Performance Enhancement */
abcfg_reg(0x10060, 9 << 17, 9 << 17);
abcfg_reg(0x10064, 9 << 17, 9 << 17);
/* 4.5 Enabling OHCI Prefetch for Performance Enhancement, A12 */
abcfg_reg(0x80, 1 << 0, 1<< 0);
/* 4.6 B-Link Client's Credit Variable Settings for the Downstream Arbitration Equation */
/* 4.7 Enabling Additional Address Bits Checking in Downstream */
/* 4.16 IO write and SMI ordering enhancement*/
abcfg_reg(0x9c, 3 << 0, 3 << 0);
if (REV_SB700_A12 == rev) {
abcfg_reg(0x9c, 1 << 8, 1 << 8);
} else if (rev >= REV_SB700_A14) {
abcfg_reg(0x9c, 1 << 8, 0 << 8);
}
if (REV_SB700_A15 == rev) {
abcfg_reg(0x90, 1 << 21, 1 << 21);
abcfg_reg(0x9c, 1 << 5 | 1 << 9 | 1 << 15, 1 << 5 | 1 << 9 | 1 << 15);
}
/* 4.8 Set B-Link Prefetch Mode */
abcfg_reg(0x80, 3 << 17, 3 << 17);
/* 4.9 Enabling Detection of Upstream Interrupts */
abcfg_reg(0x94, 1 << 20 | 0x7FFFF, 1 << 20 | 0x00FEE);
/* 4.10: Enabling Downstream Posted Transactions to Pass Non-Posted
* Transactions for the K8 Platform (for All Revisions) */
abcfg_reg(0x10090, 1 << 8, 1 << 8);
/* Set ACPI Software clock Throttling Period to 244 us*/
byte = pm_ioread(0x68);
byte &= ~(3 << 6);
byte |= (2 << 6); /* 244us */
pm_iowrite(0x68, byte);
if (REV_SB700_A15 == rev) {
u16 word;
/* rpr v2.13 4.18 Enabling Posted Pass Non-Posted Downstream */
axindxc_reg(0x02, 1 << 9, 1 << 9);
abcfg_reg(0x9C, 0x00007CC0, 0x00007CC0);
abcfg_reg(0x1009C, 0x00000030, 0x00000030);
abcfg_reg(0x10090, 0x00001E00, 0x00001E00);
/* rpr v2.13 4.19 Enabling Posted Pass Non-Posted Upstream */
abcfg_reg(0x58, 0x0000F800, 0x0000E800);
/* rpr v2.13 4.20 64 bit Non-Posted Memory Write Support */
axindxc_reg(0x02, 1 << 10, 1 << 10);
/* rpr v2.13 2.38 Unconditional Shutdown */
byte = pci_read_config8(dev, 0x43);
byte &= ~(1 << 3);
pci_write_config8(dev, 0x43, byte);
word = pci_read_config16(dev, 0x38);
word |= 1 << 12;
pci_write_config16(dev, 0x38, word);
byte |= 1 << 3;
pci_write_config8(dev, 0x43, byte);
/* Enable southbridge MMIO decode */
dword = pci_read_config32(dev, SB_MMIO_CFG_REG);
dword &= ~(0xffffff << 8);
dword |= SB_MMIO_BASE_ADDRESS;
dword |= 0x1;
pci_write_config32(dev, SB_MMIO_CFG_REG, dword);
}
byte = pci_read_config8(dev, 0xAE);
if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID))
byte |= 1 << 4;
byte |= 1 << 5; /* ACPI_DISABLE_TIMER_IRQ_ENHANCEMENT_FOR_8254_TIMER */
byte |= 1 << 6; /* Enable arbiter between APIC and PIC interrupts */
pci_write_config8(dev, 0xAE, byte);
/* 4.11:Programming Cycle Delay for AB and BIF Clock Gating */
/* 4.12: Enabling AB and BIF Clock Gating */
abcfg_reg(0x10054, 0xFFFF0000, 0x1040000);
abcfg_reg(0x54, 0xFF << 16, 4 << 16);
abcfg_reg(0x54, 1 << 24, 0 << 24);
abcfg_reg(0x98, 0x0000FF00, 0x00004700);
/* 4.13:Enabling AB Int_Arbiter Enhancement (for All Revisions) */
abcfg_reg(0x10054, 0x0000FFFF, 0x07FF);
/* 4.14:Enabling Requester ID for upstream traffic. */
abcfg_reg(0x98, 1 << 16, 1 << 16);
/* 9.2: Enabling IDE Data Bus DD7 Pull Down Resistor */
byte = pm2_ioread(0xE5);
byte |= 1 << 2;
pm2_iowrite(0xE5, byte);
/* Enable IDE controller. */
byte = pm_ioread(0x59);
byte &= ~(1 << 1);
pm_iowrite(0x59, byte);
/* Enable SCI as irq9. */
outb(0x4, 0xC00);
outb(0x9, 0xC01);
printk(BIOS_INFO, "sm_init() end\n");
/* Enable NbSb virtual channel */
axcfg_reg(0x114, 0x3f << 1, 0 << 1);
axcfg_reg(0x120, 0x7f << 1, 0x7f << 1);
axcfg_reg(0x120, 7 << 24, 1 << 24);
axcfg_reg(0x120, 1 << 31, 1 << 31);
abcfg_reg(0x50, 1 << 3, 1 << 3);
}
/**
* @brief SB Cimx entry point sbBeforePciInit wrapper
*/
static void sb800_enable(device_t dev)
{
struct southbridge_amd_cimx_wrapper_sb800_config *sb_chip =
(struct southbridge_amd_cimx_wrapper_sb800_config *)(dev->chip_info);
sb800_cimx_config(sb_config);
printk(BIOS_DEBUG, "sb800_enable() ");
/* Config SouthBridge SMBUS/ACPI/IDE/LPC/PCIB.*/
commonInitEarlyBoot(sb_config);
commonInitEarlyPost(sb_config);
switch (dev->path.pci.devfn) {
case (0x11 << 3) | 0: /* 0:11.0 SATA */
if (dev->enabled) {
sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_ENABLED;
if (1 == sb_chip->boot_switch_sata_ide)
sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary.
else if (0 == sb_chip->boot_switch_sata_ide)
sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary.
} else {
sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_DISABLED;
}
sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY
break;
case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */
case (0x12 << 3) | 2: /* 0:12:2 EHCI-USB1 */
case (0x13 << 3) | 0: /* 0:13:0 OHCI-USB2 */
case (0x13 << 3) | 2: /* 0:13:2 EHCI-USB2 */
case (0x14 << 3) | 5: /* 0:14:5 OHCI-USB4 */
case (0x16 << 3) | 0: /* 0:16:0 OHCI-USB3 */
case (0x16 << 3) | 2: /* 0:16:2 EHCI-USB3 */
usbInitBeforePciEnum(sb_config); // USB POST TIME Only
break;
case (0x14 << 3) | 0: /* 0:14:0 SMBUS */
{
u32 ioapic_base;
printk(BIOS_INFO, "sm_init().\n");
ioapic_base = IO_APIC_ADDR;
clear_ioapic(ioapic_base);
/* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */
#if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS < 16)
/* Assign the ioapic ID the next available number after the processor core local APIC IDs */
setup_ioapic(ioapic_base, CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS);
#elif (CONFIG_APIC_ID_OFFSET > 0)
/* Assign the ioapic ID the value 0. Processor APIC IDs follow. */
setup_ioapic(ioapic_base, 0);
#else
#error "The processor APIC IDs must be lifted to make room for the I/O APIC ID"
#endif
}
break;
case (0x14 << 3) | 1: /* 0:14:1 IDE */
if (dev->enabled) {
sb_config->SATAMODE.SataMode.SataIdeCombinedMode = CIMX_OPTION_ENABLED;
} else {
sb_config->SATAMODE.SataMode.SataIdeCombinedMode = CIMX_OPTION_DISABLED;
}
sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY
break;
case (0x14 << 3) | 2: /* 0:14:2 HDA */
if (dev->enabled) {
if (AZALIA_DISABLE == sb_config->AzaliaController) {
sb_config->AzaliaController = AZALIA_AUTO;
}
printk(BIOS_DEBUG, "hda enabled\n");
} else {
sb_config->AzaliaController = AZALIA_DISABLE;
printk(BIOS_DEBUG, "hda disabled\n");
}
azaliaInitBeforePciEnum(sb_config); // Detect and configure High Definition Audio
break;
case (0x14 << 3) | 3: /* 0:14:3 LPC */
break;
case (0x14 << 3) | 4: /* 0:14:4 PCI */
break;
case (0x14 << 3) | 6: /* 0:14:6 GEC */
if (dev->enabled) {
sb_config->GecConfig = 0;
printk(BIOS_DEBUG, "gec enabled\n");
} else {
sb_config->GecConfig = 1;
printk(BIOS_DEBUG, "gec disabled\n");
}
gecInitBeforePciEnum(sb_config); // Init GEC
break;
case (0x15 << 3) | 0: /* 0:15:0 PCIe PortA */
sb_config->PORTCONFIG[0].PortCfg.PortPresent = dev->enabled;
return;
case (0x15 << 3) | 1: /* 0:15:1 PCIe PortB */
sb_config->PORTCONFIG[1].PortCfg.PortPresent = dev->enabled;
return;
case (0x15 << 3) | 2: /* 0:15:2 PCIe PortC */
sb_config->PORTCONFIG[2].PortCfg.PortPresent = dev->enabled;
return;
case (0x15 << 3) | 3: /* 0:15:3 PCIe PortD */
sb_config->PORTCONFIG[3].PortCfg.PortPresent = dev->enabled;
/*
* GPP_CFGMODE_X4000: PortA Lanes[3:0]
* GPP_CFGMODE_X2200: PortA Lanes[1:0], PortB Lanes[3:2]
* GPP_CFGMODE_X2110: PortA Lanes[1:0], PortB Lane2, PortC Lane3
* GPP_CFGMODE_X1111: PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3
*/
if (sb_config->GppLinkConfig != sb_chip->gpp_configuration) {
sb_config->GppLinkConfig = sb_chip->gpp_configuration;
}
sbPcieGppEarlyInit(sb_config);
break;
default:
break;
}
/* Special setting ABCFG registers before PCI emulation. */
abSpecialSetBeforePciEnum(sb_config);
usbDesertPll(sb_config);
//sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT;
//AmdSbDispatcher(sb_config);
}
