int board_early_init_f(void) { setup_iomux_uart(); #if defined(CONFIG_VIDEO_IPUV3) setup_display(); #endif return 0; }
int board_early_init_f(void) { setup_iomux_uart(); setup_iomux_fec(); #ifdef CONFIG_USB_EHCI_MX5 setup_usb_h1(); #endif return 0; }
int board_early_init_f(void) { init_drive_strength(); setup_iomux_uart(); setup_iomux_spi(); setup_iomux_led(); return 0; }
int board_early_init_f(void) { setup_iomux_uart(); #ifdef CONFIG_SYS_USE_SPINOR setup_spinor(); #endif return 0; }
int board_early_init_f(void) { setup_iomux_uart(); setup_iomux_gpio(); gpio_direction_output(SOFT_RESET_GPIO, 1); gpio_direction_output(SD2_DRIVER_ENABLE, 1); setup_display(); set_gpr_register(); return 0; }
int board_early_init_f(void) { setup_iomux_uart(); #ifdef CONFIG_SYS_I2C_MXC setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); #endif return 0; }
int board_early_init_f(void) { clock_init(); mscm_init(); setup_iomux_uart(); setup_iomux_enet(); setup_iomux_i2c(); return 0; }
int board_early_init_f(void) { ccgr_init(); gpr_init(); setup_iomux_uart(); setup_iomux_spi(); setup_iomux_i2c(); setup_iomux_features(); return 0; }
int board_early_init_f(void) { setup_iomux_uart(); imx_iomux_v3_setup_multiple_pads(init_pads, ARRAY_SIZE(init_pads)); setup_buttons(); #if defined(CONFIG_VIDEO_IPUV3) setup_display(); #endif return 0; }
int board_early_init_f(void) { setup_iomux_uart(); setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); imx_iomux_v3_setup_multiple_pads(usb_otg1_pads, ARRAY_SIZE(usb_otg1_pads)); imx_iomux_v3_setup_multiple_pads(usb_otg2_pads, ARRAY_SIZE(usb_otg2_pads)); return 0; }
int board_early_init_f(void) { setup_iomux_uart(); #ifdef CONFIG_CMD_SATA setup_sata(); #endif #ifdef CONFIG_USB_EHCI_MX6 setup_usb(); #endif return 0; }
int board_early_init_f(void) { setup_iomux_uart(); #ifdef CONFIG_SYS_USE_NAND setup_gpmi_nand(); #endif #if defined(CONFIG_VIDEO_IPUV3) setup_display(); #endif return 0; }
int board_early_init_f(void) { #ifdef CONFIG_MXC_RDC imx_rdc_setup_peripherals(shared_resources, ARRAY_SIZE(shared_resources)); #endif #ifdef CONFIG_SYS_AUXCORE_FASTUP arch_auxiliary_core_up(0, CONFIG_SYS_AUXCORE_BOOTDATA); #endif setup_iomux_uart(); return 0; }
int board_init(void) { system_rev = get_cpu_rev(); gd->bd->bi_arch_number = MACH_TYPE_MX51_BABBAGE; /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; setup_iomux_uart(); setup_iomux_fec(); return 0; }
int board_early_init_f(void) { setup_iomux_uart(); #ifdef CONFIG_NAND_MXS setup_gpmi_nand(); #endif #ifdef CONFIG_MTD_NOR_FLASH eim_clk_setup(); #endif return 0; }
int board_early_init_f(void) { setup_iomux_uart(); #if defined(CONFIG_VIDEO_IPUV3) setup_display(); #endif #ifdef CONFIG_CMD_SATA /* Only mx6q wandboard has SATA */ if (is_cpu_type(MXC_CPU_MX6Q)) setup_sata(); #endif return 0; }
int board_early_init_f(void) { int ret = 0; setup_iomux_uart(); #ifdef CONFIG_VIDEO_IPUV3 ret = setup_display(); #endif #ifdef CONFIG_USB_EHCI_MX6 setup_usb(); #endif return ret; }
int board_early_init_f(void) { setup_iomux_uart(); setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */ imx_iomux_v3_setup_multiple_pads(peri_3v3_pads, ARRAY_SIZE(peri_3v3_pads)); /* Active high for ncp692 */ gpio_direction_output(IMX_GPIO_NR(4, 16) , 1); return 0; }
int board_early_init_f(void) { setup_iomux_uart(); /* Disable wl1271 */ gpio_direction_input(WL12XX_WL_IRQ_GP); gpio_direction_output(WL12XX_WL_ENABLE_GP, 0); gpio_direction_output(WL12XX_BT_ENABLE_GP, 0); imx_iomux_v3_setup_multiple_pads(wl12xx_pads, ARRAY_SIZE(wl12xx_pads)); #if defined(CONFIG_VIDEO_IPUV3) setup_display(); #endif return 0; }
int board_early_init_f(void) { setup_iomux_uart(); #if defined(CONFIG_VIDEO_IPUV3) setup_display(); #endif #ifdef CONFIG_SYS_USE_SPINOR setup_spinor(); #endif #ifdef CONFIG_CMD_SATA setup_sata(); #endif return 0; }
int board_early_init_f(void) { setup_iomux_uart(); set_gpios(gpios_out_high, ARRAY_SIZE(gpios_out_high), 1); set_gpios(gpios_out_low, ARRAY_SIZE(gpios_out_low), 0); gpio_direction_input(WL12XX_WL_IRQ_GP); imx_iomux_v3_setup_multiple_pads(wl12xx_pads, ARRAY_SIZE(wl12xx_pads)); imx_iomux_v3_setup_multiple_pads(init_pads, ARRAY_SIZE(init_pads)); setup_buttons(); #if defined(CONFIG_VIDEO_IPUV3) setup_display(); #endif return 0; }
int board_early_init_f(void) { imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads)); setup_iomux_uart(); #if defined(CONFIG_VIDEO_IPUV3) if (IS_ENABLED(CONFIG_TARGET_GE_B850V3)) /* Set LDB clock to Video PLL */ select_ldb_di_clock_source(MXC_PLL5_CLK); else /* Set LDB clock to USB PLL */ select_ldb_di_clock_source(MXC_PLL3_SW_CLK); #endif return 0; }
int board_early_init_f(void) { setup_iomux_uart(); setup_iomux_fec(); setup_iomux_i2c(); setup_iomux_nand(); setup_iomux_video(); m53_set_clock(); mxc_set_sata_internal_clock(); /* NAND clock @ 33MHz */ m53_set_nand(); return 0; }
int board_early_init_f(void) { setup_iomux_uart(); /* Disable wl1271 For Nitrogen6w */ gpio_direction_input(WL12XX_WL_IRQ_GP); gpio_direction_output(WL12XX_WL_ENABLE_GP, 0); gpio_direction_output(WL12XX_BT_ENABLE_GP, 0); gpio_direction_output(GP_USB_OTG_PWR, 0); /* OTG power off */ imx_iomux_v3_setup_multiple_pads(wl12xx_pads, ARRAY_SIZE(wl12xx_pads)); setup_buttons(); #if defined(CONFIG_VIDEO_IPUV3) setup_display(); #endif return 0; }
int board_early_init_f(void) { setup_iomux_uart(); imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads)); /* Disable WiFi/BT */ gpio_direction_input(WIFI_WL_IRQ_GP); gpio_direction_output(WIFI_WL_ENABLE_GP, 0); gpio_direction_output(WIFI_BT_ENABLE_GP, 0); gpio_direction_output(WIFI_BT_REG_ON, 0); imx_iomux_v3_setup_multiple_pads(wifi_pads, ARRAY_SIZE(wifi_pads)); #if defined(CONFIG_VIDEO_IPUV3) setup_display(); #endif return 0; }
int board_early_init_f(void) { u32 cputype = cpu_type(get_cpu_rev()); switch (cputype) { case MXC_CPU_MX6SOLO: board_type = BOARD_IS_RIOTBOARD; break; case MXC_CPU_MX6D: board_type = BOARD_IS_MARSBOARD; break; } setup_iomux_uart(); if (board_type == BOARD_IS_RIOTBOARD) imx_iomux_v3_setup_multiple_pads( tft_pads_riot, ARRAY_SIZE(tft_pads_riot)); else if (board_type == BOARD_IS_MARSBOARD) imx_iomux_v3_setup_multiple_pads( tft_pads_mars, ARRAY_SIZE(tft_pads_mars)); #if defined(CONFIG_VIDEO_IPUV3) /* power ON LCD */ gpio_direction_output(IMX_GPIO_NR(1, 29) , 1); /* touch interrupt is an input */ gpio_direction_input(IMX_GPIO_NR(6, 14)); /* power ON backlight */ gpio_direction_output(IMX_GPIO_NR(6, 15) , 1); /* set backlight level to off */ if (board_type == BOARD_IS_RIOTBOARD) gpio_direction_output(IMX_GPIO_NR(1, 18) , 0); else if (board_type == BOARD_IS_MARSBOARD) gpio_direction_output(IMX_GPIO_NR(2, 10) , 0); setup_display(); #endif return 0; }
void board_init_f(ulong dummy) { /* setup AIPS and disable watchdog */ arch_cpu_init(); ccgr_init(); gpr_init(); /* setup GP timer */ timer_init(); setup_iomux_boardid(); setup_iomux_gpio(); setup_iomux_enet(); setup_iomux_sd(); setup_iomux_spi(); setup_iomux_uart(); setup_iomux_usb(); /* UART clocks enabled and gd valid - init serial console */ preloader_console_init(); /* Start the DDR DRAM */ if (is_mx6dq()) mx6dq_dram_iocfg(dhcom_mem_ddr.width, &dhcom6dq_ddr_ioregs, &dhcom6dq_grp_ioregs); else mx6sdl_dram_iocfg(dhcom_mem_ddr.width, &dhcom6sdl_ddr_ioregs, &dhcom6sdl_grp_ioregs); mx6_dram_cfg(&dhcom_ddr_info, &dhcom_mmdc_calib, &dhcom_mem_ddr); /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); /* load/boot image from boot device */ board_init_r(NULL, 0); }
int board_early_init_f(void) { setup_iomux_uart(); return 0; }
int dram_init(void) { struct ddrmc_lvl_info lvl = { .wrlvl_reg_en = 1, .wrlvl_dl_0 = 0, .wrlvl_dl_1 = 0, .rdlvl_gt_reg_en = 1, .rdlvl_gt_dl_0 = 4, .rdlvl_gt_dl_1 = 4, .rdlvl_reg_en = 1, .rdlvl_dl_0 = 0, .rdlvl_dl_1 = 0, }; static const struct ddr3_jedec_timings timings = { .tinit = 5, .trst_pwron = 80000, .cke_inactive = 200000, .wrlat = 5, .caslat_lin = 12, .trc = 21, .trrd = 4, .tccd = 4, .tfaw = 20, .trp = 6, .twtr = 4, .tras_min = 15, .tmrd = 4, .trtp = 4, .tras_max = 28080, .tmod = 12, .tckesr = 4, .tcke = 3, .trcd_int = 6, .tdal = 12, .tdll = 512, .trp_ab = 6, .tref = 3120, .trfc = 44, .tpdex = 3, .txpdll = 10, .txsnr = 48, .txsr = 468, .cksrx = 5, .cksre = 5, .zqcl = 256, .zqinit = 512, .zqcs = 64, .ref_per_zq = 64, .aprebit = 10, .wlmrd = 40, .wldqsen = 25, }; ddrmc_setup_iomux(); ddrmc_ctrl_init_ddr3(&timings, &lvl, 1, 3); gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); return 0; } static void setup_iomux_uart(void) { static const iomux_v3_cfg_t uart1_pads[] = { NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, UART_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, UART_PAD_CTRL), }; imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); } static void setup_iomux_enet(void) { static const iomux_v3_cfg_t enet0_pads[] = { NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKIN, ENET_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTC1__RMII0_MDIO, ENET_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTC0__RMII0_MDC, ENET_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTC2__RMII0_CRS_DV, ENET_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTC3__RMII0_RD1, ENET_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTC4__RMII0_RD0, ENET_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTC5__RMII0_RXER, ENET_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTC6__RMII0_TD1, ENET_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTC7__RMII0_TD0, ENET_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTC8__RMII0_TXEN, ENET_PAD_CTRL), }; imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads)); } static void setup_iomux_i2c(void) { static const iomux_v3_cfg_t i2c0_pads[] = { VF610_PAD_PTB14__I2C0_SCL, VF610_PAD_PTB15__I2C0_SDA, }; imx_iomux_v3_setup_multiple_pads(i2c0_pads, ARRAY_SIZE(i2c0_pads)); } #ifdef CONFIG_NAND_VF610_NFC static void setup_iomux_nfc(void) { static const iomux_v3_cfg_t nfc_pads[] = { VF610_PAD_PTD31__NF_IO15, VF610_PAD_PTD30__NF_IO14, VF610_PAD_PTD29__NF_IO13, VF610_PAD_PTD28__NF_IO12, VF610_PAD_PTD27__NF_IO11, VF610_PAD_PTD26__NF_IO10, VF610_PAD_PTD25__NF_IO9, VF610_PAD_PTD24__NF_IO8, VF610_PAD_PTD23__NF_IO7, VF610_PAD_PTD22__NF_IO6, VF610_PAD_PTD21__NF_IO5, VF610_PAD_PTD20__NF_IO4, VF610_PAD_PTD19__NF_IO3, VF610_PAD_PTD18__NF_IO2, VF610_PAD_PTD17__NF_IO1, VF610_PAD_PTD16__NF_IO0, VF610_PAD_PTB24__NF_WE_B, VF610_PAD_PTB25__NF_CE0_B, VF610_PAD_PTB27__NF_RE_B, VF610_PAD_PTC26__NF_RB_B, VF610_PAD_PTC27__NF_ALE, VF610_PAD_PTC28__NF_CLE }; imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads)); } #endif static void setup_iomux_qspi(void) { static const iomux_v3_cfg_t qspi0_pads[] = { VF610_PAD_PTD0__QSPI0_A_QSCK, VF610_PAD_PTD1__QSPI0_A_CS0, VF610_PAD_PTD2__QSPI0_A_DATA3, VF610_PAD_PTD3__QSPI0_A_DATA2, VF610_PAD_PTD4__QSPI0_A_DATA1, VF610_PAD_PTD5__QSPI0_A_DATA0, VF610_PAD_PTD7__QSPI0_B_QSCK, VF610_PAD_PTD8__QSPI0_B_CS0, VF610_PAD_PTD9__QSPI0_B_DATA3, VF610_PAD_PTD10__QSPI0_B_DATA2, VF610_PAD_PTD11__QSPI0_B_DATA1, VF610_PAD_PTD12__QSPI0_B_DATA0, }; imx_iomux_v3_setup_multiple_pads(qspi0_pads, ARRAY_SIZE(qspi0_pads)); } #ifdef CONFIG_FSL_ESDHC struct fsl_esdhc_cfg esdhc_cfg[1] = { {ESDHC1_BASE_ADDR}, }; int board_mmc_getcd(struct mmc *mmc) { /* eSDHC1 is always present */ return 1; } int board_mmc_init(bd_t *bis) { static const iomux_v3_cfg_t esdhc1_pads[] = { NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL), }; esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); imx_iomux_v3_setup_multiple_pads( esdhc1_pads, ARRAY_SIZE(esdhc1_pads)); return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); } #endif static void clock_init(void) { struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR; clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK, CCM_CCGR0_UART1_CTRL_MASK); clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK, CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK); clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK, CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK | CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK | CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK | CCM_CCGR2_QSPI0_CTRL_MASK); clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK, CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK); clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK, CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK | CCM_CCGR4_GPC_CTRL_MASK | CCM_CCGR4_I2C0_CTRL_MASK); clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK, CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK); clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK, CCM_CCGR7_SDHC1_CTRL_MASK); clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK, CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK); clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK, CCM_CCGR10_NFC_CTRL_MASK); clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN, ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT); clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN, ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT); clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK, CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5)); clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK, CCM_CCSR_PLL1_PFD_CLK_SEL(3) | CCM_CCSR_PLL2_PFD4_EN | CCM_CCSR_PLL2_PFD3_EN | CCM_CCSR_PLL2_PFD2_EN | CCM_CCSR_PLL2_PFD1_EN | CCM_CCSR_PLL1_PFD4_EN | CCM_CCSR_PLL1_PFD3_EN | CCM_CCSR_PLL1_PFD2_EN | CCM_CCSR_PLL1_PFD1_EN | CCM_CCSR_DDRC_CLK_SEL(1) | CCM_CCSR_FAST_CLK_SEL(1) | CCM_CCSR_SYS_CLK_SEL(4)); clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK, CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) | CCM_CACRR_ARM_CLK_DIV(0)); clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK, CCM_CSCMR1_ESDHC1_CLK_SEL(3) | CCM_CSCMR1_QSPI0_CLK_SEL(3) | CCM_CSCMR1_NFC_CLK_SEL(0)); clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK, CCM_CSCDR1_RMII_CLK_EN); clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK, CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) | CCM_CSCDR2_NFC_EN); clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK, CCM_CSCDR3_QSPI0_EN | CCM_CSCDR3_QSPI0_DIV(1) | CCM_CSCDR3_QSPI0_X2_DIV(1) | CCM_CSCDR3_QSPI0_X4_DIV(3) | CCM_CSCDR3_NFC_PRE_DIV(5)); clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK, CCM_CSCMR2_RMII_CLK_SEL(0)); } static void mscm_init(void) { struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR; int i; for (i = 0; i < MSCM_IRSPRC_NUM; i++) writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]); } int board_phy_config(struct phy_device *phydev) { if (phydev->drv->config) phydev->drv->config(phydev); return 0; } int board_early_init_f(void) { clock_init(); mscm_init(); setup_iomux_uart(); setup_iomux_enet(); setup_iomux_i2c(); setup_iomux_qspi(); #ifdef CONFIG_NAND_VF610_NFC setup_iomux_nfc(); #endif return 0; } int board_init(void) { struct scsc_reg *scsc = (struct scsc_reg *)SCSC_BASE_ADDR; /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; /* * Enable external 32K Oscillator * * The internal clock experiences significant drift * so we must use the external oscillator in order * to maintain correct time in the hwclock */ setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN); return 0; } int checkboard(void) { puts("Board: vf610twr\n"); return 0; }
int dram_init(void) { static const struct ddr3_jedec_timings pcm052_ddr_timings = { .tinit = 5, .trst_pwron = 80000, .cke_inactive = 200000, .wrlat = 5, .caslat_lin = 12, .trc = 6, .trrd = 4, .tccd = 4, .tbst_int_interval = 4, .tfaw = 18, .trp = 6, .twtr = 4, .tras_min = 15, .tmrd = 4, .trtp = 4, .tras_max = 14040, .tmod = 12, .tckesr = 4, .tcke = 3, .trcd_int = 6, .tras_lockout = 1, .tdal = 10, .bstlen = 3, .tdll = 512, .trp_ab = 6, .tref = 1542, .trfc = 64, .tref_int = 5, .tpdex = 3, .txpdll = 10, .txsnr = 68, .txsr = 506, .cksrx = 5, .cksre = 5, .freq_chg_en = 1, .zqcl = 256, .zqinit = 512, .zqcs = 64, .ref_per_zq = 64, .zqcs_rotate = 1, .aprebit = 10, .cmd_age_cnt = 255, .age_cnt = 255, .q_fullness = 0, .odt_rd_mapcs0 = 1, .odt_wr_mapcs0 = 1, .wlmrd = 40, .wldqsen = 25, }; static const iomux_v3_cfg_t pcm052_pads[] = { PCM052_VF610_PAD_DDR_A15__DDR_A_15, PCM052_VF610_PAD_DDR_A14__DDR_A_14, PCM052_VF610_PAD_DDR_A13__DDR_A_13, PCM052_VF610_PAD_DDR_A12__DDR_A_12, PCM052_VF610_PAD_DDR_A11__DDR_A_11, PCM052_VF610_PAD_DDR_A10__DDR_A_10, PCM052_VF610_PAD_DDR_A9__DDR_A_9, PCM052_VF610_PAD_DDR_A8__DDR_A_8, PCM052_VF610_PAD_DDR_A7__DDR_A_7, PCM052_VF610_PAD_DDR_A6__DDR_A_6, PCM052_VF610_PAD_DDR_A5__DDR_A_5, PCM052_VF610_PAD_DDR_A4__DDR_A_4, PCM052_VF610_PAD_DDR_A3__DDR_A_3, PCM052_VF610_PAD_DDR_A2__DDR_A_2, PCM052_VF610_PAD_DDR_A1__DDR_A_1, PCM052_VF610_PAD_DDR_A0__DDR_A_0, PCM052_VF610_PAD_DDR_BA2__DDR_BA_2, PCM052_VF610_PAD_DDR_BA1__DDR_BA_1, PCM052_VF610_PAD_DDR_BA0__DDR_BA_0, PCM052_VF610_PAD_DDR_CAS__DDR_CAS_B, PCM052_VF610_PAD_DDR_CKE__DDR_CKE_0, PCM052_VF610_PAD_DDR_CLK__DDR_CLK_0, PCM052_VF610_PAD_DDR_CS__DDR_CS_B_0, PCM052_VF610_PAD_DDR_D15__DDR_D_15, PCM052_VF610_PAD_DDR_D14__DDR_D_14, PCM052_VF610_PAD_DDR_D13__DDR_D_13, PCM052_VF610_PAD_DDR_D12__DDR_D_12, PCM052_VF610_PAD_DDR_D11__DDR_D_11, PCM052_VF610_PAD_DDR_D10__DDR_D_10, PCM052_VF610_PAD_DDR_D9__DDR_D_9, PCM052_VF610_PAD_DDR_D8__DDR_D_8, PCM052_VF610_PAD_DDR_D7__DDR_D_7, PCM052_VF610_PAD_DDR_D6__DDR_D_6, PCM052_VF610_PAD_DDR_D5__DDR_D_5, PCM052_VF610_PAD_DDR_D4__DDR_D_4, PCM052_VF610_PAD_DDR_D3__DDR_D_3, PCM052_VF610_PAD_DDR_D2__DDR_D_2, PCM052_VF610_PAD_DDR_D1__DDR_D_1, PCM052_VF610_PAD_DDR_D0__DDR_D_0, PCM052_VF610_PAD_DDR_DQM1__DDR_DQM_1, PCM052_VF610_PAD_DDR_DQM0__DDR_DQM_0, PCM052_VF610_PAD_DDR_DQS1__DDR_DQS_1, PCM052_VF610_PAD_DDR_DQS0__DDR_DQS_0, PCM052_VF610_PAD_DDR_RAS__DDR_RAS_B, PCM052_VF610_PAD_DDR_WE__DDR_WE_B, PCM052_VF610_PAD_DDR_ODT1__DDR_ODT_0, PCM052_VF610_PAD_DDR_ODT0__DDR_ODT_1, PCM052_VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1, PCM052_VF610_PAD_DDR_DDRBYTE0__DDR_DDRBYTE0, PCM052_VF610_PAD_DDR_RESETB, }; imx_iomux_v3_setup_multiple_pads(pcm052_pads, ARRAY_SIZE(pcm052_pads)); ddrmc_ctrl_init_ddr3(&pcm052_ddr_timings, pcm052_cr_settings, pcm052_phy_settings, 1, 2); gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); return 0; } static void setup_iomux_uart(void) { static const iomux_v3_cfg_t uart1_pads[] = { NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, VF610_UART_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, VF610_UART_PAD_CTRL), }; imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); } #define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \ PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE) static void setup_iomux_enet(void) { static const iomux_v3_cfg_t enet0_pads[] = { NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKIN, ENET_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTC1__RMII0_MDIO, ENET_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTC0__RMII0_MDC, ENET_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTC2__RMII0_CRS_DV, ENET_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTC3__RMII0_RD1, ENET_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTC4__RMII0_RD0, ENET_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTC5__RMII0_RXER, ENET_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTC6__RMII0_TD1, ENET_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTC7__RMII0_TD0, ENET_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTC8__RMII0_TXEN, ENET_PAD_CTRL), }; imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads)); } /* * I2C2 is the only I2C used, on pads PTA22/PTA23. */ static void setup_iomux_i2c(void) { static const iomux_v3_cfg_t i2c_pads[] = { VF610_PAD_PTA22__I2C2_SCL, VF610_PAD_PTA23__I2C2_SDA, }; imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads)); } #ifdef CONFIG_NAND_VF610_NFC static void setup_iomux_nfc(void) { static const iomux_v3_cfg_t nfc_pads[] = { VF610_PAD_PTD31__NF_IO15, VF610_PAD_PTD30__NF_IO14, VF610_PAD_PTD29__NF_IO13, VF610_PAD_PTD28__NF_IO12, VF610_PAD_PTD27__NF_IO11, VF610_PAD_PTD26__NF_IO10, VF610_PAD_PTD25__NF_IO9, VF610_PAD_PTD24__NF_IO8, VF610_PAD_PTD23__NF_IO7, VF610_PAD_PTD22__NF_IO6, VF610_PAD_PTD21__NF_IO5, VF610_PAD_PTD20__NF_IO4, VF610_PAD_PTD19__NF_IO3, VF610_PAD_PTD18__NF_IO2, VF610_PAD_PTD17__NF_IO1, VF610_PAD_PTD16__NF_IO0, VF610_PAD_PTB24__NF_WE_B, VF610_PAD_PTB25__NF_CE0_B, VF610_PAD_PTB27__NF_RE_B, VF610_PAD_PTC26__NF_RB_B, VF610_PAD_PTC27__NF_ALE, VF610_PAD_PTC28__NF_CLE }; imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads)); } #endif static void setup_iomux_qspi(void) { static const iomux_v3_cfg_t qspi0_pads[] = { VF610_PAD_PTD0__QSPI0_A_QSCK, VF610_PAD_PTD1__QSPI0_A_CS0, VF610_PAD_PTD2__QSPI0_A_DATA3, VF610_PAD_PTD3__QSPI0_A_DATA2, VF610_PAD_PTD4__QSPI0_A_DATA1, VF610_PAD_PTD5__QSPI0_A_DATA0, VF610_PAD_PTD7__QSPI0_B_QSCK, VF610_PAD_PTD8__QSPI0_B_CS0, VF610_PAD_PTD9__QSPI0_B_DATA3, VF610_PAD_PTD10__QSPI0_B_DATA2, VF610_PAD_PTD11__QSPI0_B_DATA1, VF610_PAD_PTD12__QSPI0_B_DATA0, }; imx_iomux_v3_setup_multiple_pads(qspi0_pads, ARRAY_SIZE(qspi0_pads)); } #define ESDHC_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \ PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE) struct fsl_esdhc_cfg esdhc_cfg[1] = { {ESDHC1_BASE_ADDR}, }; int board_mmc_getcd(struct mmc *mmc) { /* eSDHC1 is always present */ return 1; } int board_mmc_init(bd_t *bis) { static const iomux_v3_cfg_t esdhc1_pads[] = { NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL), }; esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); imx_iomux_v3_setup_multiple_pads( esdhc1_pads, ARRAY_SIZE(esdhc1_pads)); return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); } static void clock_init(void) { struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR; clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK, CCM_CCGR0_UART1_CTRL_MASK); clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK, CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK); clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK, CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK | CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK | CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK | CCM_CCGR2_QSPI0_CTRL_MASK); clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK, CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK); clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK, CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK | CCM_CCGR4_GPC_CTRL_MASK); clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK, CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK); clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK, CCM_CCGR7_SDHC1_CTRL_MASK); clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK, CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK); clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK, CCM_CCGR10_NFC_CTRL_MASK | CCM_CCGR10_I2C2_CTRL_MASK); clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN, ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT); clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN, ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT); clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK, CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5)); clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK, CCM_CCSR_PLL1_PFD_CLK_SEL(3) | CCM_CCSR_PLL2_PFD4_EN | CCM_CCSR_PLL2_PFD3_EN | CCM_CCSR_PLL2_PFD2_EN | CCM_CCSR_PLL2_PFD1_EN | CCM_CCSR_PLL1_PFD4_EN | CCM_CCSR_PLL1_PFD3_EN | CCM_CCSR_PLL1_PFD2_EN | CCM_CCSR_PLL1_PFD1_EN | CCM_CCSR_DDRC_CLK_SEL(1) | CCM_CCSR_FAST_CLK_SEL(1) | CCM_CCSR_SYS_CLK_SEL(4)); clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK, CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) | CCM_CACRR_ARM_CLK_DIV(0)); clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK, CCM_CSCMR1_ESDHC1_CLK_SEL(3) | CCM_CSCMR1_QSPI0_CLK_SEL(3) | CCM_CSCMR1_NFC_CLK_SEL(0)); clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK, CCM_CSCDR1_RMII_CLK_EN); clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK, CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) | CCM_CSCDR2_NFC_EN); clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK, CCM_CSCDR3_QSPI0_EN | CCM_CSCDR3_QSPI0_DIV(1) | CCM_CSCDR3_QSPI0_X2_DIV(1) | CCM_CSCDR3_QSPI0_X4_DIV(3) | CCM_CSCDR3_NFC_PRE_DIV(5)); clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK, CCM_CSCMR2_RMII_CLK_SEL(0)); } static void mscm_init(void) { struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR; int i; for (i = 0; i < MSCM_IRSPRC_NUM; i++) writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]); } int board_phy_config(struct phy_device *phydev) { if (phydev->drv->config) phydev->drv->config(phydev); return 0; } int board_early_init_f(void) { clock_init(); mscm_init(); setup_iomux_uart(); setup_iomux_enet(); setup_iomux_i2c(); setup_iomux_qspi(); setup_iomux_nfc(); return 0; }