/*
* Prepare for running the kernel
*/
static void
_mode_kernel(void)
{
/* Disable the PROM NMI clock. */
set_clk_mode(0, IREG_CLOCK_ENAB_7, 0);
/* Restore our own vector table */
setvbr(vector_table);
/* Enable our level-5 clock. */
set_clk_mode(IREG_CLOCK_ENAB_5, 0, 1);
}
/*
* Prepare for running the PROM monitor
*/
static void
_mode_monitor(void)
{
/* Disable our level-5 clock. */
set_clk_mode(0, IREG_CLOCK_ENAB_5, 0);
/* Restore the PROM vector table */
setvbr(sunmon_vbr);
/* Enable the PROM NMI clock. */
set_clk_mode(IREG_CLOCK_ENAB_7, 0, 1);
/* XXX - Disable watchdog action? */
}
/*
* This is called from locore.s just after the kernel is remapped
* to its proper address, but before the call to main(). The work
* done here corresponds to various things done in locore.s on the
* hp300 port (and other m68k) but which we prefer to do in C code.
* Also do setup specific to the Sun PROM monitor and IDPROM here.
*/
void
_bootstrap(void)
{
extern struct consdev consdev_prom; /* XXX */
/* First, Clear BSS. */
memset(edata, 0, end - edata);
/* Set v_handler, get boothowto. */
sunmon_init();
/*
* Initialize console to point to the PROM (output only) table
* for early printf calls.
*/
cn_tab = &consdev_prom;
/* Handle kernel mapping, pmap_bootstrap(), etc. */
_vm_init();
/*
* Find and save OBIO mappings needed early,
* and call some init functions.
*/
obio_init();
/*
* Point interrupts/exceptions to our vector table.
* (Until now, we use the one setup by the PROM.)
*
* This is done after obio_init() / intreg_init() finds
* the interrupt register and disables the NMI clock so
* it will not cause "spurrious level 7" complaints.
* Done after _vm_init so the PROM can debug that.
*/
setvbr((void **)vector_table);
/* Interrupts are enabled later, after autoconfig. */
/*
* Find the IDPROM and copy it to memory.
* Needs obio_init and setvbr earlier.
*/
idprom_init();
/*
* Turn on the LEDs so we know power is on.
* Needs idprom_init and obio_init earlier.
*/
leds_init();
}
/*
* This is called from locore.s just after the kernel is remapped
* to its proper address, but before the call to main(). The work
* done here corresponds to various things done in locore.s on the
* hp300 port (and other m68k) but which we prefer to do in C code.
* Also do setup specific to the Sun PROM monitor and IDPROM here.
*/
void
_bootstrap(void)
{
vaddr_t va;
/* First, Clear BSS. */
memset(edata, 0, end - edata);
/* Initialize the PROM. */
prom_init();
/* Copy the IDPROM from control space. */
idprom_init();
/* Validate the Sun2 model (from IDPROM). */
_verify_hardware();
/* Handle kernel mapping, pmap_bootstrap(), etc. */
_vm_init();
/*
* Point interrupts/exceptions to our vector table.
* (Until now, we use the one setup by the PROM.)
*/
setvbr((void **)vector_table);
/* Interrupts are enabled later, after autoconfig. */
/*
* Now unmap the PROM's physical/virtual pages zero through three.
*/
for(va = 0; va < PAGE_SIZE * 4; va += PAGE_SIZE)
set_pte(va, PG_INVAL);
/*
* Turn on the LEDs so we know power is on.
* Needs idprom_init and obio_init earlier.
*/
leds_init();
}
/*
* Breath some life into the CPU...
*
* Set up the memory map,
* initialize a bunch of registers,
* initialize the UPM's
*/
void cpu_init_f(void)
{
volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
scm1->mpr = 0x77777777;
scm1->pacra = 0;
scm1->pacrb = 0;
scm1->pacrc = 0;
scm1->pacrd = 0;
scm1->pacre = 0;
scm1->pacrf = 0;
scm1->pacrg = 0;
/* FlexBus */
gpio->par_be =
GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 | GPIO_PAR_BE_BE1_BE1 |
GPIO_PAR_BE_BE0_BE0;
gpio->par_fbctl =
GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA | GPIO_PAR_FBCTL_RW_RW |
GPIO_PAR_FBCTL_TS_TS;
#if !defined(CONFIG_CF_SBF)
#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
fbcs->csar0 = CONFIG_SYS_CS0_BASE;
fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
#endif
#endif
#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
/* Latch chipselect */
fbcs->csar1 = CONFIG_SYS_CS1_BASE;
fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
#endif
#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
fbcs->csar2 = CONFIG_SYS_CS2_BASE;
fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
#endif
#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
fbcs->csar3 = CONFIG_SYS_CS3_BASE;
fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
#endif
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
fbcs->csar4 = CONFIG_SYS_CS4_BASE;
fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
#endif
#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
fbcs->csar5 = CONFIG_SYS_CS5_BASE;
fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
#endif
/*
* now the flash base address is no longer at 0 (Newer ColdFire family
* boot at address 0 instead of 0xFFnn_nnnn). The vector table must
* also move to the new location.
*/
if (CONFIG_SYS_CS0_BASE != 0)
setvbr(CONFIG_SYS_CS0_BASE);
#ifdef CONFIG_FSL_I2C
gpio->par_feci2c = GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA;
#endif
icache_enable();
}
/*
* Breath some life into the CPU...
*
* Set up the memory map,
* initialize a bunch of registers,
* initialize the UPM's
*/
void cpu_init_f(void)
{
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
#ifdef CONFIG_MCF5441x
scm_t *scm = (scm_t *) MMAP_SCM;
pm_t *pm = (pm_t *) MMAP_PM;
/* Disable Switch */
*(unsigned long *)(MMAP_L2_SW0 + 0x00000024) = 0;
/* Disable core watchdog */
out_be16(&scm->cwcr, 0);
out_8(&gpio->par_fbctl,
GPIO_PAR_FBCTL_ALE_FB_ALE | GPIO_PAR_FBCTL_OE_FB_OE |
GPIO_PAR_FBCTL_FBCLK | GPIO_PAR_FBCTL_RW |
GPIO_PAR_FBCTL_TA_TA);
out_8(&gpio->par_be,
GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 |
GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0);
/* eDMA */
out_8(&pm->pmcr0, 17);
/* INTR0 - INTR2 */
out_8(&pm->pmcr0, 18);
out_8(&pm->pmcr0, 19);
out_8(&pm->pmcr0, 20);
/* I2C */
out_8(&pm->pmcr0, 22);
out_8(&pm->pmcr1, 4);
out_8(&pm->pmcr1, 7);
/* DTMR0 - DTMR3*/
out_8(&pm->pmcr0, 28);
out_8(&pm->pmcr0, 29);
out_8(&pm->pmcr0, 30);
out_8(&pm->pmcr0, 31);
/* PIT0 - PIT3 */
out_8(&pm->pmcr0, 32);
out_8(&pm->pmcr0, 33);
out_8(&pm->pmcr0, 34);
out_8(&pm->pmcr0, 35);
/* Edge Port */
out_8(&pm->pmcr0, 36);
out_8(&pm->pmcr0, 37);
/* USB OTG */
out_8(&pm->pmcr0, 44);
/* USB Host */
out_8(&pm->pmcr0, 45);
/* ESDHC */
out_8(&pm->pmcr0, 51);
/* ENET0 - ENET1 */
out_8(&pm->pmcr0, 53);
out_8(&pm->pmcr0, 54);
/* NAND */
out_8(&pm->pmcr0, 63);
#ifdef CONFIG_SYS_I2C_0
out_8(&gpio->par_cani2c, 0xF0);
/* I2C0 pull up */
out_be16(&gpio->pcr_b, 0x003C);
/* I2C0 max speed */
out_8(&gpio->srcr_cani2c, 0x03);
#endif
#ifdef CONFIG_SYS_I2C_2
/* I2C2 */
out_8(&gpio->par_ssi0h, 0xA0);
/* I2C2, UART7 */
out_8(&gpio->par_ssi0h, 0xA8);
/* UART7 */
out_8(&gpio->par_ssi0l, 0x2);
/* UART8, UART9 */
out_8(&gpio->par_cani2c, 0xAA);
/* UART4, UART0 */
out_8(&gpio->par_uart0, 0xAF);
/* UART5, UART1 */
out_8(&gpio->par_uart1, 0xAF);
/* UART6, UART2 */
out_8(&gpio->par_uart2, 0xAF);
/* I2C2 pull up */
out_be16(&gpio->pcr_h, 0xF000);
#endif
#ifdef CONFIG_SYS_I2C_5
/* I2C5 */
out_8(&gpio->par_uart1, 0x0A);
/* I2C5 pull up */
out_be16(&gpio->pcr_e, 0x0003);
out_be16(&gpio->pcr_f, 0xC000);
#endif
/* Lowest slew rate for UART0,1,2 */
out_8(&gpio->srcr_uart, 0x00);
#endif /* CONFIG_MCF5441x */
#ifdef CONFIG_MCF5445x
scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
out_be32(&scm1->mpr, 0x77777777);
out_be32(&scm1->pacra, 0);
out_be32(&scm1->pacrb, 0);
out_be32(&scm1->pacrc, 0);
out_be32(&scm1->pacrd, 0);
out_be32(&scm1->pacre, 0);
out_be32(&scm1->pacrf, 0);
out_be32(&scm1->pacrg, 0);
/* FlexBus */
out_8(&gpio->par_be,
GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 |
GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0);
out_8(&gpio->par_fbctl,
GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA |
GPIO_PAR_FBCTL_RW_RW | GPIO_PAR_FBCTL_TS_TS);
#ifdef CONFIG_SYS_FSL_I2C
out_be16(&gpio->par_feci2c,
GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA);
#endif
#endif /* CONFIG_MCF5445x */
/* FlexBus Chipselect */
init_fbcs();
/*
* now the flash base address is no longer at 0 (Newer ColdFire family
* boot at address 0 instead of 0xFFnn_nnnn). The vector table must
* also move to the new location.
*/
if (CONFIG_SYS_CS0_BASE != 0)
setvbr(CONFIG_SYS_CS0_BASE);
icache_enable();
}
