Exemple #1
0
void sbc_init(void)
{
	/* XECS1: sub/boot memory (boot swap = off/on) */
	writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
	writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
	writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
	writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);

#if !defined(CONFIG_SPL_BUILD)
	/* XECS0: boot/sub memory (boot swap = off/on) */
	writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
	writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
	writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
	writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
#endif
	/* XECS3: peripherals */
	writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30);
	writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31);
	writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32);
	writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34);

	/* base address regsiters */
	writel(0x0000bc01, SBBASE0);
	writel(0x0400bc01, SBBASE1);
	writel(0x0800bf01, SBBASE3);

#if !defined(CONFIG_SPL_BUILD)
	/* enable access to sub memory when boot swap is on */
	sg_set_pinsel(155, 1); /* PORT24 -> XECS0 */
#endif
	sg_set_pinsel(156, 1); /* PORT25 -> XECS3 */
}
Exemple #2
0
void sbc_init(void)
{
	/* only address/data multiplex mode is supported */

	/*
	 * Only CS1 is connected to support card.
	 * BKSZ[1:0] should be set to "01".
	 */
	writel(SBCTRL0_ADMULTIPLX_MEM_VALUE, SBCTRL10);
	writel(SBCTRL1_ADMULTIPLX_MEM_VALUE, SBCTRL11);
	writel(SBCTRL2_ADMULTIPLX_MEM_VALUE, SBCTRL12);

	if (boot_is_swapped()) {
		/*
		 * Boot Swap On: boot from external NOR/SRAM
		 * 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff.
		 *
		 * 0x00000000-0x01efffff, 0x02000000-0x03efffff: memory bank
		 * 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals
		 */
		writel(0x0000bc01, SBBASE0);
	} else {
		/*
		 * Boot Swap Off: boot from mask ROM
		 * 0x00000000-0x01ffffff: mask ROM
		 * 0x02000000-0x03efffff: memory bank (31MB)
		 * 0x03f00000-0x03ffffff: peripherals (1MB)
		 */
		writel(0x0000be01, SBBASE0); /* dummy */
		writel(0x0200be01, SBBASE1);
	}

	sg_set_pinsel(99, 1);	/* GPIO26 -> EA24 */
}
Exemple #3
0
unsigned int uniphier_pro5_debug_uart_init(void)
{
	u32 tmp;

	sg_set_iectrl(0);
	sg_set_pinsel(47, 0, 4, 8);	/* TXD0 -> TXD0 */
	sg_set_pinsel(49, 0, 4, 8);	/* TXD1 -> TXD1 */
	sg_set_pinsel(51, 0, 4, 8);	/* TXD2 -> TXD2 */
	sg_set_pinsel(53, 0, 4, 8);	/* TXD3 -> TXD3 */

	writel(1, SG_LOADPINCTRL);

	tmp = readl(SC_CLKCTRL);
	tmp |= SC_CLKCTRL_CEN_PERI;
	writel(tmp, SC_CLKCTRL);

	return DIV_ROUND_CLOSEST(UNIPHIER_PRO5_UART_CLK, 16 * CONFIG_BAUDRATE);
}
Exemple #4
0
unsigned int uniphier_ld20_debug_uart_init(void)
{
	u32 tmp;

	sg_set_iectrl(54);		/* TXD0 */
	sg_set_iectrl(58);		/* TXD1 */
	sg_set_iectrl(90);		/* TXD2 */
	sg_set_iectrl(94);		/* TXD3 */
	sg_set_pinsel(54, 0, 8, 4);	/* TXD0 -> TXD0 */
	sg_set_pinsel(58, 1, 8, 4);	/* SPITXD1 -> TXD1 */
	sg_set_pinsel(90, 1, 8, 4);	/* PC0WE -> TXD2 */
	sg_set_pinsel(94, 1, 8, 4);	/* PCD00 -> TXD3 */

	tmp = readl(SC_CLKCTRL4);
	tmp |= SC_CLKCTRL4_PERI;
	writel(tmp, SC_CLKCTRL4);

	return DIV_ROUND_CLOSEST(UNIPHIER_LD20_UART_CLK, 16 * CONFIG_BAUDRATE);
}
Exemple #5
0
void sbc_init(void)
{
	u32 tmp;

	/* system bus output enable */
	tmp = readl(PC0CTRL);
	tmp &= 0xfffffcff;
	writel(tmp, PC0CTRL);

	/* XECS1: sub/boot memory (boot swap = off/on) */
	writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
	writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
	writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
	writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);

	/* XECS0: boot/sub memory (boot swap = off/on) */
	writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
	writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
	writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
	writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);

	/* XECS3: peripherals */
	writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30);
	writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31);
	writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32);
	writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34);

	/* base address regsiters */
	writel(0x0000bc01, SBBASE0);
	writel(0x0400bc01, SBBASE1);
	writel(0x0800bf01, SBBASE3);

	/* enable access to sub memory when boot swap is on */
	if (boot_is_swapped())
		sg_set_pinsel(155, 1); /* PORT24 -> XECS0 */

	sg_set_pinsel(156, 1); /* PORT25 -> XECS3 */
}
Exemple #6
0
void pin_init(void)
{
#ifdef CONFIG_USB_EHCI_UNIPHIER
	sg_set_pinsel(13, 0);	/* USB0OC */
	sg_set_pinsel(14, 1);	/* USB0VBUS */

	sg_set_pinsel(15, 0);	/* USB1OC */
	sg_set_pinsel(16, 1);	/* USB1VBUS */

	sg_set_pinsel(17, 0);	/* USB2OC */
	sg_set_pinsel(18, 1);	/* USB2VBUS */

	sg_set_pinsel(19, 0);	/* USB3OC */
	sg_set_pinsel(20, 1);	/* USB3VBUS */
#endif
}
Exemple #7
0
void early_pin_init(void)
{
	/* Comment format:    PAD Name -> Function Name */

#ifdef CONFIG_UNIPHIER_SERIAL
	sg_set_pinsel(63, 0);	/* RXD0 */
	sg_set_pinsel(64, 1);	/* TXD0 */

	sg_set_pinsel(65, 0);	/* RXD1 */
	sg_set_pinsel(66, 1);	/* TXD1 */

	sg_set_pinsel(96, 2);	/* RXD2 */
	sg_set_pinsel(102, 2);	/* TXD2 */
#endif
}
int ph1_sld3_early_pin_init(const struct uniphier_board_data *bd)
{
	/* Comment format:    PAD Name -> Function Name */

#ifdef CONFIG_UNIPHIER_SERIAL
	sg_set_pinsel(63, 0, 4, 4);	/* RXD0 */
	sg_set_pinsel(64, 1, 4, 4);	/* TXD0 */

	sg_set_pinsel(65, 0, 4, 4);	/* RXD1 */
	sg_set_pinsel(66, 1, 4, 4);	/* TXD1 */

	sg_set_pinsel(96, 2, 4, 4);	/* RXD2 */
	sg_set_pinsel(102, 2, 4, 4);	/* TXD2 */
#endif

	return 0;
}
Exemple #9
0
void uniphier_pro4_pin_init(void)
{
	/* Comment format:    PAD Name -> Function Name */

#ifdef CONFIG_NAND_DENALI
	sg_set_pinsel(40, 0, 4, 8);	/* NFD0   -> NFD0 */
	sg_set_pinsel(41, 0, 4, 8);	/* NFD1   -> NFD1 */
	sg_set_pinsel(42, 0, 4, 8);	/* NFD2   -> NFD2 */
	sg_set_pinsel(43, 0, 4, 8);	/* NFD3   -> NFD3 */
	sg_set_pinsel(44, 0, 4, 8);	/* NFD4   -> NFD4 */
	sg_set_pinsel(45, 0, 4, 8);	/* NFD5   -> NFD5 */
	sg_set_pinsel(46, 0, 4, 8);	/* NFD6   -> NFD6 */
	sg_set_pinsel(47, 0, 4, 8);	/* NFD7   -> NFD7 */
	sg_set_pinsel(48, 0, 4, 8);	/* NFALE  -> NFALE */
	sg_set_pinsel(49, 0, 4, 8);	/* NFCLE  -> NFCLE */
	sg_set_pinsel(50, 0, 4, 8);	/* XNFRE  -> XNFRE */
	sg_set_pinsel(51, 0, 4, 8);	/* XNFWE  -> XNFWE */
	sg_set_pinsel(52, 0, 4, 8);	/* XNFWP  -> XNFWP */
	sg_set_pinsel(53, 0, 4, 8);	/* XNFCE0 -> XNFCE0 */
	sg_set_pinsel(54, 0, 4, 8);	/* NRYBY0 -> NRYBY0 */
	/* sg_set_pinsel(131, 1, 4, 8); */	/* RXD2   -> NRYBY1 */
	/* sg_set_pinsel(132, 1, 4, 8); */	/* TXD2   -> XNFCE1 */
#endif

#ifdef CONFIG_USB_XHCI_UNIPHIER
	sg_set_pinsel(180, 0, 4, 8);	/* USB0VBUS -> USB0VBUS */
	sg_set_pinsel(181, 0, 4, 8);	/* USB0OD   -> USB0OD */
	sg_set_pinsel(182, 0, 4, 8);	/* USB1VBUS -> USB1VBUS */
	sg_set_pinsel(183, 0, 4, 8);	/* USB1OD   -> USB1OD */
#endif

	writel(1, SG_LOADPINCTRL);
}
Exemple #10
0
void sbc_init(void)
{
#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
	/*
	 * Only CS1 is connected to support card.
	 * BKSZ[1:0] should be set to "01".
	 */
	writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10);
	writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11);
	writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12);
	writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14);

	if (readl(SBBASE0) & 0x1) {
		/*
		 * Boot Swap Off: boot from mask ROM
		 * 0x00000000-0x01ffffff: mask ROM
		 * 0x02000000-0x3effffff: memory bank (31MB)
		 * 0x03f00000-0x3fffffff: peripherals (1MB)
		 */
		writel(0x0000be01, SBBASE0); /* dummy */
		writel(0x0200be01, SBBASE1);
	} else {
		/*
		 * Boot Swap On: boot from external NOR/SRAM
		 * 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff.
		 *
		 * 0x00000000-0x01efffff, 0x02000000-0x03efffff: memory bank
		 * 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals
		 */
		writel(0x0000bc01, SBBASE0);
	}
#elif defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
#if !defined(CONFIG_SPL_BUILD)
	/* XECS0: boot/sub memory (boot swap = off/on) */
	writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
	writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
	writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
	writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
#endif
	/* XECS1: sub/boot memory (boot swap = off/on) */
	writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
	writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
	writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
	writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);

	/* XECS3: peripherals */
	writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30);
	writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31);
	writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32);
	writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34);

	writel(0x0000bc01, SBBASE0); /* boot memory */
	writel(0x0400bc01, SBBASE1); /* sub memory */
	writel(0x0800bf01, SBBASE3); /* peripherals */

#if !defined(CONFIG_SPL_BUILD)
	sg_set_pinsel(318, 5); /* PORT22 -> XECS0 */
#endif
	sg_set_pinsel(313, 5); /* PORT15 -> XECS3 */
	writel(0x00000001, SG_LOADPINCTRL);

#endif /* CONFIG_XXX_MICRO_SUPPORT_CARD */
}
Exemple #11
0
void uniphier_pxs2_pin_init(void)
{
	/* Comment format:    PAD Name -> Function Name */

#ifdef CONFIG_NAND_DENALI
	sg_set_pinsel(30, 8, 8, 4);	/* XNFRE  -> XNFRE */
	sg_set_pinsel(31, 8, 8, 4);	/* XNFWE  -> XNFWE */
	sg_set_pinsel(32, 8, 8, 4);	/* NFALE  -> NFALE */
	sg_set_pinsel(33, 8, 8, 4);	/* NFCLE  -> NFCLE */
	sg_set_pinsel(34, 8, 8, 4);	/* XNFWP  -> XNFWP */
	sg_set_pinsel(35, 8, 8, 4);	/* XNFCE0 -> XNFCE0 */
	sg_set_pinsel(36, 8, 8, 4);	/* NRYBY0 -> NRYBY0 */
	sg_set_pinsel(37, 8, 8, 4);	/* XNFCE1 -> NRYBY1 */
	sg_set_pinsel(38, 8, 8, 4);	/* NRYBY1 -> XNFCE1 */
	sg_set_pinsel(39, 8, 8, 4);	/* NFD0   -> NFD0 */
	sg_set_pinsel(40, 8, 8, 4);	/* NFD1   -> NFD1 */
	sg_set_pinsel(41, 8, 8, 4);	/* NFD2   -> NFD2 */
	sg_set_pinsel(42, 8, 8, 4);	/* NFD3   -> NFD3 */
	sg_set_pinsel(43, 8, 8, 4);	/* NFD4   -> NFD4 */
	sg_set_pinsel(44, 8, 8, 4);	/* NFD5   -> NFD5 */
	sg_set_pinsel(45, 8, 8, 4);	/* NFD6   -> NFD6 */
	sg_set_pinsel(46, 8, 8, 4);	/* NFD7   -> NFD7 */
#endif

#ifdef CONFIG_USB_XHCI_UNIPHIER
	sg_set_pinsel(56, 8, 8, 4);	/* USB0VBUS -> USB0VBUS */
	sg_set_pinsel(57, 8, 8, 4);	/* USB0OD   -> USB0OD */
	sg_set_pinsel(58, 8, 8, 4);	/* USB1VBUS -> USB1VBUS */
	sg_set_pinsel(59, 8, 8, 4);	/* USB1OD   -> USB1OD */
	sg_set_pinsel(60, 8, 8, 4);	/* USB2VBUS -> USB2VBUS */
	sg_set_pinsel(61, 8, 8, 4);	/* USB2OD   -> USB2OD */
	sg_set_pinsel(62, 8, 8, 4);	/* USB3VBUS -> USB3VBUS */
	sg_set_pinsel(63, 8, 8, 4);	/* USB3OD   -> USB3OD */
#endif
}
Exemple #12
0
int uniphier_sld3_sbc_init(const struct uniphier_board_data *bd)
{
	sg_set_pinsel(99, 1, 4, 4);	/* GPIO26 -> EA24 */

	return 0;
}
void pin_init(void)
{
	/* Comment format:    PAD Name -> Function Name */

#ifdef CONFIG_UNIPHIER_SERIAL
	sg_set_pinsel(70, 3);	/* HDDOUT0 -> TXD0 */
	sg_set_pinsel(71, 3);	/* HSDOUT1 -> RXD0 */

	sg_set_pinsel(114, 0);	/* TXD1 -> TXD1 */
	sg_set_pinsel(115, 0);	/* RXD1 -> RXD1 */

	sg_set_pinsel(112, 1);	/* SBO1 -> TXD2 */
	sg_set_pinsel(113, 1);	/* SBI1 -> RXD2 */

	sg_set_pinsel(110, 1);	/* SBO0 -> TXD3 */
	sg_set_pinsel(111, 1);	/* SBI0 -> RXD3 */
#endif

#ifdef CONFIG_NAND_DENALI
	sg_set_pinsel(15, 0);	/* XNFRE_GB -> XNFRE_GB */
	sg_set_pinsel(16, 0);	/* XNFWE_GB -> XNFWE_GB */
	sg_set_pinsel(17, 0);	/* XFALE_GB -> NFALE_GB */
	sg_set_pinsel(18, 0);	/* XFCLE_GB -> NFCLE_GB */
	sg_set_pinsel(19, 0);	/* XNFWP_GB -> XFNWP_GB */
	sg_set_pinsel(20, 0);	/* XNFCE0_GB -> XNFCE0_GB */
	sg_set_pinsel(21, 0);	/* NANDRYBY0_GB -> NANDRYBY0_GB */
	sg_set_pinsel(22, 0);	/* XFNCE1_GB  -> XFNCE1_GB */
	sg_set_pinsel(23, 0);	/* NANDRYBY1_GB  -> NANDRYBY1_GB */
	sg_set_pinsel(24, 0);	/* NFD0_GB -> NFD0_GB */
	sg_set_pinsel(25, 0);	/* NFD1_GB -> NFD1_GB */
	sg_set_pinsel(26, 0);	/* NFD2_GB -> NFD2_GB */
	sg_set_pinsel(27, 0);	/* NFD3_GB -> NFD3_GB */
	sg_set_pinsel(28, 0);	/* NFD4_GB -> NFD4_GB */
	sg_set_pinsel(29, 0);	/* NFD5_GB -> NFD5_GB */
	sg_set_pinsel(30, 0);	/* NFD6_GB -> NFD6_GB */
	sg_set_pinsel(31, 0);	/* NFD7_GB -> NFD7_GB */
#endif

#ifdef CONFIG_USB_EHCI_UNIPHIER
	sg_set_pinsel(41, 0);	/* USB0VBUS -> USB0VBUS */
	sg_set_pinsel(42, 0);	/* USB0OD   -> USB0OD */
	sg_set_pinsel(43, 0);	/* USB1VBUS -> USB1VBUS */
	sg_set_pinsel(44, 0);	/* USB1OD   -> USB1OD */
	/* sg_set_pinsel(114, 4); */ /* TXD1 -> USB2VBUS (shared with UART) */
	/* sg_set_pinsel(115, 4); */ /* RXD1 -> USB2OD */
#endif
}
void ph1_ld4_pin_init(void)
{
	u32 tmp;

	/* Comment format:    PAD Name -> Function Name */

#ifdef CONFIG_NAND_DENALI
	sg_set_pinsel(158, 0, 8, 4);	/* XNFRE -> XNFRE_GB */
	sg_set_pinsel(159, 0, 8, 4);	/* XNFWE -> XNFWE_GB */
	sg_set_pinsel(160, 0, 8, 4);	/* XFALE -> NFALE_GB */
	sg_set_pinsel(161, 0, 8, 4);	/* XFCLE -> NFCLE_GB */
	sg_set_pinsel(162, 0, 8, 4);	/* XNFWP -> XFNWP_GB */
	sg_set_pinsel(163, 0, 8, 4);	/* XNFCE0 -> XNFCE0_GB */
	sg_set_pinsel(164, 0, 8, 4);	/* NANDRYBY0 -> NANDRYBY0_GB */
	sg_set_pinsel(22, 0, 8, 4);	/* MMCCLK  -> XFNCE1_GB */
	sg_set_pinsel(23, 0, 8, 4);	/* MMCCMD  -> NANDRYBY1_GB */
	sg_set_pinsel(24, 0, 8, 4);	/* MMCDAT0 -> NFD0_GB */
	sg_set_pinsel(25, 0, 8, 4);	/* MMCDAT1 -> NFD1_GB */
	sg_set_pinsel(26, 0, 8, 4);	/* MMCDAT2 -> NFD2_GB */
	sg_set_pinsel(27, 0, 8, 4);	/* MMCDAT3 -> NFD3_GB */
	sg_set_pinsel(28, 0, 8, 4);	/* MMCDAT4 -> NFD4_GB */
	sg_set_pinsel(29, 0, 8, 4);	/* MMCDAT5 -> NFD5_GB */
	sg_set_pinsel(30, 0, 8, 4);	/* MMCDAT6 -> NFD6_GB */
	sg_set_pinsel(31, 0, 8, 4);	/* MMCDAT7 -> NFD7_GB */
#endif

#ifdef CONFIG_USB_EHCI_UNIPHIER
	sg_set_pinsel(53, 0, 8, 4);	/* USB0VBUS -> USB0VBUS */
	sg_set_pinsel(54, 0, 8, 4);	/* USB0OD   -> USB0OD */
	sg_set_pinsel(55, 0, 8, 4);	/* USB1VBUS -> USB1VBUS */
	sg_set_pinsel(56, 0, 8, 4);	/* USB1OD   -> USB1OD */
	/* sg_set_pinsel(67, 23, 8, 4); */ /* PCOE -> USB2VBUS */
	/* sg_set_pinsel(68, 23, 8, 4); */ /* PCWAIT -> USB2OD */
#endif

	tmp = readl(SG_IECTRL);
	tmp |= 0x41;
	writel(tmp, SG_IECTRL);
}
void pin_init(void)
{
	/* Comment format:    PAD Name -> Function Name */

#ifdef CONFIG_UNIPHIER_SERIAL
	sg_set_pinsel(127, 0);	/* RXD0 -> RXD0 */
	sg_set_pinsel(128, 0);	/* TXD0 -> TXD0 */
	sg_set_pinsel(129, 0);	/* RXD1 -> RXD1 */
	sg_set_pinsel(130, 0);	/* TXD1 -> TXD1 */
	sg_set_pinsel(131, 0);	/* RXD2 -> RXD2 */
	sg_set_pinsel(132, 0);	/* TXD2 -> TXD2 */
	sg_set_pinsel(88, 2);	/* CH6CLK -> RXD3 */
	sg_set_pinsel(89, 2);	/* CH6VAL -> TXD3 */
#endif

#ifdef CONFIG_NAND_DENALI
	sg_set_pinsel(40, 0);	/* NFD0   -> NFD0 */
	sg_set_pinsel(41, 0);	/* NFD1   -> NFD1 */
	sg_set_pinsel(42, 0);	/* NFD2   -> NFD2 */
	sg_set_pinsel(43, 0);	/* NFD3   -> NFD3 */
	sg_set_pinsel(44, 0);	/* NFD4   -> NFD4 */
	sg_set_pinsel(45, 0);	/* NFD5   -> NFD5 */
	sg_set_pinsel(46, 0);	/* NFD6   -> NFD6 */
	sg_set_pinsel(47, 0);	/* NFD7   -> NFD7 */
	sg_set_pinsel(48, 0);	/* NFALE  -> NFALE */
	sg_set_pinsel(49, 0);	/* NFCLE  -> NFCLE */
	sg_set_pinsel(50, 0);	/* XNFRE  -> XNFRE */
	sg_set_pinsel(51, 0);	/* XNFWE  -> XNFWE */
	sg_set_pinsel(52, 0);	/* XNFWP  -> XNFWP */
	sg_set_pinsel(53, 0);	/* XNFCE0 -> XNFCE0 */
	sg_set_pinsel(54, 0);	/* NRYBY0 -> NRYBY0 */
#endif

#ifdef CONFIG_USB_EHCI_UNIPHIER
	sg_set_pinsel(184, 0);	/* USB2VBUS -> USB2VBUS */
	sg_set_pinsel(185, 0);	/* USB2OD   -> USB2OD */
	sg_set_pinsel(187, 0);	/* USB3VBUS -> USB3VBUS */
	sg_set_pinsel(188, 0);	/* USB3OD   -> USB3OD */
#endif

	writel(1, SG_LOADPINCTRL);
}