void gendsra() { #ifdef INTERPRET_DSRA gencallinterp((unsigned long)DSRA, 0); #else int rt1 = allocate_64_register1((unsigned long *)dst->f.r.rt); int rt2 = allocate_64_register2((unsigned long *)dst->f.r.rt); int rd1 = allocate_64_register1_w((unsigned long *)dst->f.r.rd); int rd2 = allocate_64_register2_w((unsigned long *)dst->f.r.rd); mov_reg32_reg32(rd1, rt1); mov_reg32_reg32(rd2, rt2); shrd_reg32_reg32_imm8(rd1, rd2, dst->f.r.sa); sar_reg32_imm8(rd2, dst->f.r.sa); if (dst->f.r.sa & 0x20) { mov_reg32_reg32(rd1, rd2); sar_reg32_imm8(rd2, 31); } #endif }
void gendsra(usf_state_t * state) { #ifdef INTERPRET_DSRA gencallinterp(state, (unsigned int)state->current_instruction_table.DSRA, 0); #else int rt1 = allocate_64_register1(state, (unsigned int *)state->dst->f.r.rt); int rt2 = allocate_64_register2(state, (unsigned int *)state->dst->f.r.rt); int rd1 = allocate_64_register1_w(state, (unsigned int *)state->dst->f.r.rd); int rd2 = allocate_64_register2_w(state, (unsigned int *)state->dst->f.r.rd); mov_reg32_reg32(state, rd1, rt1); mov_reg32_reg32(state, rd2, rt2); shrd_reg32_reg32_imm8(state, rd1, rd2, state->dst->f.r.sa); sar_reg32_imm8(state, rd2, state->dst->f.r.sa); if (state->dst->f.r.sa & 0x20) { mov_reg32_reg32(state, rd1, rd2); sar_reg32_imm8(state, rd2, 31); } #endif }
void gendsrl(void) { #ifdef INTERPRET_DSRL gencallinterp((unsigned int)cached_interpreter_table.DSRL, 0); #else int rt1 = allocate_64_register1((unsigned int *)dst->f.r.rt); int rt2 = allocate_64_register2((unsigned int *)dst->f.r.rt); int rd1 = allocate_64_register1_w((unsigned int *)dst->f.r.rd); int rd2 = allocate_64_register2_w((unsigned int *)dst->f.r.rd); mov_reg32_reg32(rd1, rt1); mov_reg32_reg32(rd2, rt2); shrd_reg32_reg32_imm8(rd1, rd2, dst->f.r.sa); shr_reg32_imm8(rd2, dst->f.r.sa); if (dst->f.r.sa & 0x20) { mov_reg32_reg32(rd1, rd2); xor_reg32_reg32(rd2, rd2); } #endif }
void gendsra(void) { #ifdef INTERPRET_DSRA gencallinterp((unsigned int)cached_interpreter_table.DSRA, 0); #else int rt1 = allocate_64_register1((unsigned int *)g_dev.r4300.recomp.dst->f.r.rt); int rt2 = allocate_64_register2((unsigned int *)g_dev.r4300.recomp.dst->f.r.rt); int rd1 = allocate_64_register1_w((unsigned int *)g_dev.r4300.recomp.dst->f.r.rd); int rd2 = allocate_64_register2_w((unsigned int *)g_dev.r4300.recomp.dst->f.r.rd); mov_reg32_reg32(rd1, rt1); mov_reg32_reg32(rd2, rt2); shrd_reg32_reg32_imm8(rd1, rd2, g_dev.r4300.recomp.dst->f.r.sa); sar_reg32_imm8(rd2, g_dev.r4300.recomp.dst->f.r.sa); if (g_dev.r4300.recomp.dst->f.r.sa & 0x20) { mov_reg32_reg32(rd1, rd2); sar_reg32_imm8(rd2, 31); } #endif }