void si_en(){ // i2c0_init(255); // is default here si5351c_disable_all_outputs(); si5351c_disable_oeb_pin_control(); si5351c_power_down_all_clocks(); si5351c_set_crystal_configuration(); si5351c_enable_xo_and_ms_fanout(); si5351c_configure_pll_sources(); si5351c_configure_pll_multisynth(); /* MS3/CLK3 is the source for the external clock output. */ si5351c_configure_multisynth(3, 80*128-512, 0, 1, 0); /* 800/80 = 10MHz */ /* MS4/CLK4 is the source for the RFFC5071 mixer. */ si5351c_configure_multisynth(4, 16*128-512, 0, 1, 0); /* 800/16 = 50MHz */ /* MS5/CLK5 is the source for the MAX2837 clock input. */ si5351c_configure_multisynth(5, 20*128-512, 0, 1, 0); /* 800/20 = 40MHz */ /* MS6/CLK6 is unused. */ /* MS7/CLK7 is the source for the LPC43xx microcontroller. */ uint8_t ms7data[] = { 90, 255, 20, 0 }; si5351c_write(ms7data, sizeof(ms7data)); si5351c_set_clock_source(PLL_SOURCE_XTAL); // soft reset uint8_t resetdata[] = { 177, 0xac }; si5351c_write(resetdata, sizeof(resetdata)); si5351c_enable_clock_outputs(); };
extern "C" int main() { turn_on_crystal_oscillator(); start_system_pll(); start_usb_pll(); set_main_clock_to_system_pll(); enable_peripheral_clocks(); serial_init(); configure_pins(); delay(1000000); //enable_clock_output(); NVIC.enable_interrupts(); //serial_write_string("main():loop"); //serial_write_line(); // Power for FPGA v1p2_enable(); // FPGA VCCINT v2p5_enable(); // FPGA PLLs? v1p8_enable(); // FPGA VCCIOs, DDR2. v1p1_enable(); // USB internal voltage delay(1000000); // Power for the clock generator. // V3P3A must be turned on *after* V1P8 to satisfy // Si5351C requirement. v3p3a_enable(); delay(1000000); // I2C configuration i2c0_init(500); // Give Si5351C time to power up? delay(100000); si5351c_disable_all_outputs(); //si5351c_disable_oeb_pin_control(); si5351c_power_down_all_clocks(); si5351c_set_crystal_configuration(); si5351c_enable_xo_and_ms_fanout(); si5351c_configure_pll_sources_for_xtal(); si5351c_configure_pll1_multisynth(); si5351c_configure_multisynth(4, 1536, 0, 1, 0); // 50MHz si5351c_configure_multisynth(5, 1536, 0, 1, 0); // 50MHz si5351c_configure_multisynths_6_and_7(); si5351c_configure_clock_control(); si5351c_enable_clock_outputs(); clockgen_output_enable(); fe_enable(); while(true) { //write_led_status(read_fpga_conf_done()); write_led_status(1); delay(1000000); write_led_status(0); delay(1000000); } return 0; }
bool sample_rate_set(const uint32_t sample_rate_hz) { uint32_t p1 = 4608; uint32_t p2 = 0; uint32_t p3 = 0; switch(sample_rate_hz) { case 8000000: p1 = SI_INTDIV(50); // 800MHz / 50 = 16 MHz (SGPIO), 8 MHz (codec) break; case 9216000: // 43.40277777777778: a = 43; b = 29; c = 72 p1 = 5043; p2 = 40; p3 = 72; break; case 10000000: p1 = SI_INTDIV(40); // 800MHz / 40 = 20 MHz (SGPIO), 10 MHz (codec) break; case 12288000: // 32.552083333333336: a = 32; b = 159; c = 288 p1 = 3654; p2 = 192; p3 = 288; break; case 12500000: p1 = SI_INTDIV(32); // 800MHz / 32 = 25 MHz (SGPIO), 12.5 MHz (codec) break; case 16000000: p1 = SI_INTDIV(25); // 800MHz / 25 = 32 MHz (SGPIO), 16 MHz (codec) break; case 18432000: // 21.70138888889: a = 21; b = 101; c = 144 p1 = 2265; p2 = 112; p3 = 144; break; case 20000000: p1 = SI_INTDIV(20); // 800MHz / 20 = 40 MHz (SGPIO), 20 MHz (codec) break; default: return false; } /* MS0/CLK0 is the source for the MAX5864/CPLD (CODEC_CLK). */ si5351c_configure_multisynth(&clock_gen, 0, p1, p2, p3, 1); /* MS0/CLK1 is the source for the CPLD (CODEC_X2_CLK). */ si5351c_configure_multisynth(&clock_gen, 1, p1, 0, 1, 0);//p1 doesn't matter /* MS0/CLK2 is the source for SGPIO (CODEC_X2_CLK) */ si5351c_configure_multisynth(&clock_gen, 2, p1, 0, 1, 0);//p1 doesn't matter return true; }
/* clock startup for LPC4320 configure PLL1 to max speed (204MHz). Note: PLL1 clock is used by M4/M0 core, Peripheral, APB1. */ void cpu_clock_init(void) { /* use IRC as clock source for APB1 (including I2C0) */ CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_IRC); /* use IRC as clock source for APB3 */ CGU_BASE_APB3_CLK = CGU_BASE_APB3_CLK_CLK_SEL(CGU_SRC_IRC); i2c_bus_start(clock_gen.bus, &i2c_config_si5351c_slow_clock); si5351c_disable_all_outputs(&clock_gen); si5351c_disable_oeb_pin_control(&clock_gen); si5351c_power_down_all_clocks(&clock_gen); si5351c_set_crystal_configuration(&clock_gen); si5351c_enable_xo_and_ms_fanout(&clock_gen); si5351c_configure_pll_sources(&clock_gen); si5351c_configure_pll_multisynth(&clock_gen); /* * Clocks: * CLK0 -> MAX5864/CPLD * CLK1 -> CPLD * CLK2 -> SGPIO * CLK3 -> External Clock Output (power down at boot) * CLK4 -> RFFC5072 (MAX2837 on rad1o) * CLK5 -> MAX2837 (MAX2871 on rad1o) * CLK6 -> none * CLK7 -> LPC43xx (uses a 12MHz crystal by default) */ /* MS4/CLK4 is the source for the RFFC5071 mixer (MAX2837 on rad1o). */ si5351c_configure_multisynth(&clock_gen, 4, 20*128-512, 0, 1, 0); /* 800/20 = 40MHz */ /* MS5/CLK5 is the source for the MAX2837 clock input (MAX2871 on rad1o). */ si5351c_configure_multisynth(&clock_gen, 5, 20*128-512, 0, 1, 0); /* 800/20 = 40MHz */ /* MS6/CLK6 is unused. */ /* MS7/CLK7 is unused. */ /* Set to 10 MHz, the common rate between Jawbreaker and HackRF One. */ sample_rate_set(10000000); si5351c_set_clock_source(&clock_gen, PLL_SOURCE_XTAL); // soft reset // uint8_t resetdata[] = { 177, 0xac }; // si5351c_write(&clock_gen, resetdata, sizeof(resetdata)); si5351c_reset_pll(&clock_gen); si5351c_enable_clock_outputs(&clock_gen); //FIXME disable I2C /* Kick I2C0 down to 400kHz when we switch over to APB1 clock = 204MHz */ i2c_bus_start(clock_gen.bus, &i2c_config_si5351c_fast_clock); /* * 12MHz clock is entering LPC XTAL1/OSC input now. * On HackRF One and Jawbreaker, there is a 12 MHz crystal at the LPC. * Set up PLL1 to run from XTAL1 input. */ //FIXME a lot of the details here should be in a CGU driver /* set xtal oscillator to low frequency mode */ CGU_XTAL_OSC_CTRL &= ~CGU_XTAL_OSC_CTRL_HF_MASK; /* power on the oscillator and wait until stable */ CGU_XTAL_OSC_CTRL &= ~CGU_XTAL_OSC_CTRL_ENABLE_MASK; /* Wait about 100us after Crystal Power ON */ delay(WAIT_CPU_CLOCK_INIT_DELAY); /* use XTAL_OSC as clock source for BASE_M4_CLK (CPU) */ CGU_BASE_M4_CLK = (CGU_BASE_M4_CLK_CLK_SEL(CGU_SRC_XTAL) | CGU_BASE_M4_CLK_AUTOBLOCK(1)); /* use XTAL_OSC as clock source for APB1 */ CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_AUTOBLOCK(1) | CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_XTAL); /* use XTAL_OSC as clock source for APB3 */ CGU_BASE_APB3_CLK = CGU_BASE_APB3_CLK_AUTOBLOCK(1) | CGU_BASE_APB3_CLK_CLK_SEL(CGU_SRC_XTAL); cpu_clock_pll1_low_speed(); /* use PLL1 as clock source for BASE_M4_CLK (CPU) */ CGU_BASE_M4_CLK = (CGU_BASE_M4_CLK_CLK_SEL(CGU_SRC_PLL1) | CGU_BASE_M4_CLK_AUTOBLOCK(1)); /* use XTAL_OSC as clock source for PLL0USB */ CGU_PLL0USB_CTRL = CGU_PLL0USB_CTRL_PD(1) | CGU_PLL0USB_CTRL_AUTOBLOCK(1) | CGU_PLL0USB_CTRL_CLK_SEL(CGU_SRC_XTAL); while (CGU_PLL0USB_STAT & CGU_PLL0USB_STAT_LOCK_MASK); /* configure PLL0USB to produce 480 MHz clock from 12 MHz XTAL_OSC */ /* Values from User Manual v1.4 Table 94, for 12MHz oscillator. */ CGU_PLL0USB_MDIV = 0x06167FFA; CGU_PLL0USB_NP_DIV = 0x00302062; CGU_PLL0USB_CTRL |= (CGU_PLL0USB_CTRL_PD(1) | CGU_PLL0USB_CTRL_DIRECTI(1) | CGU_PLL0USB_CTRL_DIRECTO(1) | CGU_PLL0USB_CTRL_CLKEN(1)); /* power on PLL0USB and wait until stable */ CGU_PLL0USB_CTRL &= ~CGU_PLL0USB_CTRL_PD_MASK; while (!(CGU_PLL0USB_STAT & CGU_PLL0USB_STAT_LOCK_MASK)); /* use PLL0USB as clock source for USB0 */ CGU_BASE_USB0_CLK = CGU_BASE_USB0_CLK_AUTOBLOCK(1) | CGU_BASE_USB0_CLK_CLK_SEL(CGU_SRC_PLL0USB); /* Switch peripheral clock over to use PLL1 (204MHz) */ CGU_BASE_PERIPH_CLK = CGU_BASE_PERIPH_CLK_AUTOBLOCK(1) | CGU_BASE_PERIPH_CLK_CLK_SEL(CGU_SRC_PLL1); /* Switch APB1 clock over to use PLL1 (204MHz) */ CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_AUTOBLOCK(1) | CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_PLL1); /* Switch APB3 clock over to use PLL1 (204MHz) */ CGU_BASE_APB3_CLK = CGU_BASE_APB3_CLK_AUTOBLOCK(1) | CGU_BASE_APB3_CLK_CLK_SEL(CGU_SRC_PLL1); CGU_BASE_SSP0_CLK = CGU_BASE_SSP0_CLK_AUTOBLOCK(1) | CGU_BASE_SSP0_CLK_CLK_SEL(CGU_SRC_PLL1); CGU_BASE_SSP1_CLK = CGU_BASE_SSP1_CLK_AUTOBLOCK(1) | CGU_BASE_SSP1_CLK_CLK_SEL(CGU_SRC_PLL1); #if (defined JAWBREAKER || defined HACKRF_ONE) /* Disable unused clocks */ /* Start with PLLs */ CGU_PLL0AUDIO_CTRL = CGU_PLL0AUDIO_CTRL_PD(1); /* Dividers */ CGU_IDIVA_CTRL = CGU_IDIVA_CTRL_PD(1); CGU_IDIVB_CTRL = CGU_IDIVB_CTRL_PD(1); CGU_IDIVC_CTRL = CGU_IDIVC_CTRL_PD(1); CGU_IDIVD_CTRL = CGU_IDIVD_CTRL_PD(1); CGU_IDIVE_CTRL = CGU_IDIVE_CTRL_PD(1); /* Base clocks */ CGU_BASE_SPIFI_CLK = CGU_BASE_SPIFI_CLK_PD(1); /* SPIFI is only used at boot */ CGU_BASE_USB1_CLK = CGU_BASE_USB1_CLK_PD(1); /* USB1 is not exposed on HackRF */ CGU_BASE_PHY_RX_CLK = CGU_BASE_PHY_RX_CLK_PD(1); CGU_BASE_PHY_TX_CLK = CGU_BASE_PHY_TX_CLK_PD(1); CGU_BASE_LCD_CLK = CGU_BASE_LCD_CLK_PD(1); CGU_BASE_VADC_CLK = CGU_BASE_VADC_CLK_PD(1); CGU_BASE_SDIO_CLK = CGU_BASE_SDIO_CLK_PD(1); CGU_BASE_UART0_CLK = CGU_BASE_UART0_CLK_PD(1); CGU_BASE_UART1_CLK = CGU_BASE_UART1_CLK_PD(1); CGU_BASE_UART2_CLK = CGU_BASE_UART2_CLK_PD(1); CGU_BASE_UART3_CLK = CGU_BASE_UART3_CLK_PD(1); CGU_BASE_OUT_CLK = CGU_BASE_OUT_CLK_PD(1); CGU_BASE_AUDIO_CLK = CGU_BASE_AUDIO_CLK_PD(1); CGU_BASE_CGU_OUT0_CLK = CGU_BASE_CGU_OUT0_CLK_PD(1); CGU_BASE_CGU_OUT1_CLK = CGU_BASE_CGU_OUT1_CLK_PD(1); /* Disable unused peripheral clocks */ CCU1_CLK_APB1_CAN1_CFG = 0; CCU1_CLK_APB1_I2S_CFG = 0; CCU1_CLK_APB1_MOTOCONPWM_CFG = 0; CCU1_CLK_APB3_ADC0_CFG = 0; CCU1_CLK_APB3_ADC1_CFG = 0; CCU1_CLK_APB3_CAN0_CFG = 0; CCU1_CLK_APB3_DAC_CFG = 0; CCU1_CLK_M4_DMA_CFG = 0; CCU1_CLK_M4_EMC_CFG = 0; CCU1_CLK_M4_EMCDIV_CFG = 0; CCU1_CLK_M4_ETHERNET_CFG = 0; CCU1_CLK_M4_LCD_CFG = 0; CCU1_CLK_M4_QEI_CFG = 0; CCU1_CLK_M4_RITIMER_CFG = 0; CCU1_CLK_M4_SCT_CFG = 0; CCU1_CLK_M4_SDIO_CFG = 0; CCU1_CLK_M4_SPIFI_CFG = 0; CCU1_CLK_M4_TIMER0_CFG = 0; CCU1_CLK_M4_TIMER1_CFG = 0; CCU1_CLK_M4_TIMER2_CFG = 0; CCU1_CLK_M4_TIMER3_CFG = 0; CCU1_CLK_M4_UART1_CFG = 0; CCU1_CLK_M4_USART0_CFG = 0; CCU1_CLK_M4_USART2_CFG = 0; CCU1_CLK_M4_USART3_CFG = 0; CCU1_CLK_M4_USB1_CFG = 0; CCU1_CLK_M4_VADC_CFG = 0; // CCU1_CLK_SPIFI_CFG = 0; // CCU1_CLK_USB1_CFG = 0; // CCU1_CLK_VADC_CFG = 0; // CCU2_CLK_APB0_UART1_CFG = 0; // CCU2_CLK_APB0_USART0_CFG = 0; // CCU2_CLK_APB2_USART2_CFG = 0; // CCU2_CLK_APB2_USART3_CFG = 0; // CCU2_CLK_APLL_CFG = 0; // CCU2_CLK_SDIO_CFG = 0; #endif #ifdef RAD1O /* Disable unused clock outputs. They generate noise. */ scu_pinmux(CLK0, SCU_CLK_IN | SCU_CONF_FUNCTION7); scu_pinmux(CLK2, SCU_CLK_IN | SCU_CONF_FUNCTION7); #endif }
bool sample_rate_frac_set(uint32_t rate_num, uint32_t rate_denom) { const uint64_t VCO_FREQ = 800 * 1000 * 1000; /* 800 MHz */ uint32_t MSx_P1,MSx_P2,MSx_P3; uint32_t a, b, c; uint32_t rem; hackrf_ui_setSampleRate(rate_num/2); /* Find best config */ a = (VCO_FREQ * rate_denom) / rate_num; rem = (VCO_FREQ * rate_denom) - (a * rate_num); if (!rem) { /* Integer mode */ b = 0; c = 1; } else { /* Fractional */ uint32_t g = gcd(rem, rate_num); rem /= g; rate_num /= g; if (rate_num < (1<<20)) { /* Perfect match */ b = rem; c = rate_num; } else { /* Approximate */ c = (1<<20) - 1; b = ((uint64_t)c * (uint64_t)rem) / rate_num; g = gcd(b, c); b /= g; c /= g; } } /* Can we enable integer mode ? */ if (a & 0x1 || b) si5351c_set_int_mode(&clock_gen, 0, 0); else si5351c_set_int_mode(&clock_gen, 0, 1); /* Final MS values */ MSx_P1 = 128*a + (128 * b/c) - 512; MSx_P2 = (128*b) % c; MSx_P3 = c; /* MS0/CLK0 is the source for the MAX5864/CPLD (CODEC_CLK). */ si5351c_configure_multisynth(&clock_gen, 0, MSx_P1, MSx_P2, MSx_P3, 1); /* MS0/CLK1 is the source for the CPLD (CODEC_X2_CLK). */ si5351c_configure_multisynth(&clock_gen, 1, 0, 0, 0, 0);//p1 doesn't matter /* MS0/CLK2 is the source for SGPIO (CODEC_X2_CLK) */ si5351c_configure_multisynth(&clock_gen, 2, 0, 0, 0, 0);//p1 doesn't matter return true; }