t_stat tti_svc (UNIT *uptr)
{
int32 c;
uptr->wait = sim_rtcn_calb (POLL_RATE, TMR_POLL); /* calibrate poll timer */
sim_activate (uptr, uptr->wait); /* continue poll */
tty_shin = 0377; /* assume inactive */
if (tty_lf) { /* auto lf pending? */
c = 012; /* force lf */
tty_lf = 0;
}
else {
if ((c = sim_poll_kbd ()) < SCPE_KFLAG) return c; /* no char or error? */
if (c & SCPE_BREAK) c = 0; /* break? */
else c = sim_tt_inpcvt (c, TT_GET_MODE (uptr->flags));
tty_lf = ((c & 0177) == 015) && (uptr->flags & UNIT_AUTOLF);
}
if (tty_mode & TM_KBD) { /* keyboard enabled? */
tty_buf = c; /* put char in buf */
uptr->pos = uptr->pos + 1;
ttyio (&tty_dib, ioENF, 0); /* set flag */
if (c) {
tto_out (c); /* echo? */
return ttp_out (c); /* punch? */
}
}
else tty_shin = c; /* no, char shifts in */
return SCPE_OK;
}
t_stat rtc_svc (UNIT *uptr)
{
uint32 i, idx;
int32 t;
t_stat st;
t = sim_rtcn_calb (RTC_HZ_BASE, TMR_RTC); /* calibrate clock */
sim_activate (uptr, t); /* reactivate unit */
for (i = 0; i < RTC_NUM_EVNTS; i++) { /* loop thru events */
if (rtc_cntr[i] != 0) { /* event active? */
rtc_cntr[i] = rtc_cntr[i] - 1; /* decrement */
if (rtc_cntr[i] == 0) { /* expired? */
idx = rtc_indx[i];
rtc_cntr[i] = rtc_tab[idx].cntr_reset; /* reset counter */
if (rtc_xtra[i] != 0) { /* fudge factor? */
rtc_xtra[i] = rtc_xtra[i] - 1; /* decr fudge cntr */
if (rtc_xtra[i] == 0) { /* expired? */
rtc_cntr[i]++; /* extra tick */
rtc_xtra[i] = rtc_tab[idx].xtra_reset; /* reset fudge cntr */
} /* end fudge = 0 */
} /* end fudge active */
if ((rtc_usrv[i] == NULL) || /* registered? */
(rtc_usrv[i]->action == NULL))
return SCPE_IERR; /* should be */
st = rtc_usrv[i]->action (rtc_usrv[i]); /* callback */
if (st != SCPE_OK) /* error */
return st;
} /* end cntr = 0 */
} /* end event active */
} /* end event loop */
return SCPE_OK;
}
t_stat clk_svc (UNIT *uptr)
{
tmr_poll = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */
sim_activate_after (uptr, 1000000/clk_tps); /* reactivate unit */
tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */
AIO_SET_INTERRUPT_LATENCY(tmr_poll*clk_tps); /* set interrrupt latency */
return SCPE_OK;
}
static t_stat clk_service (UNIT *uptr)
{
dprintf (clk_dev, DEB_PSERV, "Service entered with counter %u increment %u limit %u\n",
count_register, increment, limit_register);
prescaler = prescaler - 1; /* decrement the prescaler count */
if (prescaler == 0) { /* if the prescaler count has expired */
count_register = count_register + increment & R_MASK; /* then the count register counts up */
if (count_register == limit_register) { /* if the limit has been reached */
if (limit_irq == SET) /* then if the last limit interrupt wasn't serviced */
lost_tick_irq = SET; /* then set the overflow interrupt */
else /* otherwise */
limit_irq = SET; /* set the limit interrupt */
if (control_word & CN_COUNT_RESET) /* if the counter reset option is selected */
count_register = 0; /* then clear the count register */
if (control_word & CN_IRQ_ENABLE /* if clock interrupts are enabled */
&& clk_dib.interrupt_active == CLEAR) { /* and the interrupt active flip-flop is clear */
clk_dib.interrupt_request = SET; /* then request an interrupt */
iop_assert_INTREQ (&clk_dib); /* and notify the IOP of the INTREQ signal */
}
}
if (uptr->flags & UNIT_CALTIME) /* if in calibrated timing mode */
prescaler = scale [rate]; /* then reset the prescaler */
else /* otherwise */
prescaler = 1; /* the prescaler isn't used */
}
if (!(uptr->flags & UNIT_CALTIME)) { /* if the clock is in real timing mode */
uptr->wait = delay [rate]; /* then set an event-based delay */
increment = 1; /* equal to the selected period */
coscheduled = FALSE; /* the clock is not coscheduled with the process clock */
}
else if (coschedulable && cpu_is_calibrated) { /* otherwise if the process clock is calibrated */
uptr->wait = sim_activate_time (cpu_pclk_uptr); /* then synchronize with it */
increment = CLK_MULTIPLIER; /* at one-tenth of the selected period */
coscheduled = TRUE; /* the clock is coscheduled with the process clock */
}
else { /* otherwise */
uptr->wait = sim_rtcn_calb (ticks [rate], TMR_CLK); /* calibrate the clock to a delay */
increment = 1; /* equal to the selected period */
coscheduled = FALSE; /* the clock is not coscheduled with the process clock */
}
dprintf (clk_dev, DEB_PSERV, "Rate %s delay %d service %s\n",
rate_name [rate], uptr->wait,
(coscheduled ? "coscheduled" : "scheduled"));
return sim_activate (uptr, uptr->wait); /* activate the unit and return the status */
}
void tmr_sched (uint32 nicr)
{
uint32 usecs = (nicr) ? (~nicr + 1) : 0xFFFFFFFF;
clk_tps = (int32)((1000000.0 / usecs) + 0.5);
sim_debug (TMR_DB_SCHED, &tmr_dev, "tmr_sched(nicr=0x%08X-usecs=0x%08X) - tps=%d\n", nicr, usecs, clk_tps);
tmr_poll = sim_rtcn_calb (clk_tps, TMR_CLK);
sim_activate_after (&tmr_unit, usecs);
}
t_stat clk_svc (UNIT *uptr)
{
tmr_poll = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */
sim_activate (&clk_unit, tmr_poll); /* reactivate unit */
tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */
todr_reg = todr_reg + 1; /* incr TODR */
if ((tmr_iccs & TMR_CSR_RUN) && tmr_use_100hz) /* timer on, std intvl? */
tmr_incr (TMR_INC); /* do timer service */
return SCPE_OK;
}
t_stat clk_svc (UNIT *uptr)
{
tmr_poll = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */
sim_activate_after (uptr, 1000000/clk_tps); /* reactivate unit */
tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */
AIO_SET_INTERRUPT_LATENCY(tmr_poll*clk_tps); /* set interrrupt latency */
if ((tmr_iccs & TMR_CSR_RUN) && tmr_use_100hz) /* timer on, std intvl? */
tmr_incr (TMR_INC); /* do timer service */
return SCPE_OK;
}
t_stat clk_svc (UNIT *uptr)
{
int32 t;
dev_done = dev_done | INT_CLK; /* set done */
int_req = INT_UPDATE; /* update interrupts */
t = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */
sim_activate (&clk_unit, t); /* reactivate unit */
tmxr_poll = t; /* set mux poll */
return SCPE_OK;
}
t_stat pclk_svc (UNIT *uptr)
{
int32 rv;
pclk_tick (); /* tick clock */
if ((pclk_csr & CSR_GO) == 0) /* done? */
return SCPE_OK;
rv = CSR_GETRATE (pclk_csr); /* get rate */
sim_activate (&pclk_unit, sim_rtcn_calb (rate[rv], TMR_PCLK));
return SCPE_OK;
}
void tmr_sched (uint32 nicr)
{
uint32 usecs = (nicr) ? (~nicr + 1) : 0xFFFFFFFF;
clk_tps = 1000000 / usecs;
sim_debug (TMR_DB_SCHED, &tmr_dev, "tmr_sched(nicr=0x%08X-usecs=0x%08X) - tps=%d\n", nicr, usecs, clk_tps);
tmr_poll = sim_rtcn_calb (clk_tps, TMR_CLK);
if (SCPE_OK == sim_activate_after (&tmr_unit, usecs))
tmr_sav = sim_grtime(); /* Save interval base time */
}
t_stat clk_svc (UNIT *uptr)
{
int32 t;
clk_csr = clk_csr | CSR_DONE; /* set done */
if ((clk_csr & CSR_IE) || clk_fie) SET_INT (CLK);
t = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */
sim_activate (&clk_unit, t); /* reactivate unit */
tmr_poll = t; /* set timer poll */
tmxr_poll = t; /* set mux poll */
return SCPE_OK;
}
static t_stat clk_svc (UNUSED UNIT * up)
{
// only valid for TR
#ifdef USE_IDLE
sim_activate (& TR_clk_unit [0], sim_rtcn_init(CLK_TR_HZ, TR_CLK));
#else
(void) sim_rtcn_calb (CLK_TR_HZ, TR_CLK); // calibrate clock
#endif
uint32 t = sim_is_active(&TR_clk_unit[0]);
sim_debug (DBG_INFO, & clk_dev, "clk_svc: TR has %d time units left\n", t);
return 0;
}
void iccs_wr (int32 val)
{
sim_debug_bits_hdr (TMR_DB_REG, &tmr_dev, "iccs_wr()", tmr_iccs_bits, tmr_iccs, val, TRUE);
if ((val & TMR_CSR_RUN) == 0) { /* clearing run? */
if (tmr_iccs & TMR_CSR_RUN) { /* run 1 -> 0? */
tmr_icr = icr_rd (); /* update itr */
sim_rtcn_calb (0, TMR_CLK); /* stop timer */
}
sim_cancel (&tmr_unit); /* cancel timer */
}
if (val & CSR_DONE) /* Interrupt Acked? */
sim_rtcn_tick_ack (20, TMR_CLK); /* Let timers know */
tmr_iccs = tmr_iccs & ~(val & TMR_CSR_W1C); /* W1C csr */
tmr_iccs = (tmr_iccs & ~TMR_CSR_WR) | /* new r/w */
(val & TMR_CSR_WR);
if (val & TMR_CSR_XFR) /* xfr set? */
tmr_icr = tmr_nicr;
if (val & TMR_CSR_RUN) { /* run? */
if (val & TMR_CSR_XFR) /* new tir? */
sim_cancel (&tmr_unit); /* stop prev */
if (!sim_is_active (&tmr_unit)) { /* not running? */
sim_rtcn_init_unit (&tmr_unit, CLK_DELAY, TMR_CLK); /* init timer */
tmr_sched (tmr_icr); /* activate */
}
}
else {
if (val & TMR_CSR_XFR) /* xfr set? */
tmr_icr = tmr_nicr;
if (val & TMR_CSR_SGL) { /* single step? */
tmr_icr = tmr_icr + 1; /* incr tmr */
if (tmr_icr == 0) { /* if ovflo, */
if (tmr_iccs & TMR_CSR_DON) /* done? set err */
tmr_iccs = tmr_iccs | TMR_CSR_ERR;
else
tmr_iccs = tmr_iccs | TMR_CSR_DON; /* set done */
if (tmr_iccs & TMR_CSR_IE) { /* ie? */
tmr_int = 1; /* set int req */
sim_debug (TMR_DB_INT, &tmr_dev, "tmr_incr() - INT=1\n");
}
tmr_icr = tmr_nicr; /* reload tir */
}
}
}
if ((tmr_iccs & (TMR_CSR_DON | TMR_CSR_IE)) != /* update int */
(TMR_CSR_DON | TMR_CSR_IE)) {
if (tmr_int) {
tmr_int = 0;
sim_debug (TMR_DB_INT, &tmr_dev, "iccs_wr() - INT=0\n");
}
}
}
t_stat clk_svc (UNIT *uptr)
{
int32 t;
if (clk_csr & CSR_IE)
SET_INT (CLK);
t = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */
sim_activate_after (&clk_unit, 1000000/clk_tps); /* reactivate unit */
tmr_poll = t; /* set tmr poll */
tmxr_poll = t * TMXR_MULT; /* set mux poll */
if (!todr_blow && todr_reg) /* if running? */
todr_reg = todr_reg + 1; /* incr TODR */
return SCPE_OK;
}
t_stat clk_svc (UNIT *uptr)
{
if (clk_dev.flags & DEV_DIS) /* disabled? */
return SCPE_OK;
tmxr_poll = sim_rtcn_calb (CLK_TPS, TMR_CLK); /* calibrate clock */
sim_activate (&clk_unit, tmxr_poll); /* reactivate unit */
clk_cntr = clk_cntr + CLK_CNTS; /* incr counter */
if ((clk_cntr % CLK_C32MS) == 0) /* 32ms interval? */
dev_req_int (clk32ms_sbs); /* req intr */
if (clk_cntr >= CLK_C1MIN) { /* 1min interval? */
dev_req_int (clk1min_sbs); /* req intr */
clk_cntr = 0; /* reset counter */
}
return SCPE_OK;
}
t_stat XX_clk_svc(UNIT *up)
{
// only valid for TR
#if 0
tmr_poll = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */
sim_activate (&clk_unit, tmr_poll); /* reactivate unit */
tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */
todr_reg = todr_reg + 1; /* incr TODR */
if ((tmr_iccs & TMR_CSR_RUN) && tmr_use_100hz) /* timer on, std intvl? */
tmr_incr (TMR_INC); /* do timer service */
return 0;
#else
return 2;
#endif
}
t_stat clk_svc (UNIT *uptr)
{
if (!clk.control) /* control clear? */
return SCPE_OK; /* done */
if (clk_unit.flags & UNIT_DIAG) /* diag mode? */
clk_tick = clk_delay (0); /* get fixed delay */
else if (clk_select == 2) /* 10 msec period? */
clk_tick = sync_poll (SERVICE); /* sync poll */
else
clk_tick = sim_rtcn_calb (clk_tps[clk_select], TMR_CLK); /* calibrate delay */
sim_activate (uptr, clk_tick); /* reactivate */
clk_ctr = clk_ctr - 1; /* decrement counter */
if (clk_ctr <= 0) { /* end of interval? */
if (clk.flag)
clk_error = CLK_ERROR; /* overrun? error */
else
clkio (&clk_dib, ioENF, 0); /* set flag */
clk_ctr = clk_delay (1); /* reset counter */
}
return SCPE_OK;
}
