/*
* This function set up the main chip clock.
*
* Input: Frequency to be set.
*/
static void set_chip_clock(unsigned int frequency)
{
struct pll_value pll;
unsigned int ulActualMxClk;
/* Cheok_0509: For SM750LE, the chip clock is fixed. Nothing to set. */
if (sm750_get_chip_type() == SM750LE)
return;
if (frequency) {
/*
* Set up PLL structure to hold the value to be set in clocks.
*/
pll.inputFreq = DEFAULT_INPUT_CLOCK; /* Defined in CLOCK.H */
pll.clockType = MXCLK_PLL;
/*
* Call sm750_calc_pll_value() to fill the other fields
* of the PLL structure. Sometimes, the chip cannot set
* up the exact clock required by the User.
* Return value of sm750_calc_pll_value gives the actual
* possible clock.
*/
ulActualMxClk = sm750_calc_pll_value(frequency, &pll);
/* Master Clock Control: MXCLK_PLL */
poke32(MXCLK_PLL_CTRL, sm750_format_pll_reg(&pll));
}
}
unsigned int ddk750_get_vm_size(void)
{
unsigned int reg;
unsigned int data;
/* sm750le only use 64 mb memory*/
if (sm750_get_chip_type() == SM750LE)
return SZ_64M;
/* for 750,always use power mode0*/
reg = peek32(MODE0_GATE);
reg |= MODE0_GATE_GPIO;
poke32(MODE0_GATE, reg);
/* get frame buffer size from GPIO */
reg = peek32(MISC_CTRL) & MISC_CTRL_LOCALMEM_SIZE_MASK;
switch (reg) {
case MISC_CTRL_LOCALMEM_SIZE_8M:
data = SZ_8M; break; /* 8 Mega byte */
case MISC_CTRL_LOCALMEM_SIZE_16M:
data = SZ_16M; break; /* 16 Mega byte */
case MISC_CTRL_LOCALMEM_SIZE_32M:
data = SZ_32M; break; /* 32 Mega byte */
case MISC_CTRL_LOCALMEM_SIZE_64M:
data = SZ_64M; break; /* 64 Mega byte */
default:
data = 0;
break;
}
return data;
}
void ddk750_set_dpms(DPMS_t state)
{
unsigned int value;
if (sm750_get_chip_type() == SM750LE) {
value = peek32(CRT_DISPLAY_CTRL) & ~CRT_DISPLAY_CTRL_DPMS_MASK;
value |= (state << CRT_DISPLAY_CTRL_DPMS_SHIFT);
poke32(CRT_DISPLAY_CTRL, value);
} else {
value = peek32(SYSTEM_CTRL);
value = (value & ~SYSTEM_CTRL_DPMS_MASK) | state;
poke32(SYSTEM_CTRL, value);
}
}
/*
* This function initializes the i2c attributes and bus
*
* Parameters:
* clk_gpio - The GPIO pin to be used as i2c SCL
* data_gpio - The GPIO pin to be used as i2c SDA
*
* Return Value:
* -1 - Fail to initialize the i2c
* 0 - Success
*/
long sm750_sw_i2c_init(
unsigned char clk_gpio,
unsigned char data_gpio
)
{
int i;
/*
* Return 0 if the GPIO pins to be used is out of range. The
* range is only from [0..63]
*/
if ((clk_gpio > 31) || (data_gpio > 31))
return -1;
if (sm750_get_chip_type() == SM750LE)
return sm750le_i2c_init(clk_gpio, data_gpio);
/* Initialize the GPIO pin for the i2c Clock Register */
sw_i2c_clk_gpio_mux_reg = GPIO_MUX;
sw_i2c_clk_gpio_data_reg = GPIO_DATA;
sw_i2c_clk_gpio_data_dir_reg = GPIO_DATA_DIRECTION;
/* Initialize the Clock GPIO Offset */
sw_i2c_clk_gpio = clk_gpio;
/* Initialize the GPIO pin for the i2c Data Register */
sw_i2c_data_gpio_mux_reg = GPIO_MUX;
sw_i2c_data_gpio_data_reg = GPIO_DATA;
sw_i2c_data_gpio_data_dir_reg = GPIO_DATA_DIRECTION;
/* Initialize the Data GPIO Offset */
sw_i2c_data_gpio = data_gpio;
/* Enable the GPIO pins for the i2c Clock and Data (GPIO MUX) */
POKE32(sw_i2c_clk_gpio_mux_reg,
PEEK32(sw_i2c_clk_gpio_mux_reg) & ~(1 << sw_i2c_clk_gpio));
POKE32(sw_i2c_data_gpio_mux_reg,
PEEK32(sw_i2c_data_gpio_mux_reg) & ~(1 << sw_i2c_data_gpio));
/* Enable GPIO power */
sm750_enable_gpio(1);
/* Clear the i2c lines. */
for (i = 0; i < 9; i++)
sw_i2c_stop();
return 0;
}
static unsigned int get_mxclk_freq(void)
{
unsigned int pll_reg;
unsigned int M, N, OD, POD;
if (sm750_get_chip_type() == SM750LE)
return MHz(130);
pll_reg = peek32(MXCLK_PLL_CTRL);
M = (pll_reg & PLL_CTRL_M_MASK) >> PLL_CTRL_M_SHIFT;
N = (pll_reg & PLL_CTRL_N_MASK) >> PLL_CTRL_M_SHIFT;
OD = (pll_reg & PLL_CTRL_OD_MASK) >> PLL_CTRL_OD_SHIFT;
POD = (pll_reg & PLL_CTRL_POD_MASK) >> PLL_CTRL_POD_SHIFT;
return DEFAULT_INPUT_CLOCK * M / N / (1 << OD) / (1 << POD);
}
static void set_memory_clock(unsigned int frequency)
{
unsigned int reg, divisor;
/*
* Cheok_0509: For SM750LE, the memory clock is fixed.
* Nothing to set.
*/
if (sm750_get_chip_type() == SM750LE)
return;
if (frequency) {
/*
* Set the frequency to the maximum frequency
* that the DDR Memory can take which is 336MHz.
*/
if (frequency > MHz(336))
frequency = MHz(336);
/* Calculate the divisor */
divisor = DIV_ROUND_CLOSEST(get_mxclk_freq(), frequency);
/* Set the corresponding divisor in the register. */
reg = peek32(CURRENT_GATE) & ~CURRENT_GATE_M2XCLK_MASK;
switch (divisor) {
default:
case 1:
reg |= CURRENT_GATE_M2XCLK_DIV_1;
break;
case 2:
reg |= CURRENT_GATE_M2XCLK_DIV_2;
break;
case 3:
reg |= CURRENT_GATE_M2XCLK_DIV_3;
break;
case 4:
reg |= CURRENT_GATE_M2XCLK_DIV_4;
break;
}
sm750_set_current_gate(reg);
}
}
/*
* SM50x can operate in one of three modes: 0, 1 or Sleep.
* On hardware reset, power mode 0 is default.
*/
void sm750_set_power_mode(unsigned int mode)
{
unsigned int ctrl = 0;
ctrl = peek32(POWER_MODE_CTRL) & ~POWER_MODE_CTRL_MODE_MASK;
if (sm750_get_chip_type() == SM750LE)
return;
switch (mode) {
case POWER_MODE_CTRL_MODE_MODE0:
ctrl |= POWER_MODE_CTRL_MODE_MODE0;
break;
case POWER_MODE_CTRL_MODE_MODE1:
ctrl |= POWER_MODE_CTRL_MODE_MODE1;
break;
case POWER_MODE_CTRL_MODE_SLEEP:
ctrl |= POWER_MODE_CTRL_MODE_SLEEP;
break;
default:
break;
}
/* Set up other fields in Power Control Register */
if (mode == POWER_MODE_CTRL_MODE_SLEEP) {
ctrl &= ~POWER_MODE_CTRL_OSC_INPUT;
#ifdef VALIDATION_CHIP
ctrl &= ~POWER_MODE_CTRL_336CLK;
#endif
} else {
ctrl |= POWER_MODE_CTRL_OSC_INPUT;
#ifdef VALIDATION_CHIP
ctrl |= POWER_MODE_CTRL_336CLK;
#endif
}
/* Program new power mode. */
poke32(POWER_MODE_CTRL, ctrl);
}
static unsigned int get_power_mode(void)
{
if (sm750_get_chip_type() == SM750LE)
return 0;
return peek32(POWER_MODE_CTRL) & POWER_MODE_CTRL_MODE_MASK;
}
/*
* monk liu @ 4/6/2011:
* re-write the calculatePLL function of ddk750.
* the original version function does not use
* some mathematics tricks and shortcut
* when it doing the calculation of the best N,M,D combination
* I think this version gives a little upgrade in speed
*
* 750 pll clock formular:
* Request Clock = (Input Clock * M )/(N * X)
*
* Input Clock = 14318181 hz
* X = 2 power D
* D ={0,1,2,3,4,5,6}
* M = {1,...,255}
* N = {2,...,15}
*/
unsigned int sm750_calc_pll_value(unsigned int request_orig, struct pll_value *pll)
{
/*
* as sm750 register definition,
* N located in 2,15 and M located in 1,255
*/
int N, M, X, d;
int mini_diff;
unsigned int RN, quo, rem, fl_quo;
unsigned int input, request;
unsigned int tmpClock, ret;
const int max_OD = 3;
int max_d = 6;
if (sm750_get_chip_type() == SM750LE) {
/*
* SM750LE don't have
* programmable PLL and M/N values to work on.
* Just return the requested clock.
*/
return request_orig;
}
ret = 0;
mini_diff = ~0;
request = request_orig / 1000;
input = pll->inputFreq / 1000;
/*
* for MXCLK register,
* no POD provided, so need be treated differently
*/
if (pll->clockType == MXCLK_PLL)
max_d = 3;
for (N = 15; N > 1; N--) {
/*
* RN will not exceed maximum long
* if @request <= 285 MHZ (for 32bit cpu)
*/
RN = N * request;
quo = RN / input;
rem = RN % input;/* rem always small than 14318181 */
fl_quo = rem * 10000 / input;
for (d = max_d; d >= 0; d--) {
X = BIT(d);
M = quo * X;
M += fl_quo * X / 10000;
/* round step */
M += (fl_quo * X % 10000) > 5000 ? 1 : 0;
if (M < 256 && M > 0) {
unsigned int diff;
tmpClock = pll->inputFreq * M / N / X;
diff = abs(tmpClock - request_orig);
if (diff < mini_diff) {
pll->M = M;
pll->N = N;
pll->POD = 0;
if (d > max_OD)
pll->POD = d - max_OD;
pll->OD = d - pll->POD;
mini_diff = diff;
ret = tmpClock;
}
}
}
}
return ret;
}
int ddk750_init_hw(struct initchip_param *pInitParam)
{
unsigned int reg;
if (pInitParam->powerMode != 0)
pInitParam->powerMode = 0;
sm750_set_power_mode(pInitParam->powerMode);
/* Enable display power gate & LOCALMEM power gate*/
reg = peek32(CURRENT_GATE);
reg |= (CURRENT_GATE_DISPLAY | CURRENT_GATE_LOCALMEM);
sm750_set_current_gate(reg);
if (sm750_get_chip_type() != SM750LE) {
/* set panel pll and graphic mode via mmio_88 */
reg = peek32(VGA_CONFIGURATION);
reg |= (VGA_CONFIGURATION_PLL | VGA_CONFIGURATION_MODE);
poke32(VGA_CONFIGURATION, reg);
} else {
#if defined(__i386__) || defined(__x86_64__)
/* set graphic mode via IO method */
outb_p(0x88, 0x3d4);
outb_p(0x06, 0x3d5);
#endif
}
/* Set the Main Chip Clock */
set_chip_clock(MHz((unsigned int)pInitParam->chipClock));
/* Set up memory clock. */
set_memory_clock(MHz(pInitParam->memClock));
/* Set up master clock */
set_master_clock(MHz(pInitParam->masterClock));
/*
* Reset the memory controller.
* If the memory controller is not reset in SM750,
* the system might hang when sw accesses the memory.
* The memory should be resetted after changing the MXCLK.
*/
if (pInitParam->resetMemory == 1) {
reg = peek32(MISC_CTRL);
reg &= ~MISC_CTRL_LOCALMEM_RESET;
poke32(MISC_CTRL, reg);
reg |= MISC_CTRL_LOCALMEM_RESET;
poke32(MISC_CTRL, reg);
}
if (pInitParam->setAllEngOff == 1) {
sm750_enable_2d_engine(0);
/* Disable Overlay, if a former application left it on */
reg = peek32(VIDEO_DISPLAY_CTRL);
reg &= ~DISPLAY_CTRL_PLANE;
poke32(VIDEO_DISPLAY_CTRL, reg);
/* Disable video alpha, if a former application left it on */
reg = peek32(VIDEO_ALPHA_DISPLAY_CTRL);
reg &= ~DISPLAY_CTRL_PLANE;
poke32(VIDEO_ALPHA_DISPLAY_CTRL, reg);
/* Disable alpha plane, if a former application left it on */
reg = peek32(ALPHA_DISPLAY_CTRL);
reg &= ~DISPLAY_CTRL_PLANE;
poke32(ALPHA_DISPLAY_CTRL, reg);
/* Disable DMA Channel, if a former application left it on */
reg = peek32(DMA_ABORT_INTERRUPT);
reg |= DMA_ABORT_INTERRUPT_ABORT_1;
poke32(DMA_ABORT_INTERRUPT, reg);
/* Disable DMA Power, if a former application left it on */
sm750_enable_dma(0);
}
/* We can add more initialization as needed. */
return 0;
}
