void mainboard_smi_sleep(u8 slp_typ)
{
/* Disable USB charging if required */
switch (slp_typ) {
case 3:
if (smm_get_gnvs()->s3u0 == 0)
google_chromeec_set_usb_charge_mode(
0, USB_CHARGE_MODE_DISABLED);
if (smm_get_gnvs()->s3u1 == 0)
google_chromeec_set_usb_charge_mode(
1, USB_CHARGE_MODE_DISABLED);
break;
case 5:
if (smm_get_gnvs()->s5u0 == 0)
google_chromeec_set_usb_charge_mode(
0, USB_CHARGE_MODE_DISABLED);
if (smm_get_gnvs()->s5u1 == 0)
google_chromeec_set_usb_charge_mode(
1, USB_CHARGE_MODE_DISABLED);
break;
}
/* Disable SCI and SMI events */
google_chromeec_set_smi_mask(0);
google_chromeec_set_sci_mask(0);
/* Clear pending events that may trigger immediate wake */
while (google_chromeec_get_event() != 0);
/* Enable wake events */
google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
}
void mainboard_smi_sleep(uint8_t slp_typ)
{
/* Disable USB charging if required */
switch (slp_typ) {
case 3:
#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
if (smm_get_gnvs()->s3u0 == 0)
google_chromeec_set_usb_charge_mode(
0, USB_CHARGE_MODE_DISABLED);
if (smm_get_gnvs()->s3u1 == 0)
google_chromeec_set_usb_charge_mode(
1, USB_CHARGE_MODE_DISABLED);
/* Enable wake events */
google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
#endif
/* Enable wake pin in GPE block. */
enable_gpe(WAKE_GPIO_EN);
break;
case 5:
#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
if (smm_get_gnvs()->s5u0 == 0)
google_chromeec_set_usb_charge_mode(
0, USB_CHARGE_MODE_DISABLED);
if (smm_get_gnvs()->s5u1 == 0)
google_chromeec_set_usb_charge_mode(
1, USB_CHARGE_MODE_DISABLED);
/* Enable wake events */
google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS);
#endif
break;
}
#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
/* Disable SCI and SMI events */
google_chromeec_set_smi_mask(0);
google_chromeec_set_sci_mask(0);
/* Clear pending events that may trigger immediate wake */
while (google_chromeec_get_event() != 0)
;
if (smm_get_gnvs()->bdid == BOARD_DVT) {
/* Set LPC lines to low power in S3/S5. */
if ((slp_typ == SLEEP_STATE_S3) || (slp_typ == SLEEP_STATE_S5))
lpc_set_low_power();
}
#endif
}
void mainboard_smi_sleep(u8 slp_typ)
{
/* Disable USB charging if required */
switch (slp_typ) {
case 3:
if (smm_get_gnvs()->s3u0 == 0) {
google_chromeec_set_usb_charge_mode(
0, USB_CHARGE_MODE_DISABLED);
google_chromeec_set_usb_charge_mode(
1, USB_CHARGE_MODE_DISABLED);
}
/* Put SSD in reset to prevent leak. */
set_gpio(SAMUS_GPIO_SSD_RESET_L, 0);
/* Prevent leak from standby rail to WLAN rail in S3. */
set_gpio(SAMUS_GPIO_WLAN_DISABLE_L, 0);
/* Disable LTE */
set_gpio(SAMUS_GPIO_LTE_DISABLE_L, 0);
/* Enable wake events */
google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
break;
case 5:
if (smm_get_gnvs()->s5u0 == 0) {
google_chromeec_set_usb_charge_mode(
0, USB_CHARGE_MODE_DISABLED);
google_chromeec_set_usb_charge_mode(
1, USB_CHARGE_MODE_DISABLED);
}
/* Put SSD in reset to prevent leak. */
set_gpio(SAMUS_GPIO_SSD_RESET_L, 0);
/* Prevent leak from standby rail to WLAN rail in S5. */
set_gpio(SAMUS_GPIO_WLAN_DISABLE_L, 0);
/* Disable LTE */
set_gpio(SAMUS_GPIO_LTE_DISABLE_L, 0);
/* Enable wake events */
google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS);
break;
}
/* Disable SCI and SMI events */
google_chromeec_set_smi_mask(0);
google_chromeec_set_sci_mask(0);
/* Clear pending events that may trigger immediate wake */
while (google_chromeec_get_event() != 0);
}
void mainboard_smi_sleep(u8 slp_typ)
{
printk(BIOS_DEBUG, "mainboard_smi_sleep: %x\n", slp_typ);
/* Tell the EC to Enable USB power for S3 if requested */
if (smm_get_gnvs()->s3u0 != 0 || smm_get_gnvs()->s3u1 != 0)
ec_mem_write(EC_EC_PSW, ec_mem_read(EC_EC_PSW) | EC_PSW_USB);
/* Disable wake on USB, LAN & RTC */
/* Enable Wake from Keyboard */
if ((slp_typ == 4) || (slp_typ == 5)) {
printk(BIOS_DEBUG, "Disabling wake on RTC\n");
ec_mem_write(EC_EC_PSW, EC_PSW_IKB);
}
}
void mainboard_smi_sleep(u8 slp_typ)
{
printk(BIOS_DEBUG, "mainboard_smi_sleep: %x\n", slp_typ);
/* Disable SCI and SMI events */
/* Clear pending events that may trigger immediate wake */
/* Enable wake events */
/* Tell the EC to Disable USB power */
if (smm_get_gnvs()->s3u0 == 0 && smm_get_gnvs()->s3u1 == 0) {
ec_kbc_write_cmd(0x45);
ec_kbc_write_ib(0xF2);
}
}
/* Inherited from cpu/x86/smm.h resulting in a different signature */
int southbridge_io_trap_handler(int smif)
{
global_nvs_t *gnvs = smm_get_gnvs();
switch (smif) {
case 0x32:
printk(BIOS_DEBUG, "OS Init\n");
/*
* gnvs->smif:
* - On success, the IO Trap Handler returns 0
* - On failure, the IO Trap Handler returns a value != 0
*/
gnvs->smif = 0;
return 1; /* IO trap handled */
}
/* Not handled */
return 0;
}
int mainboard_io_trap_handler(int smif)
{
switch (smif) {
case 0x99:
printk(BIOS_DEBUG, "Sample\n");
smm_get_gnvs()->smif = 0;
break;
default:
return 0;
}
/* On success, the IO Trap Handler returns 0
* On failure, the IO Trap Handler returns a value != 0
*
* For now, we force the return value to 0 and log all traps to
* see what's going on.
*/
return 1;
}
void mainboard_smi_sleep(uint8_t slp_typ)
{
void *addr;
uint32_t mask;
/* Disable USB charging if required */
switch (slp_typ) {
case 3:
#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
if (smm_get_gnvs()->s3u0 == 0)
google_chromeec_set_usb_charge_mode(
0, USB_CHARGE_MODE_DISABLED);
if (smm_get_gnvs()->s3u1 == 0)
google_chromeec_set_usb_charge_mode(
1, USB_CHARGE_MODE_DISABLED);
/* Enable wake events */
google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
#endif
/* Enable wake pin in GPE block. */
enable_gpe(WAKE_GPIO_EN);
break;
case 5:
#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
if (smm_get_gnvs()->s5u0 == 0)
google_chromeec_set_usb_charge_mode(
0, USB_CHARGE_MODE_DISABLED);
if (smm_get_gnvs()->s5u1 == 0)
google_chromeec_set_usb_charge_mode(
1, USB_CHARGE_MODE_DISABLED);
/* Enable wake events */
google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS);
#endif
/* Disabling wake from SUS_GPIO1 (TOUCH INT) and
* SUS_GPIO7 (TRACKPAD INT) in North bank as they are not
* valid S5 wake sources
*/
addr = (void *)(IO_BASE_ADDRESS + COMMUNITY_OFFSET_GPNORTH +
GPIO_WAKE_MASK_REG0);
mask = ~(GPIO_SUS1_WAKE_MASK | GPIO_SUS7_WAKE_MASK);
write32(addr, read32(addr) & mask);
break;
}
#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
/* Disable SCI and SMI events */
google_chromeec_set_smi_mask(0);
google_chromeec_set_sci_mask(0);
/* Clear pending events that may trigger immediate wake */
while (google_chromeec_get_event() != 0)
;
if (smm_get_gnvs()->bdid == BOARD_PRE_EVT) {
/* Set LPC lines to low power in S3/S5. */
if ((slp_typ == SLEEP_STATE_S3) || (slp_typ == SLEEP_STATE_S5))
lpc_set_low_power();
}
#endif
}
void smihandler_southbridge_monitor(
const struct smm_save_state_ops *save_state_ops)
{
#define IOTRAP(x) (trap_sts & (1 << x))
u32 trap_cycle;
u32 data, mask = 0;
u8 trap_sts;
int i;
global_nvs_t *gnvs = smm_get_gnvs();
/* TRSR - Trap Status Register */
trap_sts = pcr_read8(PID_PSTH, PCR_PSTH_TRPST);
/* Clear trap(s) in TRSR */
pcr_write8(PID_PSTH, PCR_PSTH_TRPST, trap_sts);
/* TRPC - Trapped cycle */
trap_cycle = pcr_read32(PID_PSTH, PCR_PSTH_TRPC);
for (i = 16; i < 20; i++) {
if (trap_cycle & (1 << i))
mask |= (0xff << ((i - 16) << 2));
}
/* IOTRAP(3) SMI function call */
if (IOTRAP(3)) {
if (gnvs && gnvs->smif)
io_trap_handler(gnvs->smif);
return;
}
/*
* IOTRAP(2) currently unused
* IOTRAP(1) currently unused
*/
/* IOTRAP(0) SMIC */
if (IOTRAP(0)) {
if (!(trap_cycle & (1 << 24))) { /* It's a write */
printk(BIOS_DEBUG, "SMI1 command\n");
/* Trapped write data */
data = pcr_read32(PID_PSTH, PCR_PSTH_TRPD);
data &= mask;
}
}
printk(BIOS_DEBUG, " trapped io address = 0x%x\n",
trap_cycle & 0xfffc);
for (i = 0; i < 4; i++)
if (IOTRAP(i))
printk(BIOS_DEBUG, " TRAP = %d\n", i);
printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf);
printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask);
printk(BIOS_DEBUG, " read/write: %s\n",
(trap_cycle & (1 << 24)) ? "read" : "write");
if (!(trap_cycle & (1 << 24))) {
/* Write Cycle */
data = pcr_read32(PID_PSTH, PCR_PSTH_TRPD);
printk(BIOS_DEBUG, " iotrap written data = 0x%08x\n", data);
}
#undef IOTRAP
}