static void *smp_write_config_table(void *v) { struct mp_config_table *mc; int isa_bus; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LAPIC_ADDR); smp_write_processors(mc); mptable_write_buses(mc, NULL, &isa_bus); /* I/O APICs: APIC ID Version State Address */ smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); /* Legacy Interrupts */ mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0); /* Builtin devices on Bus 0 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x8, 0x2, 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, 0x2, 0x13); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x2, 0x17); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x2, 0x13); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x76, 0x2, 0x12); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, 0x2, 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x6c, 0x2, 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x70, 0x2, 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x71, 0x2, 0x11); /* Firewire 4:0.0 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x0, 0x2, 0x10); // riser slot top 5:8.0 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x20, 0x2, 0x14); // riser slot middle 5:9.0 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x24, 0x2, 0x15); // riser slot bottom 5:a.0 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x28, 0x2, 0x16); /* Onboard Ethernet */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10); /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0); smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1); /* Compute the checksums */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc)); return smp_next_mpe_entry(mc); }
static void *smp_write_config_table(void *v) { int ioapic_id, ioapic_ver, isa_bus; struct mp_config_table *mc; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LAPIC_ADDR); smp_write_processors(mc); mptable_write_buses(mc, NULL, &isa_bus); ioapic_id = 2; ioapic_ver = 0x11; /* External Intel 82093AA IOAPIC. */ smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR); /* Legacy Interrupts */ mptable_add_isa_interrupts(mc, isa_bus, ioapic_id, 0); /* I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x13, ioapic_id, 0x13); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x18, ioapic_id, 0x13); /* Local Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */ smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 0x1, 0x0, MP_APIC_ALL, 0x0); smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 0x1, 0x0, MP_APIC_ALL, 0x1); /* Compute the checksums. */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc)); return smp_next_mpe_entry(mc); }
static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; static const char oem[8] = "COREBOOT"; static const char productid[12] = "TREX "; struct mp_config_table *mc; struct mb_sysconf_t *m; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); memset(mc, 0, sizeof(*mc)); memcpy(mc->mpc_signature, sig, sizeof(sig)); mc->mpc_length = sizeof(*mc); /* initially just the header */ mc->mpc_spec = 0x04; mc->mpc_checksum = 0; /* not yet computed */ memcpy(mc->mpc_oem, oem, sizeof(oem)); memcpy(mc->mpc_productid, productid, sizeof(productid)); mc->mpc_oemptr = 0; mc->mpc_oemsize = 0; mc->mpc_entry_count = 0; /* No entries yet... */ mc->mpc_lapic = LAPIC_ADDR; mc->mpe_length = 0; mc->mpe_checksum = 0; mc->reserved = 0; smp_write_processors(mc); get_bus_conf(); m = sysconf.mb; /*Bus: Bus ID Type*/ /* define bus and isa numbers */ #if 0 unsigned char bus_num; for(bus_num = 0; bus_num < m->bus_isa; bus_num++) { smp_write_bus(mc, bus_num, "PCI "); printk(BIOS_DEBUG, "writing bus %d as PCI...\n",bus_num); } #endif smp_write_bus(mc, 0, "PCI "); smp_write_bus(mc, 1, "PCI "); smp_write_bus(mc, 7, "PCI "); smp_write_bus(mc, 8, "PCI "); smp_write_bus(mc,m->bus_isa, "ISA "); printk(BIOS_DEBUG, "writing %d as ISA...\n",m->bus_isa); /*I/O APICs: APIC ID Version State Address*/ { device_t dev = 0; int i; struct resource *res; for(i=0; i<3; i++) { dev = dev_find_device(0x1166, 0x0235, dev); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { printk(BIOS_DEBUG, "APIC %d base address: %llx\n",m->apicid_bcm5785[i], res->base); smp_write_ioapic(mc, m->apicid_bcm5785[i], 0x11, res->base); } } } } /* IRQ routing as factory BIOS */ outb(0x01, 0xc00); outb(0x0A, 0xc01); outb(0x17, 0xc00); outb(0x05, 0xc01); /* outb(0x2E, 0xc00); outb(0x0B, 0xc01); */ /* outb(0x07, 0xc00); outb(0x07, 0xc01); */ outb(0x07, 0xc00); outb(0x0b, 0xc01); outb(0x24, 0xc00); outb(0x05, 0xc01); //outb(0x00, 0xc00); outb(0x09, 0xc01); outb(0x02, 0xc00); outb(0x0E, 0xc01); // 8259 registers... outb(0xa0, 0x4d0); outb(0x0e, 0x4d1); { device_t dev; dev = dev_find_device(0x1166, 0x0205, 0); if(dev) { uint32_t dword; dword = pci_read_config32(dev, 0x64); dword |= (1<<30); // GEVENT14-21 used as PCI IRQ0-7 pci_write_config32(dev, 0x64, dword); } // set GEVENT pins to NO OP outb(0x33, 0xcd6); outb(0x00, 0xcd7); outb(0x34, 0xcd6); outb(0x00, 0xcd7); outb(0x35, 0xcd6); outb(0x00, 0xcd7); } // hide XIOAPIC PCI configuration space { device_t dev; dev = dev_find_device(0x1166, 0x205, 0); if (dev) { uint32_t dword; dword = pci_read_config32(dev, 0x64); dword |= (1<<26); pci_write_config32(dev, 0x64, dword); } } mptable_add_isa_interrupts(mc, m->bus_isa, m->apicid_bcm5785[0], 0); //SATA /* printk(BIOS_DEBUG, "MPTABLE_SATA: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0x7); */ /* smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0x7); */ printk(BIOS_DEBUG, "MPTABLE_SATA: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0xb); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0xb); //USB printk(BIOS_DEBUG, "sysconf.sbdn: %d on bus: %x \n",sysconf.sbdn, m->bus_bcm5785_0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x03<<2)|0, m->apicid_bcm5785[0], 0xa); //VGA smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x4<<2)|0, m->apicid_bcm5785[1], 0x7); //PCIE smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x6<<2)|0, m->apicid_bcm5785[2], 0xe); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x7<<2)|0, m->apicid_bcm5785[2], 0xe); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x8<<2)|0, m->apicid_bcm5785[2], 0xe); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x9<<2)|0, m->apicid_bcm5785[2], 0xe); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0xa<<2)|0, m->apicid_bcm5785[2], 0xe); //IDE // outb(0x02, 0xc00); outb(0x0e, 0xc01); // printk(BIOS_DEBUG, "MPTABLE_IDE: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_0, ((1+sysconf.sbdn)<<2)|1, m->apicid_bcm5785[0], 0xe); // smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_bcm5785_0, (0x02<<2)|1, m->apicid_bcm5785[0], 0xe); //onboard Broadcom GbE smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,8, (4<<2)|0, m->apicid_bcm5785[2], 0x4); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,8, (4<<2)|1, m->apicid_bcm5785[2], 0x4); /* enable int */ /* why here? must get the BAR and PCI command bit 1 set before enable it ....*/ { device_t dev; dev = dev_find_device(0x1166, 0x0205, 0); if(dev) { uint32_t dword; dword = pci_read_config32(dev, 0x6c); dword |= (1<<4); // enable interrupts printk(BIOS_DEBUG, "6ch: %x\n",dword); pci_write_config32(dev, 0x6c, dword); } } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ printk(BIOS_DEBUG, "m->bus_isa is: %x\n",m->bus_isa); smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa , 0x0, MP_APIC_ALL, 0x1); //extended table entries smp_write_address_space(mc,0 , ADDRESS_TYPE_IO, 0x0, 0x0, 0x0, 0x0001); smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x0, 0x7f80, 0x0, 0x5e80); smp_write_address_space(mc,0 , ADDRESS_TYPE_PREFETCH, 0x0, 0xde00, 0x0, 0x0100); smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x0, 0xdf00, 0x0, 0x1fe0); smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x1000, 0xfee0, 0xf000, 0x011f); smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x0, 0x000a, 0x0, 0x0006); smp_write_bus_hierarchy(mc, 9, 0x01, 0); smp_write_compatibility_address_space(mc, 0, ADDRESS_RANGE_ADD, 0); smp_write_compatibility_address_space(mc, 0, ADDRESS_RANGE_ADD, 1); /* Compute the checksums */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc)); return smp_next_mpe_entry(mc); }
static void *smp_write_config_table(void *v) { struct mp_config_table *mc; unsigned sbdn; int i, bus_isa; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LAPIC_ADDR); smp_write_processors(mc); get_bus_conf(); sbdn = sysconf.sbdn; mptable_write_buses(mc, NULL, &bus_isa); /*I/O APICs: APIC ID Version State Address*/ { device_t dev; struct resource *res; uint32_t dword; dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x1,0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_1); if (res) { smp_write_ioapic(mc, apicid_ck804, 0x11, res->base); } /* Initialize interrupt mapping*/ dword = 0x0120d218; pci_write_config32(dev, 0x7c, dword); dword = 0x12008a00; pci_write_config32(dev, 0x80, dword); dword = 0x0000007d; pci_write_config32(dev, 0x84, dword); } dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base); } } dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base); } } } mptable_add_isa_interrupts(mc, bus_isa, apicid_ck804, 1); // Onboard ck804 smbus smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+1)<<2)|1, apicid_ck804, 0xa); // 10 // Onboard ck804 USB 1.1 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|0, apicid_ck804, 0x15); // 21 // Onboard ck804 USB 2 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|1, apicid_ck804, 0x14); // 20 // Onboard ck804 SATA 0 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +7)<<2)|0, apicid_ck804, 0x17); // 23 // Onboard ck804 SATA 1 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +8)<<2)|0, apicid_ck804, 0x16); // 22 //Slot PCIE x16 for(i=0;i<4;i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4); } //Slot PCIE x4 for(i=0;i<4;i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|i, apicid_ck804, 0x10 + (1+i+4-sbdn%4)%4); } //Onboard ati smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (7<<2)|0, apicid_ck804, 0x13); // 19 //Channel B of 8131 //Onboard Broadcom NIC for(i=0;i<2;i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|i, apicid_8131_2, (0+i)%4); //28 } //Channel A of 8131 //Slot 4 PCIX 133/100/66 for(i=0;i<4;i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|i, apicid_8131_1, (0+i)%4); //24 } //Slot 3 PCIX 133/100/66 SoDIMM PCI for(i=0;i<4;i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0xa<<2)|i, apicid_8131_1, (2+i)%4); //26 } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc)); return smp_next_mpe_entry(mc); }
static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; static const char oem[8] = "COREBOOT"; static const char productid[12] = "ultra40 "; struct mp_config_table *mc; unsigned char bus_num; int i; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); memset(mc, 0, sizeof(*mc)); memcpy(mc->mpc_signature, sig, sizeof(sig)); mc->mpc_length = sizeof(*mc); /* initially just the header */ mc->mpc_spec = 0x04; mc->mpc_checksum = 0; /* not yet computed */ memcpy(mc->mpc_oem, oem, sizeof(oem)); memcpy(mc->mpc_productid, productid, sizeof(productid)); mc->mpc_oemptr = 0; mc->mpc_oemsize = 0; mc->mpc_entry_count = 0; /* No entries yet... */ mc->mpc_lapic = LAPIC_ADDR; mc->mpe_length = 0; mc->mpe_checksum = 0; mc->reserved = 0; smp_write_processors(mc); get_bus_conf(); /*Bus: Bus ID Type*/ /* define bus and isa numbers */ for(bus_num = 0; bus_num < bus_isa; bus_num++) { smp_write_bus(mc, bus_num, "PCI "); } smp_write_bus(mc, bus_isa, "ISA "); /*I/O APICs: APIC ID Version State Address*/ { device_t dev; struct resource *res; uint32_t dword; dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x1,0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_1); if (res) { smp_write_ioapic(mc, apicid_ck804, 0x11, res->base); } /* Initialize interrupt mapping*/ dword = 0x0120d218; pci_write_config32(dev, 0x7c, dword); dword = 0x12008a00; pci_write_config32(dev, 0x80, dword); dword = 0x00080d7d; pci_write_config32(dev, 0x84, dword); } dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base); } } dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base); } } if(pci1234[2] & 0xf) { dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x1,0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_1); if (res) { smp_write_ioapic(mc, apicid_ck804b, 0x11, res->base); } dword = 0x0000d218; pci_write_config32(dev, 0x7c, dword); dword = 0x00000000; pci_write_config32(dev, 0x80, dword); dword = 0x00000d00; pci_write_config32(dev, 0x84, dword); } } } mptable_add_isa_interrupts(mc, bus_isa, apicid_ck804, 1); // Onboard ck804 smbus smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+1)<<2)|1, apicid_ck804, 0xa); // 10 // Onboard ck804 USB 1.1 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|0, apicid_ck804, 0x15); // 21 // Onboard ck804 USB 2 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|1, apicid_ck804, 0x14); // 20 // Onboard ck804 Audio smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+4)<<2)|0, apicid_ck804, 0x14); // 20 // Onboard ck804 SATA 0 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +7)<<2)|0, apicid_ck804, 0x17); // 23 // Onboard ck804 SATA 1 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +8)<<2)|0, apicid_ck804, 0x16); // 22 // Onboard ck804 NIC smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +0x0a)<<2)|0, apicid_ck804, 0x15); // 21 //Slot 1 PCIE x16 for(i=0; i<4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4); } //Onboard Firewire smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x05<<2)|0, apicid_ck804, 0x13); // 19 //Slot 2 PCI 32 for(i=0; i<4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|i, apicid_ck804, 0x10 + (0+i)%4); } if(pci1234[2] & 0xf) { //Onboard ck804b NIC smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_0, ((sbdnb+0x0a)<<2)|0, apicid_ck804b, 0x15);//24+4+4+21=53 //Slot 3 PCIE x16 for(i=0; i<4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|i, apicid_ck804b, 0x10 + (2+i+4-sbdnb%4)%4); } } //Channel B of 8131 //Slot 4 PCI-X 100/66 for(i=0; i<4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|i, apicid_8131_2, (0+i)%4); } //Slot 5 PCIX 100/66 for(i=0; i<4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|i, apicid_8131_2, (1+i)%4); // 29 } //OnBoard LSI SCSI for(i=0; i<2; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|i, apicid_8131_2, (2+i)%4); //30 } //Channel A of 8131 //Slot 6 PCIX 133/100/66 for(i=0; i<4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|i, apicid_8131_1, (0+i)%4); //24 } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc)); return smp_next_mpe_entry(mc); }
static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; static const char oem[8] = "COREBOOT"; static const char productid[12] = "P4DPE "; struct mp_config_table *mc; int isa_bus; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); memset(mc, 0, sizeof(*mc)); memcpy(mc->mpc_signature, sig, sizeof(sig)); mc->mpc_length = sizeof(*mc); /* initially just the header */ mc->mpc_spec = 0x04; mc->mpc_checksum = 0; /* not yet computed */ memcpy(mc->mpc_oem, oem, sizeof(oem)); memcpy(mc->mpc_productid, productid, sizeof(productid)); mc->mpc_oemptr = 0; mc->mpc_oemsize = 0; mc->mpc_entry_count = 0; /* No entries yet... */ mc->mpc_lapic = LAPIC_ADDR; mc->mpe_length = 0; mc->mpe_checksum = 0; mc->reserved = 0; smp_write_processors(mc); mptable_write_buses(mc, NULL, &isa_bus); /*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); { device_t dev; struct resource *res; dev = dev_find_slot(1, PCI_DEVFN(0x1e,0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, 3, 0x20, res->base); } } dev = dev_find_slot(1, PCI_DEVFN(0x1c,0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, 4, 0x20, res->base); } } dev = dev_find_slot(4, PCI_DEVFN(0x1e,0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, 5, 0x20, res->base); } } dev = dev_find_slot(4, PCI_DEVFN(0x1c,0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, 8, 0x20, res->base); } } } mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0); /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x40, 0x2, 0x15); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x40, 0x2, 0x15); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x41, 0x2, 0x15); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x41, 0x2, 0x15); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x42, 0x2, 0x15); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x46, 0x2, 0x16); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x48, 0x2, 0x17); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x3d, 0x2, 0x14); /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x0); smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc)); return smp_next_mpe_entry(mc); }
static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; static const char oem[8] = "COREBOOT"; static const char productid[12] = "D945GCLF "; struct mp_config_table *mc; int i; int max_pci_bus, isa_bus; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); memset(mc, 0, sizeof(*mc)); memcpy(mc->mpc_signature, sig, sizeof(sig)); mc->mpc_length = sizeof(*mc); /* initially just the header */ mc->mpc_spec = 0x04; mc->mpc_checksum = 0; /* not yet computed */ memcpy(mc->mpc_oem, oem, sizeof(oem)); memcpy(mc->mpc_productid, productid, sizeof(productid)); mc->mpc_oemptr = 0; mc->mpc_oemsize = 0; mc->mpc_entry_count = 0; /* No entries yet... */ mc->mpc_lapic = LAPIC_ADDR; mc->mpe_length = 0; mc->mpe_checksum = 0; mc->reserved = 0; smp_write_processors(mc); max_pci_bus = 5; // XXX read me from bridges. /* ISA bus follows */ isa_bus = max_pci_bus + 1; /* Bus: Bus ID Type */ for (i=0; i <= max_pci_bus; i++) smp_write_bus(mc, i, "PCI "); smp_write_bus(mc, isa_bus, "ISA "); /* I/O APICs: APIC ID Version State Address */ smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); /* Legacy Interrupts */ mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0); /* Builtin devices on Bus 0 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x8, 0x2, 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, 0x2, 0x13); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x2, 0x17); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x2, 0x13); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x76, 0x2, 0x12); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, 0x2, 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x6c, 0x2, 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x70, 0x2, 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x71, 0x2, 0x11); /* Firewire 4:0.0 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x0, 0x2, 0x10); /* Old riser card */ // riser slot top 5:8.0 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x20, 0x2, 0x14); // riser slot middle 5:9.0 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x24, 0x2, 0x15); // riser slot bottom 5:a.0 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x28, 0x2, 0x16); /* New Riser Card */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x30, 0x2, 0x14); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x34, 0x2, 0x15); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x38, 0x2, 0x16); /* Onboard Ethernet */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10); /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0); smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1); /* Compute the checksums */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc)); return smp_next_mpe_entry(mc); }
static void *smp_write_config_table(void *v) { struct mp_config_table *mc; int bus_isa; int boot_apic_id; unsigned apic_version; unsigned cpu_features; unsigned cpu_feature_flags; struct cpuid_result result; unsigned long cpu_flag; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LAPIC_ADDR); memcpy(mc->mpc_oem, "AMD ", 8); /*Inagua used dure core cpu with one die */ boot_apic_id = lapicid(); apic_version = lapic_read(LAPIC_LVR) & 0xff; result = cpuid(1); cpu_features = result.eax; cpu_feature_flags = result.edx; cpu_flag = MPC_CPU_ENABLED | MPC_CPU_BOOTPROCESSOR; smp_write_processor(mc, 0, apic_version, cpu_flag, cpu_features, cpu_feature_flags ); cpu_flag = MPC_CPU_ENABLED; smp_write_processor(mc, 1, apic_version, cpu_flag, cpu_features, cpu_feature_flags ); get_bus_conf(); //mptable_write_buses(mc, NULL, &bus_isa); my_smp_write_bus(mc, 0, "PCI "); my_smp_write_bus(mc, 1, "PCI "); bus_isa = 0x02; my_smp_write_bus(mc, bus_isa, "ISA "); /* I/O APICs: APIC ID Version State Address */ device_t dev; u32 dword; u8 byte; dword = 0; dword = pm_ioread(0x34) & 0xF0; dword |= (pm_ioread(0x35) & 0xFF) << 8; dword |= (pm_ioread(0x36) & 0xFF) << 16; dword |= (pm_ioread(0x37) & 0xFF) << 24; /* Set IO APIC ID onto IO_APIC_ID */ write32 (dword, 0x00); write32 (dword + 0x10, IO_APIC_ID << 24); apicid_sb900 = IO_APIC_ID; smp_write_ioapic(mc, apicid_sb900, 0x21, dword); /* PIC IRQ routine */ for (byte = 0x0; byte < sizeof(picr_data); byte ++) { outb(byte, 0xC00); outb(picr_data[byte], 0xC01); } /* APIC IRQ routine */ for (byte = 0x0; byte < sizeof(intr_data); byte ++) { outb(byte | 0x80, 0xC00); outb(intr_data[byte], 0xC01); } /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); //mptable_add_isa_interrupts(mc, bus_isa, apicid_sb900, 0); /*I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_sb900, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_sb900, 0x1); smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x2, apicid_sb900, 0x2); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x3, apicid_sb900, 0x3); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x4, apicid_sb900, 0x4); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, 0x49, apicid_sb900, 0x11); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x6, apicid_sb900, 0x6); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x7, apicid_sb900, 0x7); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x8, apicid_sb900, 0x8); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x9, apicid_sb900, 0x9); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_isa, 0xa, apicid_sb900, 0xa); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_isa, 0x1c, apicid_sb900, 0x13); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xc, apicid_sb900, 0xc); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, apicid_sb900, 0xd); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, apicid_sb900, 0xe); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_sb900, 0xf); /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ #define PCI_INT(bus, dev, int_sign, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb900, (pin)) /* Internal VGA */ PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); /* SMBUS */ PCI_INT(0x0, 0x14, 0x0, 0x10); /* HD Audio */ PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]); /* USB */ PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]); /* sata */ PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]); PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); /* on board NIC & Slot PCIE. */ /* PCI slots */ /* PCI_SLOT 0. */ PCI_INT(bus_sb900[1], 0x5, 0x0, 0x14); PCI_INT(bus_sb900[1], 0x5, 0x1, 0x15); PCI_INT(bus_sb900[1], 0x5, 0x2, 0x16); PCI_INT(bus_sb900[1], 0x5, 0x3, 0x17); /* PCI_SLOT 1. */ PCI_INT(bus_sb900[1], 0x6, 0x0, 0x15); PCI_INT(bus_sb900[1], 0x6, 0x1, 0x16); PCI_INT(bus_sb900[1], 0x6, 0x2, 0x17); PCI_INT(bus_sb900[1], 0x6, 0x3, 0x14); /* PCI_SLOT 2. */ PCI_INT(bus_sb900[1], 0x7, 0x0, 0x16); PCI_INT(bus_sb900[1], 0x7, 0x1, 0x17); PCI_INT(bus_sb900[1], 0x7, 0x2, 0x14); PCI_INT(bus_sb900[1], 0x7, 0x3, 0x15); PCI_INT(bus_sb900[2], 0x0, 0x0, 0x12); PCI_INT(bus_sb900[2], 0x0, 0x1, 0x13); PCI_INT(bus_sb900[2], 0x0, 0x2, 0x14); /* PCIe Lan*/ PCI_INT(0x0, 0x06, 0x0, 0x13); /* FCH PCIe PortA */ PCI_INT(0x0, 0x15, 0x0, 0x10); /* FCH PCIe PortB */ PCI_INT(0x0, 0x15, 0x1, 0x11); /* FCH PCIe PortC */ PCI_INT(0x0, 0x15, 0x2, 0x12); /* FCH PCIe PortD */ PCI_INT(0x0, 0x15, 0x3, 0x13); /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc)); return smp_next_mpe_entry(mc); }
void *smp_write_config_table(void *v) { struct mp_config_table *mc; int isa_bus; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LAPIC_ADDR); smp_write_processors(mc); mptable_write_buses(mc, NULL, &isa_bus); smp_write_ioapic(mc, 2, 0x20, 0xfec00000); { device_t dev; struct resource *res; dev = dev_find_slot(1, PCI_DEVFN(0x1e,0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, 3, 0x20, res->base); } } dev = dev_find_slot(1, PCI_DEVFN(0x1c,0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, 4, 0x20, res->base); } } dev = dev_find_slot(4, PCI_DEVFN(0x1e,0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, 5, 0x20, res->base); } } dev = dev_find_slot(4, PCI_DEVFN(0x1c,0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, 8, 0x20, res->base); } } } /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_DEFAULT, 0x1, 0x0, 0x1, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x1, 0x1, 0x1, 0x1); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x1, 0x0, 0x1, 0x2); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x1, 0x3, 0x1, 0x3); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x1, 0x4, 0x1, 0x4); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x1, 0x6, 0x1, 0x6); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x1, 0x7, 0x1, 0x7); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x1, 0x8, 0x1, 0x8); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x1, 0x9, 0x1, 0x9); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x1, 0xc, 0x1, 0xc); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x1, 0xd, 0x1, 0xd); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x1, 0xe, 0x1, 0xe); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x8, 0x1, 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x1, 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x1, 0x11); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x76, 0x1, 0x12); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, 0x1, 0x13); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x6c, 0x1, 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x78, 0x1, 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x79, 0x1, 0x11); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7a, 0x1, 0x12); /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0); smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc)); return smp_next_mpe_entry(mc); }
static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; static const char oem[8] = "COREBOOT"; static const char productid[12] = "Truxton "; struct mp_config_table *mc; u8 bus_num; u8 bus_isa; u8 bus_pea0 = 0; u8 bus_pea1 = 0; u8 bus_aioc; device_t dev; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); memset(mc, 0, sizeof(*mc)); memcpy(mc->mpc_signature, sig, sizeof(sig)); mc->mpc_length = sizeof(*mc); /* initially just the header */ mc->mpc_spec = 0x04; mc->mpc_checksum = 0; /* not yet computed */ memcpy(mc->mpc_oem, oem, sizeof(oem)); memcpy(mc->mpc_productid, productid, sizeof(productid)); mc->mpc_oemptr = 0; mc->mpc_oemsize = 0; mc->mpc_entry_count = 0; /* No entries yet... */ mc->mpc_lapic = LAPIC_ADDR; mc->mpe_length = 0; mc->mpe_checksum = 0; mc->reserved = 0; smp_write_processors(mc); /* AIOC bridge */ dev = dev_find_slot(0, PCI_DEVFN(0x04,0)); if (dev) { bus_aioc = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_isa++; } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 0:04.0\n"); bus_aioc = 0; bus_isa = 9; } /* PCIe A0 */ dev = dev_find_slot(0, PCI_DEVFN(0x02,0)); if (dev) { bus_pea0 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 0:02.0\n"); bus_pea0 = 0; } /* PCIe A1 */ dev = dev_find_slot(0, PCI_DEVFN(0x03,0)); if (dev) { bus_pea1 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 0:03.0\n"); bus_pea1 = 0; } /* define bus and isa numbers */ for(bus_num = 0; bus_num < bus_isa; bus_num++) { smp_write_bus(mc, bus_num, "PCI "); } smp_write_bus(mc, bus_isa, "ISA "); /* IOAPIC handling */ smp_write_ioapic(mc, 0x8, 0x20, IO_APIC_ADDR); mptable_add_isa_interrupts(mc, bus_isa, 0x8, 0); /* Standard local interrupt assignments */ smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x00, MP_APIC_ALL, 0x00); smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x00, MP_APIC_ALL, 0x01); /* IMCH/IICH PCI devices */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (0x01<<2)|0, 0x8, 0x10); /* DMA controller */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (0x02<<2)|0, 0x8, 0x10); /* PCIe port A bridge */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (0x03<<2)|0, 0x8, 0x10); /* PCIe port A1 bridge */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (0x04<<2)|0, 0x8, 0x10); /* AIOC PCI bridge */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (0x1d<<2)|0, 0x8, 0x10); /* UHCI/EHCI */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (0x1f<<2)|1, 0x8, 0x11); /* SATA/SMBus */ if (bus_pea0) { /* PCIe slot 0 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_pea0, (0<<2)|0, 0x8, 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_pea0, (0<<2)|1, 0x8, 0x11); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_pea0, (0<<2)|2, 0x8, 0x12); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_pea0, (0<<2)|3, 0x8, 0x13); } if (bus_pea1) { /* PCIe slots 1-4 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_pea1, (0<<2)|0, 0x8, 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_pea1, (0<<2)|1, 0x8, 0x11); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_pea1, (0<<2)|2, 0x8, 0x12); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_pea1, (0<<2)|3, 0x8, 0x13); } if (bus_aioc) { /* AIOC PCI devices */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_aioc, (0<<2)|0, 0x8, 0x10); /* GbE0 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_aioc, (1<<2)|0, 0x8, 0x11); /* GbE1 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_aioc, (2<<2)|0, 0x8, 0x12); /* GbE2 */ } /* There is no extension information... */ /* Compute the checksums */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc)); return smp_next_mpe_entry(mc); }
static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; static const char oem[8] = "COREBOOT"; static const char productid[12] = "A8V-E SE "; struct mp_config_table *mc; int bus_isa = 42; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); memset(mc, 0, sizeof(*mc)); memcpy(mc->mpc_signature, sig, sizeof(sig)); mc->mpc_length = sizeof(*mc); /* Initially just the header. */ mc->mpc_spec = 0x04; mc->mpc_checksum = 0; /* Not yet computed. */ memcpy(mc->mpc_oem, oem, sizeof(oem)); memcpy(mc->mpc_productid, productid, sizeof(productid)); mc->mpc_oemptr = 0; mc->mpc_oemsize = 0; mc->mpc_entry_count = 0; /* No entries yet. */ mc->mpc_lapic = LAPIC_ADDR; mc->mpe_length = 0; mc->mpe_checksum = 0; mc->reserved = 0; smp_write_processors(mc); /* Bus: Bus ID Type */ smp_write_bus(mc, 0, "PCI "); smp_write_bus(mc, 1, "PCI "); smp_write_bus(mc, 2, "PCI "); smp_write_bus(mc, 3, "PCI "); smp_write_bus(mc, 4, "PCI "); smp_write_bus(mc, 5, "PCI "); smp_write_bus(mc, 6, "PCI "); smp_write_bus(mc, bus_isa, "ISA "); /* I/O APICs: APIC ID Version State Address */ smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, IO_APIC_ADDR); smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, K8T890_APIC_BASE); mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 0, VT8237R_APIC_ID, 0x10); //IRQ16 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 1, VT8237R_APIC_ID, 0x11); //IRQ17 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 2, VT8237R_APIC_ID, 0x12); //IRQ18 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 3, VT8237R_APIC_ID, 0x13); //IRQ19 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 0, VT8237R_APIC_ID, 0x11); //IRQ17 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 1, VT8237R_APIC_ID, 0x12); //IRQ18 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 2, VT8237R_APIC_ID, 0x13); //IRQ19 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 3, VT8237R_APIC_ID, 0x10); //IRQ16 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 0, VT8237R_APIC_ID, 0x12); //IRQ18 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 1, VT8237R_APIC_ID, 0x13); //IRQ19 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 2, VT8237R_APIC_ID, 0x10); //IRQ16 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 3, VT8237R_APIC_ID, 0x11); //IRQ17 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 0, VT8237R_APIC_ID, 0x14); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 1, VT8237R_APIC_ID, 0x14); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 0, VT8237R_APIC_ID, 0x15); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 1, VT8237R_APIC_ID, 0x15); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 2, VT8237R_APIC_ID, 0x15); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x11 << 2) | 2, VT8237R_APIC_ID, 0x16); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 0, K8T890_APIC_ID, 0x3); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 1, K8T890_APIC_ID, 0x3); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 2, K8T890_APIC_ID, 0x3); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 3, K8T890_APIC_ID, 0x3); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 0, K8T890_APIC_ID, 0x7); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 1, K8T890_APIC_ID, 0xb); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 2, K8T890_APIC_ID, 0xf); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 3, K8T890_APIC_ID, 0x13); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 0, K8T890_APIC_ID, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 1, K8T890_APIC_ID, 0x1); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 2, K8T890_APIC_ID, 0x2); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 3, K8T890_APIC_ID, 0x3); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 0, K8T890_APIC_ID, 0x4); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 1, K8T890_APIC_ID, 0x5); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 2, K8T890_APIC_ID, 0x6); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 3, K8T890_APIC_ID, 0x7); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 0, K8T890_APIC_ID, 0x8); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 1, K8T890_APIC_ID, 0x9); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 2, K8T890_APIC_ID, 0xa); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 3, K8T890_APIC_ID, 0xb); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 0, K8T890_APIC_ID, 0xc); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 1, K8T890_APIC_ID, 0xd); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 2, K8T890_APIC_ID, 0xe); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 3, K8T890_APIC_ID, 0xf); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 0, K8T890_APIC_ID, 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 1, K8T890_APIC_ID, 0x11); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 2, K8T890_APIC_ID, 0x12); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 3, K8T890_APIC_ID, 0x13); /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums. */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); return smp_next_mpe_entry(mc); }
static void *smp_write_config_table(void *v) { struct mp_config_table *mc; int bus_isa; u8 bus_pea0 = 0; u8 bus_pea1 = 0; u8 bus_aioc; device_t dev; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LAPIC_ADDR); smp_write_processors(mc); /* AIOC bridge */ dev = dev_find_slot(0, PCI_DEVFN(0x04,0)); if (dev) { bus_aioc = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 0:04.0\n"); bus_aioc = 0; } /* PCIe A0 */ dev = dev_find_slot(0, PCI_DEVFN(0x02,0)); if (dev) { bus_pea0 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 0:02.0\n"); bus_pea0 = 0; } /* PCIe A1 */ dev = dev_find_slot(0, PCI_DEVFN(0x03,0)); if (dev) { bus_pea1 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 0:03.0\n"); bus_pea1 = 0; } mptable_write_buses(mc, NULL, &bus_isa); /* IOAPIC handling */ smp_write_ioapic(mc, 0x8, 0x20, IO_APIC_ADDR); mptable_add_isa_interrupts(mc, bus_isa, 0x8, 0); /* Standard local interrupt assignments */ smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x00, MP_APIC_ALL, 0x00); smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x00, MP_APIC_ALL, 0x01); /* IMCH/IICH PCI devices */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (0x01<<2)|0, 0x8, 0x10); /* DMA controller */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (0x02<<2)|0, 0x8, 0x10); /* PCIe port A bridge */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (0x03<<2)|0, 0x8, 0x10); /* PCIe port A1 bridge */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (0x04<<2)|0, 0x8, 0x10); /* AIOC PCI bridge */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (0x1d<<2)|0, 0x8, 0x10); /* UHCI/EHCI */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (0x1f<<2)|1, 0x8, 0x11); /* SATA/SMBus */ if (bus_pea0) { /* PCIe slot 0 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_pea0, (0<<2)|0, 0x8, 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_pea0, (0<<2)|1, 0x8, 0x11); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_pea0, (0<<2)|2, 0x8, 0x12); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_pea0, (0<<2)|3, 0x8, 0x13); } if (bus_pea1) { /* PCIe slots 1-4 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_pea1, (0<<2)|0, 0x8, 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_pea1, (0<<2)|1, 0x8, 0x11); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_pea1, (0<<2)|2, 0x8, 0x12); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_pea1, (0<<2)|3, 0x8, 0x13); } if (bus_aioc) { /* AIOC PCI devices */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_aioc, (0<<2)|0, 0x8, 0x10); /* GbE0 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_aioc, (1<<2)|0, 0x8, 0x11); /* GbE1 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_aioc, (2<<2)|0, 0x8, 0x12); /* GbE2 */ } /* There is no extension information... */ /* Compute the checksums */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc)); return smp_next_mpe_entry(mc); }
static void *smp_write_config_table(void *v) { struct mp_config_table *mc; int bus_isa; unsigned char bus_pxhd_1; unsigned char bus_pxhd_2; unsigned char bus_esb6300_1; unsigned char bus_esb6300_2; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LAPIC_ADDR); smp_write_processors(mc); { device_t dev; /* esb6300_2 */ dev = dev_find_slot(0, PCI_DEVFN(0x1c,0)); if (dev) { bus_esb6300_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1c.0, using defaults\n"); bus_esb6300_1 = 6; } /* esb6300_1 */ dev = dev_find_slot(0, PCI_DEVFN(0x1e,0)); if (dev) { bus_esb6300_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n"); bus_esb6300_2 = 7; } /* pxhd-1 */ dev = dev_find_slot(1, PCI_DEVFN(0x0,0)); if (dev) { bus_pxhd_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.1, using defaults\n"); bus_pxhd_1 = 2; } /* pxhd-2 */ dev = dev_find_slot(1, PCI_DEVFN(0x00,2)); if (dev) { bus_pxhd_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n"); bus_pxhd_2 = 3; } } mptable_write_buses(mc, NULL, &bus_isa); /* IOAPIC handling */ smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); smp_write_ioapic(mc, 3, 0x20, IO_APIC_ADDR + 0x10000); { struct resource *res; device_t dev; /* PXHd apic 4 */ dev = dev_find_slot(1, PCI_DEVFN(0x00,1)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, 0x04, 0x20, res->base); } } else { printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.1\n"); printk(BIOS_DEBUG, "CONFIG_DEBUG: Dev= %p\n", dev); } /* PXHd apic 5 */ dev = dev_find_slot(1, PCI_DEVFN(0x00,3)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, 0x05, 0x20, res->base); } } else { printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.3\n"); printk(BIOS_DEBUG, "CONFIG_DEBUG: Dev= %p\n", dev); } } mptable_add_isa_interrupts(mc, bus_isa, 0x2, 0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, 0x74, 0x02, 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, 0x77, 0x02, 0x17); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, 0x75, 0x02, 0x13); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, 0x7c, 0x02, 0x12); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, 0x7d, 0x02, 0x11); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added 0x03, 0x08, 0x05, 0x00); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added 0x03, 0x08, 0x05, 0x04); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added bus_esb6300_1, 0x04, 0x03, 0x00); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added bus_esb6300_1, 0x08, 0x03, 0x01); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added bus_esb6300_2, 0x04, 0x02, 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added bus_esb6300_2, 0x08, 0x02, 0x14); /* Standard local interrupt assignments */ smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x00, MP_APIC_ALL, 0x00); smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x00, MP_APIC_ALL, 0x01); /* FIXME verify I have the irqs handled for all of the risers */ /* Compute the checksums */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc)); return smp_next_mpe_entry(mc); }
static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; static const char oem[8] = "COREBOOT"; static const char productid[12] = "PC2500 "; struct mp_config_table *mc; int isa_bus; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); memset(mc, 0, sizeof(*mc)); memcpy(mc->mpc_signature, sig, sizeof(sig)); mc->mpc_length = sizeof(*mc); /* initially just the header */ mc->mpc_spec = 0x04; mc->mpc_checksum = 0; /* not yet computed */ memcpy(mc->mpc_oem, oem, sizeof(oem)); memcpy(mc->mpc_productid, productid, sizeof(productid)); mc->mpc_oemptr = 0; mc->mpc_oemsize = 0; mc->mpc_entry_count = 0; /* No entries yet... */ mc->mpc_lapic = LAPIC_ADDR; mc->mpe_length = 0; mc->mpe_checksum = 0; mc->reserved = 0; smp_write_processors(mc); mptable_write_buses(mc, NULL, &isa_bus); /* I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, IO_APIC_ADDR); /* Now, assemble the table. */ mptable_add_isa_interrupts(mc, isa_bus, VT8237R_APIC_ID, 0); #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, \ bus, (((dev)<<2)|(fn)), VT8237R_APIC_ID, (pin)) // PCI slot 1 PCI_INT(0, 8, 0, 16); PCI_INT(0, 8, 1, 17); PCI_INT(0, 8, 2, 18); PCI_INT(0, 8, 3, 19); // PCI slot 2 PCI_INT(0, 9, 0, 17); PCI_INT(0, 9, 1, 18); PCI_INT(0, 9, 2, 19); PCI_INT(0, 9, 3, 16); // SATA PCI_INT(0, 15, 1, 20); // USB PCI_INT(0, 16, 0, 21); PCI_INT(0, 16, 1, 21); PCI_INT(0, 16, 2, 21); PCI_INT(0, 16, 3, 21); // Audio PCI_INT(0, 17, 2, 22); // Ethernet PCI_INT(0, 18, 0, 23); /* Onboard VGA */ PCI_INT(1, 0, 0, 16); /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0, 0x0, MP_APIC_ALL, 0x0); smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc)); return smp_next_mpe_entry(mc); }
static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; static const char oem[8] = "COREBOOT"; static const char productid[12] = "PA78VM5 "; struct mp_config_table *mc; int j; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); memset(mc, 0, sizeof(*mc)); memcpy(mc->mpc_signature, sig, sizeof(sig)); mc->mpc_length = sizeof(*mc); /* initially just the header */ mc->mpc_spec = 0x04; mc->mpc_checksum = 0; /* not yet computed */ memcpy(mc->mpc_oem, oem, sizeof(oem)); memcpy(mc->mpc_productid, productid, sizeof(productid)); mc->mpc_oemptr = 0; mc->mpc_oemsize = 0; mc->mpc_entry_count = 0; /* No entries yet... */ mc->mpc_lapic = LAPIC_ADDR; mc->mpe_length = 0; mc->mpe_checksum = 0; mc->reserved = 0; smp_write_processors(mc); get_bus_conf(); /* Bus: Bus ID Type */ /* define bus and isa numbers */ for (j = 0; j < bus_isa; j++) { smp_write_bus(mc, j, (char *)"PCI "); } smp_write_bus(mc, bus_isa, (char *)"ISA "); /* I/O APICs: APIC ID Version State Address */ { device_t dev; u32 dword; u8 byte; dev = dev_find_slot(bus_sb700[0], PCI_DEVFN(sbdn_sb700 + 0x14, 0)); if (dev) { dword = pci_read_config32(dev, 0x74) & 0xfffffff0; smp_write_ioapic(mc, apicid_sb700, 0x11, dword); /* Initialize interrupt mapping */ /* aza */ byte = pci_read_config8(dev, 0x63); byte &= 0xf8; byte |= 0; /* 0: INTA, ...., 7: INTH */ pci_write_config8(dev, 0x63, byte); /* SATA */ dword = pci_read_config32(dev, 0xac); dword &= ~(7 << 26); dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ /* dword |= 1<<22; PIC and APIC co exists */ pci_write_config32(dev, 0xac, dword); /* * 00:12.0: PROG SATA : INT F * 00:13.0: INTA USB_0 * 00:13.1: INTB USB_1 * 00:13.2: INTC USB_2 * 00:13.3: INTD USB_3 * 00:13.4: INTC USB_4 * 00:13.5: INTD USB2 * 00:14.1: INTA IDE * 00:14.2: Prog HDA : INT E * 00:14.5: INTB ACI * 00:14.6: INTB MCI */ } } /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0); /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ #if CONFIG_GENERATE_ACPI_TABLES == 0 #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin)) #else #define PCI_INT(bus, dev, fn, pin) #endif /* usb */ PCI_INT(0x0, 0x12, 0x0, 0x10); /* USB */ PCI_INT(0x0, 0x12, 0x1, 0x11); PCI_INT(0x0, 0x13, 0x0, 0x12); PCI_INT(0x0, 0x13, 0x1, 0x13); PCI_INT(0x0, 0x14, 0x0, 0x10); /* sata */ PCI_INT(0x0, 0x11, 0x0, 0x16); /* HD Audio: b0:d20:f1:reg63 should be 0. */ /* PCI_INT(0x0, 0x14, 0x2, 0x12); */ /* on board NIC & Slot PCIE. */ /* PCI_INT(bus_rs780[0x1], 0x5, 0x0, 0x12); */ /* PCI_INT(bus_rs780[0x1], 0x5, 0x1, 0x13); */ PCI_INT(bus_rs780[0x2], 0x0, 0x0, 0x12); /* Dev 2, external GFX */ /* PCI_INT(bus_rs780[0x3], 0x0, 0x0, 0x13); */ PCI_INT(bus_rs780[0x4], 0x0, 0x0, 0x10); /* configuration B doesnt need dev 5,6,7 */ /* * PCI_INT(bus_rs780[0x5], 0x0, 0x0, 0x11); * PCI_INT(bus_rs780[0x6], 0x0, 0x0, 0x12); * PCI_INT(bus_rs780[0x7], 0x0, 0x0, 0x13); */ PCI_INT(bus_rs780[0x9], 0x0, 0x0, 0x11); PCI_INT(bus_rs780[0xA], 0x0, 0x0, 0x12); /* NIC */ /* PCI slots */ /* PCI_SLOT 0. */ PCI_INT(bus_sb700[1], 0x5, 0x0, 0x14); PCI_INT(bus_sb700[1], 0x5, 0x1, 0x15); PCI_INT(bus_sb700[1], 0x5, 0x2, 0x16); PCI_INT(bus_sb700[1], 0x5, 0x3, 0x17); /* PCI_SLOT 1. */ PCI_INT(bus_sb700[1], 0x6, 0x0, 0x15); PCI_INT(bus_sb700[1], 0x6, 0x1, 0x16); PCI_INT(bus_sb700[1], 0x6, 0x2, 0x17); PCI_INT(bus_sb700[1], 0x6, 0x3, 0x14); /* PCI_SLOT 2. */ PCI_INT(bus_sb700[1], 0x7, 0x0, 0x16); PCI_INT(bus_sb700[1], 0x7, 0x1, 0x17); PCI_INT(bus_sb700[1], 0x7, 0x2, 0x14); PCI_INT(bus_sb700[1], 0x7, 0x3, 0x15); /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc)); return smp_next_mpe_entry(mc); }
static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; static const char oem[8] = "COREBOOT"; static const char productid[12] = "S2735 "; struct mp_config_table *mc; int isa_bus; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); memset(mc, 0, sizeof(*mc)); memcpy(mc->mpc_signature, sig, sizeof(sig)); mc->mpc_length = sizeof(*mc); /* initially just the header */ mc->mpc_spec = 0x04; mc->mpc_checksum = 0; /* not yet computed */ memcpy(mc->mpc_oem, oem, sizeof(oem)); memcpy(mc->mpc_productid, productid, sizeof(productid)); mc->mpc_oemptr = 0; mc->mpc_oemsize = 0; mc->mpc_entry_count = 0; /* No entries yet... */ mc->mpc_lapic = LAPIC_ADDR; mc->mpe_length = 0; mc->mpe_checksum = 0; mc->reserved = 0; smp_write_processors(mc); mptable_write_buses(mc, NULL, &isa_bus); /*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, 8, 0x20, IO_APIC_ADDR); { device_t dev; struct resource *res; dev = dev_find_slot(1, PCI_DEVFN(0x1e,0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, 0x09, 0x20, res->base); } } dev = dev_find_slot(1, PCI_DEVFN(0x1c,0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, 0x0a, 0x20, res->base); } } } mptable_add_isa_interrupts(mc, isa_bus, 0x8, 0); /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ //USB smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7c, 0x8, 0x12); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, 0x8, 0x11); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x8, 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x8, 0x13); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, 0x8, 0x17); //onboard ati smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x8, 0x8, 0x12); //onboard intel 82551 10/100 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x4, 0x8, 0x11); // onboard Intel 82547 1000 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x4, 0xa, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x5, 0xa, 0x1); //Slot 4 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x3<<2)|0, 0x8, 0x12); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x3<<2)|1, 0x8, 0x13); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x3<<2)|2, 0x8, 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x3<<2)|3, 0x8, 0x11); //Slot 3 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x4<<2)|0, 0x8, 0x13); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x4<<2)|1, 0x8, 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x4<<2)|2, 0x8, 0x11); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x4<<2)|3, 0x8, 0x12); //Slot 1 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x3<<2)|0, 0x9, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x3<<2)|1, 0x9, 0x1); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x3<<2)|2, 0x9, 0x2); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x3<<2)|3, 0x9, 0x3); //Slot 2 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x6<<2)|0, 0x9, 0x4); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x6<<2)|1, 0x9, 0x5); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x6<<2)|2, 0x9, 0x6); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x6<<2)|3, 0x9, 0x7); /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x0, 0x0, MP_APIC_ALL, 0x0); smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x0, 0x0, MP_APIC_ALL, 0x1); /* MP Config Extended Table Entries: -- System Address Space bus ID: 0 address type: I/O address address base: 0x9000 address range: 0x6000 -- System Address Space bus ID: 0 address type: I/O address address base: 0x0 address range: 0x100 -- System Address Space bus ID: 0 address type: memory address address base: 0xa0000 address range: 0x20000 -- System Address Space bus ID: 0 address type: memory address address base: 0xfc700000 address range: 0x2500000 -- System Address Space bus ID: 0 address type: prefetch address address base: 0xff600000 address range: 0x500000 -- Bus Heirarchy bus ID: 5 bus info: 0x01 parent bus ID: 0-- Compatibility Bus Address bus ID: 0 address modifier: add predefined range: 0x00000000-- Compatibility Bus Address bus ID: 0 address modifier: add predefined range: 0x00000001 // There is no extension information... */ /* Compute the checksums */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc)); return smp_next_mpe_entry(mc); }
static void *smp_write_config_table(void *v) { struct mp_config_table *mc; unsigned sbdn; int bus_isa; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LAPIC_ADDR); smp_write_processors(mc); get_bus_conf(); sbdn = sysconf.sbdn; mptable_write_buses(mc, NULL, &bus_isa); /* I/O APICs: APIC ID Version State Address */ { device_t dev; struct resource *res; uint32_t dword; dev = dev_find_slot(bus_ck804[0], PCI_DEVFN(sbdn + 0x1, 0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_1); if (res) { smp_write_ioapic(mc, apicid_ck804, 0x11, res->base); } /* Initialize interrupt mapping. */ dword = 0x01200000; pci_write_config32(dev, 0x7c, dword); dword = 0x12008009; pci_write_config32(dev, 0x80, dword); dword = 0x0002010d; pci_write_config32(dev, 0x84, dword); } } mptable_add_isa_interrupts(mc, bus_isa, apicid_ck804, 0); // Onboard ck804 smbus smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_ck804[0], ((sbdn + 1) << 2) | 1, apicid_ck804, 0xa); // Onboard ck804 USB 1.1 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_ck804[0], ((sbdn + 2) << 2) | 0, apicid_ck804, 0x15); // Onboard ck804 USB 2 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_ck804[0], ((sbdn + 2) << 2) | 1, apicid_ck804, 0x14); // Onboard ck804 SATA 0 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_ck804[0], ((sbdn + 7) << 2) | 0, apicid_ck804, 0x17); // Onboard ck804 SATA 1 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_ck804[0], ((sbdn + 8) << 2) | 0, apicid_ck804, 0x16); // Onboard ck804 NIC smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_ck804[0], ((sbdn + 10) << 2) | 0, apicid_ck804, 0x17); /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, bus_ck804[0], 0x0, MP_APIC_ALL, 0x0); smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, bus_ck804[0], 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums. */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc)); return smp_next_mpe_entry(mc); }
static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; static const char oem[8] = "COREBOOT"; static const char productid[12] = "K9ND MS-9652"; struct mp_config_table *mc; struct mb_sysconf_t *m; unsigned sbdn; int i,j; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); memset(mc, 0, sizeof(*mc)); memcpy(mc->mpc_signature, sig, sizeof(sig)); mc->mpc_length = sizeof(*mc); /* initially just the header */ mc->mpc_spec = 0x04; mc->mpc_checksum = 0; /* not yet computed */ memcpy(mc->mpc_oem, oem, sizeof(oem)); memcpy(mc->mpc_productid, productid, sizeof(productid)); mc->mpc_oemptr = 0; mc->mpc_oemsize = 0; mc->mpc_entry_count = 0; /* No entries yet... */ mc->mpc_lapic = LAPIC_ADDR; mc->mpe_length = 0; mc->mpe_checksum = 0; mc->reserved = 0; smp_write_processors(mc); get_bus_conf(); sbdn = sysconf.sbdn; m = sysconf.mb; /*Bus: Bus ID Type*/ /* define bus and isa numbers */ for(j= 0; j < 256 ; j++) { if(m->bus_type[j]) smp_write_bus(mc, j, "PCI "); } smp_write_bus(mc, m->bus_isa, "ISA "); /*I/O APICs: APIC ID Version State Address*/ { device_t dev; struct resource *res; uint32_t dword; dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_1); if (res) { smp_write_ioapic(mc, m->apicid_mcp55, 0x11, res->base); } dword = 0x43c6c643; pci_write_config32(dev, 0x7c, dword); dword = 0x81001a00; pci_write_config32(dev, 0x80, dword); dword = 0xd00012d2; pci_write_config32(dev, 0x84, dword); } } mptable_add_isa_interrupts(mc, m->bus_isa, m->apicid_mcp55, 0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0xa); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|0, m->apicid_mcp55, 0x16); // 22 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|1, m->apicid_mcp55, 0x17); // 23 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+6)<<2)|1, m->apicid_mcp55, 0x17); // 23 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|0, m->apicid_mcp55, 0x14); // 20 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|1, m->apicid_mcp55, 0x17); // 23 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|2, m->apicid_mcp55, 0x15); // 21 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+8)<<2)|0, m->apicid_mcp55, 0x16); // 22 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21 for(j=7; j>=2; j--) { if(!m->bus_mcp55[j]) continue; for(i=0;i<4;i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00<<2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); } } for(j=0; j<1; j++) for(i=0;i<4;i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[1], ((0x04+j)<<2)|i, m->apicid_mcp55, 0x10 + (2+i+j)%4); } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc)); return smp_next_mpe_entry(mc); }
static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; static const char oem[8] = "COREBOOT"; static const char productid[12] = "DL145G1 "; struct mp_config_table *mc; unsigned char bus_num; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); memset(mc, 0, sizeof(*mc)); memcpy(mc->mpc_signature, sig, sizeof(sig)); mc->mpc_length = sizeof(*mc); /* initially just the header */ mc->mpc_spec = 0x04; mc->mpc_checksum = 0; /* not yet computed */ memcpy(mc->mpc_oem, oem, sizeof(oem)); memcpy(mc->mpc_productid, productid, sizeof(productid)); mc->mpc_oemptr = 0; mc->mpc_oemsize = 0; mc->mpc_entry_count = 0; /* No entries yet... */ mc->mpc_lapic = LAPIC_ADDR; mc->mpe_length = 0; mc->mpe_checksum = 0; mc->reserved = 0; smp_write_processors(mc); get_bus_conf(); /*Bus: Bus ID Type*/ /* define bus and isa numbers */ for(bus_num = 0; bus_num < bus_isa; bus_num++) { smp_write_bus(mc, bus_num, "PCI "); } smp_write_bus(mc, bus_isa, "ISA "); /*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, apicid_8111, 0x20, IO_APIC_ADDR); { device_t dev; struct resource *res; dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, apicid_8131_1, 0x20, res->base); } } dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, apicid_8131_2, 0x20, res->base); } } } mptable_add_isa_interrupts(mc, bus_isa, apicid_8111, 0); // // The commented-out lines are auto-detected on my servers. // /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ // Integrated SMBus 2.0 //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|3, apicid_8111 , 0x15); // Integrated AMD AC97 Audio //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|1, apicid_8111 , 0x11); //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|2, apicid_8111 , 0x12); // Integrated AMD USB smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, ( 0x4 <<2)|0, apicid_8111 , 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, ( 0x0 <<2)|3, apicid_8111 , 0x13); // On board ATI Rage XL //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, ( 0x5 <<2)|0, apicid_8111 , 0x14); // On board Broadcom nics smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, ( 0x3 <<2)|0, apicid_8131_2, 0x03); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, ( 0x3 <<2)|1, apicid_8131_2, 0x00); // On board LSI SCSI //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, ( 0x2 <<2)|0, apicid_8131_2, 0x02); // PCIX-133 Slot smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|0, apicid_8131_1, 0x01); //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|1, apicid_8131_1, 0x02); //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|2, apicid_8131_1, 0x03); //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|3, apicid_8131_1, 0x04); /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc)); return smp_next_mpe_entry(mc); }
static void *smp_write_config_table(void *v) { struct mp_config_table *mc; int bus_isa; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LAPIC_ADDR); smp_write_processors(mc); get_bus_conf(); mptable_write_buses(mc, NULL, &bus_isa); /*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, apicid_8111, 0x20, IO_APIC_ADDR); { device_t dev; struct resource *res; dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, apicid_8131_1, 0x20, res->base); } } dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, apicid_8131_2, 0x20, res->base); } } } mptable_add_isa_interrupts(mc, bus_isa, apicid_8111, 0); // // The commented-out lines are auto-detected on my servers. // /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ // Integrated SMBus 2.0 //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|3, apicid_8111 , 0x15); // Integrated AMD AC97 Audio //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|1, apicid_8111 , 0x11); //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|2, apicid_8111 , 0x12); // Integrated AMD USB smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, ( 0x4 <<2)|0, apicid_8111 , 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, ( 0x0 <<2)|3, apicid_8111 , 0x13); // On board ATI Rage XL //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, ( 0x5 <<2)|0, apicid_8111 , 0x14); // On board Broadcom nics smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, ( 0x3 <<2)|0, apicid_8131_2, 0x03); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, ( 0x3 <<2)|1, apicid_8131_2, 0x00); // On board LSI SCSI //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, ( 0x2 <<2)|0, apicid_8131_2, 0x02); // PCIX-133 Slot smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|0, apicid_8131_1, 0x01); //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|1, apicid_8131_1, 0x02); //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|2, apicid_8131_1, 0x03); //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|3, apicid_8131_1, 0x04); /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc)); return smp_next_mpe_entry(mc); }
static void *smp_write_config_table(void *v) { struct mp_config_table *mc; int bus_isa; unsigned char bus_pxhd_1; unsigned char bus_pxhd_2; unsigned char bus_pxhd_3; unsigned char bus_pxhd_4; unsigned char bus_ich5r_1; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LAPIC_ADDR); smp_write_processors(mc); { device_t dev; /* ich5r */ dev = dev_find_slot(0, PCI_DEVFN(0x1e,0)); if (dev) { bus_ich5r_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n"); bus_ich5r_1 = 7; } /* pxhd-1 */ dev = dev_find_slot(1, PCI_DEVFN(0x0,0)); if (dev) { bus_pxhd_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.0, using defaults\n"); bus_pxhd_1 = 2; } /* pxhd-2 */ dev = dev_find_slot(1, PCI_DEVFN(0x00,2)); if (dev) { bus_pxhd_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.2, using defaults\n"); bus_pxhd_2 = 3; } /* pxhd-3 */ dev = dev_find_slot(0, PCI_DEVFN(0x4,0)); if (dev) { bus_pxhd_3 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 0:04.0, using defaults\n"); bus_pxhd_3 = 5; } /* pxhd-4 */ dev = dev_find_slot(0, PCI_DEVFN(0x06,0)); if (dev) { bus_pxhd_4 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 0:06.0, using defaults\n"); bus_pxhd_4 = 6; } } mptable_write_buses(mc, NULL, &bus_isa); /* IOAPIC handling */ smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); { struct resource *res; device_t dev; /* pxhd apic 3 */ dev = dev_find_slot(1, PCI_DEVFN(0x00,1)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, 0x03, 0x20, res->base); } } else { printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.1\n"); } /* pxhd apic 4 */ dev = dev_find_slot(1, PCI_DEVFN(0x00,3)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, 0x04, 0x20, res->base); } } else { printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.3\n"); } } mptable_add_isa_interrupts(mc, bus_isa, 0x2, 0); /* ISA backward compatibility interrupts */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, 0x74, 0x02, 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, 0x76, 0x02, 0x12); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, 0x77, 0x02, 0x17); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, 0x75, 0x02, 0x13); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, 0x74, 0x02, 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, 0x7c, 0x02, 0x12); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, 0x7d, 0x02, 0x11); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pxhd_1, 0x08, 0x03, 0x00); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pxhd_1, 0x0c, 0x03, 0x06); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pxhd_1, 0x0d, 0x03, 0x07); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pxhd_2, 0x08, 0x04, 0x00); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ich5r_1, 0x04, 0x02, 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pxhd_4, 0x00, 0x02, 0x10); #if 0 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus_isa - 1), 0x04, 0x02, 0x10); #endif /* Standard local interrupt assignments */ #if 0 smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x00, MP_APIC_ALL, 0x00); #endif smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x00, MP_APIC_ALL, 0x01); /* There is no extension information... */ /* Compute the checksums */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc)); return smp_next_mpe_entry(mc); }
static void *smp_write_config_table(void *v) { struct mp_config_table *mc; int i, bus_isa; struct mb_sysconf_t *m; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LAPIC_ADDR); smp_write_processors(mc); get_bus_conf(); m = sysconf.mb; mptable_write_buses(mc, NULL, &bus_isa); /*I/O APICs: APIC ID Version State Address*/ { device_t dev = 0; struct resource *res; for(i=0; i<3; i++) { dev = dev_find_device(0x1166, 0x0235, dev); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, m->apicid_bcm5785[i], 0x11, res->base); } } } } mptable_add_isa_interrupts(mc, bus_isa, m->apicid_bcm5785[0], 0); //IDE outb(0x02, 0xc00); outb(0x0e, 0xc01); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_bcm5785_0, ((1+sysconf.sbdn)<<2)|1, m->apicid_bcm5785[0], 0xe); // IDE //SATA outb(0x07, 0xc00); outb(0x0f, 0xc01); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0xf); //USB outb(0x01, 0xc00); outb(0x0a, 0xc01); for(i=0;i<3;i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, ((2+sysconf.sbdn)<<2)|i, m->apicid_bcm5785[0], 0xa); // } /* enable int */ /* why here? must get the BAR and PCI command bit 1 set before enable it ....*/ { device_t dev; dev = dev_find_device(0x1166, 0x0205, 0); if(dev) { uint32_t dword; dword = pci_read_config32(dev, 0x6c); dword |= (1<<4); // enable interrupts pci_write_config32(dev, 0x6c, dword); } } //First pci-x slot (on bcm5785) under bus_bcm5785_1:d.0 // AIC 8130 Galileo Technology... for(i=0;i<4;i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1_1, (6<<2)|i, m->apicid_bcm5785[1], 2 + (1+i)%4); // } //pci slot (on bcm5785) for(i=0;i<4;i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (5<<2)|i, m->apicid_bcm5785[1], 8+i%4); // } //onboard ati smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (4<<2)|0, m->apicid_bcm5785[1], 0x1); //PCI-X on bcm5780 for(i=0;i<4;i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[1], (4<<2)|i, m->apicid_bcm5785[1], 2 + (0+i)%4); // } //onboard Broadcom for(i=0;i<2;i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[2], (4<<2)|i, m->apicid_bcm5785[1], 0xa + (0+i)%4); // } // First PCI-E x8 for(i=0;i<4;i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[5], (0<<2)|i, m->apicid_bcm5785[1], 0xe); // } // Second PCI-E x8 for(i=0;i<4;i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[3], (0<<2)|i, m->apicid_bcm5785[1], 0xc); // } // Third PCI-E x1 for(i=0;i<4;i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[4], (0<<2)|i, m->apicid_bcm5785[1], 0xd); // } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc)); return smp_next_mpe_entry(mc); }
static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; static const char oem[8] = "COREBOOT"; static const char productid[12] = "E325 "; struct mp_config_table *mc; unsigned char bus_num; unsigned char bus_isa; unsigned char bus_8111_0; unsigned char bus_8111_1; unsigned char bus_8131_1; unsigned char bus_8131_2; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); memset(mc, 0, sizeof(*mc)); memcpy(mc->mpc_signature, sig, sizeof(sig)); mc->mpc_length = sizeof(*mc); /* initially just the header */ mc->mpc_spec = 0x04; mc->mpc_checksum = 0; /* not yet computed */ memcpy(mc->mpc_oem, oem, sizeof(oem)); memcpy(mc->mpc_productid, productid, sizeof(productid)); mc->mpc_oemptr = 0; mc->mpc_oemsize = 0; mc->mpc_entry_count = 0; /* No entries yet... */ mc->mpc_lapic = LAPIC_ADDR; mc->mpe_length = 0; mc->mpe_checksum = 0; mc->reserved = 0; smp_write_processors(mc); { device_t dev; /* 8111 */ dev = dev_find_slot(1, PCI_DEVFN(0x03,0)); if (dev) { bus_8111_0 = pci_read_config8(dev, PCI_PRIMARY_BUS); bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_isa++; } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n"); bus_8111_0 = 1; bus_8111_1 = 4; bus_isa = 5; } /* 8131-1 */ dev = dev_find_slot(1, PCI_DEVFN(0x01,0)); if (dev) { bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n"); bus_8131_1 = 2; } /* 8131-2 */ dev = dev_find_slot(1, PCI_DEVFN(0x02,0)); if (dev) { bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n"); bus_8131_2 = 3; } } /* define bus and isa numbers */ for (bus_num = 0; bus_num < bus_isa; bus_num++) { smp_write_bus(mc, bus_num, "PCI "); } smp_write_bus(mc, bus_isa, "ISA "); /* Legacy IOAPIC #2 */ smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR); { device_t dev; struct resource *res; /* 8131-1 apic #3 */ dev = dev_find_slot(1, PCI_DEVFN(0x01,1)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, 0x03, 0x11, res->base); } } /* 8131-2 apic #4 */ dev = dev_find_slot(1, PCI_DEVFN(0x02,1)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, 0x04, 0x11, res->base); } } } mptable_add_isa_interrupts(mc, bus_isa, 0x2, 0); /* PCI Ints: Type Polarity Trigger Bus ID PCIDEVNUM|IRQ APIC ID PIN# */ /* Integrated SMBus 2.0 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_0, (0x04<<2)|3, 0x2, 0x13); /* Integrated AMD AC97 Audio */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_0, (0x04<<2)|1, 0x2, 0x11); /* Integrated AMD USB */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x00<<2)|3, 0x2, 0x13); /* On board ATI Rage XL */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x05<<2)|0, 0x2, 0x10); /* On board Broadcom nics */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|0, 0x3, 0x00); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|1, 0x3, 0x01); /* On board LSI SCSI */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x02<<2)|0, 0x3, 0x02); /* PCI Slot 1 PCIX */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|0, 0x2, 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|1, 0x2, 0x11); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|2, 0x2, 0x12); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|3, 0x2, 0x13); /* PCI Slot 2 PCIX */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|0, 0x2, 0x11); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|1, 0x2, 0x12); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|2, 0x2, 0x13); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|3, 0x2, 0x10); /* Standard local interrupt assignments: * Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x00, MP_APIC_ALL, 0x00); smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x00, MP_APIC_ALL, 0x01); /* There is no extension information... */ /* Compute the checksums */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc)); return smp_next_mpe_entry(mc); }