static int adau1701_write(struct snd_soc_codec *codec, unsigned int reg,
unsigned int value)
{
unsigned int i;
unsigned int size;
uint8_t buf[4];
int ret;
size = adau1701_register_size(codec, reg);
if (size == 0)
return -EINVAL;
snd_soc_cache_write(codec, reg, value);
buf[0] = 0x08;
buf[1] = reg;
for (i = size + 1; i >= 2; --i) {
buf[i] = value;
value >>= 8;
}
ret = i2c_master_send(to_i2c_client(codec->dev), buf, size + 2);
if (ret == size + 2)
return 0;
else if (ret < 0)
return ret;
else
return -EIO;
}
static int do_hw_write(struct snd_soc_codec *codec, unsigned int reg,
unsigned int value, const void *data, int len)
{
int ret;
if (!snd_soc_codec_volatile_register(codec, reg) &&
reg < codec->driver->reg_cache_size &&
!codec->cache_bypass) {
ret = snd_soc_cache_write(codec, reg, value);
if (ret < 0)
return -1;
}
if (codec->cache_only) {
codec->cache_sync = 1;
return 0;
}
ret = codec->hw_write(codec->control_data, data, len);
if (ret == len)
return 0;
if (ret < 0)
return ret;
else
return -EIO;
}
static int lm4857_write(struct snd_soc_codec *codec, unsigned int reg,
unsigned int value)
{
uint8_t data;
int ret;
ret = snd_soc_cache_write(codec, reg, value);
if (ret < 0)
return ret;
data = (reg << 6) | value;
ret = i2c_master_send(codec->control_data, &data, 1);
if (ret != 1) {
dev_err(codec->dev, "Failed to write register: %d\n", ret);
return ret;
}
return 0;
}
static int hw_write(struct snd_soc_codec *codec, unsigned int reg,
unsigned int value)
{
int ret;
if (!snd_soc_codec_volatile_register(codec, reg) &&
reg < codec->driver->reg_cache_size &&
!codec->cache_bypass) {
ret = snd_soc_cache_write(codec, reg, value);
if (ret < 0)
return -1;
}
if (codec->cache_only) {
codec->cache_sync = 1;
return 0;
}
return regmap_write(codec->control_data, reg, value);
}
static int sta32x_probe(struct snd_soc_codec *codec)
{
struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec);
int i, ret = 0, thermal = 0;
sta32x->codec = codec;
sta32x->pdata = dev_get_platdata(codec->dev);
/* regulators */
for (i = 0; i < ARRAY_SIZE(sta32x->supplies); i++)
sta32x->supplies[i].supply = sta32x_supply_names[i];
ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(sta32x->supplies),
sta32x->supplies);
if (ret != 0) {
dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
goto err;
}
ret = regulator_bulk_enable(ARRAY_SIZE(sta32x->supplies),
sta32x->supplies);
if (ret != 0) {
dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
goto err_get;
}
/* Tell ASoC what kind of I/O to use to read the registers. ASoC will
* then do the I2C transactions itself.
*/
ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_I2C);
if (ret < 0) {
dev_err(codec->dev, "failed to set cache I/O (ret=%i)\n", ret);
return ret;
}
/* Chip documentation explicitly requires that the reset values
* of reserved register bits are left untouched.
* Write the register default value to cache for reserved registers,
* so the write to the these registers are suppressed by the cache
* restore code when it skips writes of default registers.
*/
snd_soc_cache_write(codec, STA32X_CONFC, 0xc2);
snd_soc_cache_write(codec, STA32X_CONFE, 0xc2);
snd_soc_cache_write(codec, STA32X_CONFF, 0x5c);
snd_soc_cache_write(codec, STA32X_MMUTE, 0x10);
snd_soc_cache_write(codec, STA32X_AUTO1, 0x60);
snd_soc_cache_write(codec, STA32X_AUTO3, 0x00);
snd_soc_cache_write(codec, STA32X_C3CFG, 0x40);
/* set thermal warning adjustment and recovery */
if (!(sta32x->pdata->thermal_conf & STA32X_THERMAL_ADJUSTMENT_ENABLE))
thermal |= STA32X_CONFA_TWAB;
if (!(sta32x->pdata->thermal_conf & STA32X_THERMAL_RECOVERY_ENABLE))
thermal |= STA32X_CONFA_TWRB;
snd_soc_update_bits(codec, STA32X_CONFA,
STA32X_CONFA_TWAB | STA32X_CONFA_TWRB,
thermal);
/* select output configuration */
snd_soc_update_bits(codec, STA32X_CONFF,
STA32X_CONFF_OCFG_MASK,
sta32x->pdata->output_conf
<< STA32X_CONFF_OCFG_SHIFT);
/* channel to output mapping */
snd_soc_update_bits(codec, STA32X_C1CFG,
STA32X_CxCFG_OM_MASK,
sta32x->pdata->ch1_output_mapping
<< STA32X_CxCFG_OM_SHIFT);
snd_soc_update_bits(codec, STA32X_C2CFG,
STA32X_CxCFG_OM_MASK,
sta32x->pdata->ch2_output_mapping
<< STA32X_CxCFG_OM_SHIFT);
snd_soc_update_bits(codec, STA32X_C3CFG,
STA32X_CxCFG_OM_MASK,
sta32x->pdata->ch3_output_mapping
<< STA32X_CxCFG_OM_SHIFT);
/* initialize coefficient shadow RAM with reset values */
for (i = 4; i <= 49; i += 5)
sta32x->coef_shadow[i] = 0x400000;
for (i = 50; i <= 54; i++)
sta32x->coef_shadow[i] = 0x7fffff;
sta32x->coef_shadow[55] = 0x5a9df7;
sta32x->coef_shadow[56] = 0x7fffff;
sta32x->coef_shadow[59] = 0x7fffff;
sta32x->coef_shadow[60] = 0x400000;
sta32x->coef_shadow[61] = 0x400000;
if (sta32x->pdata->needs_esd_watchdog)
INIT_DELAYED_WORK(&sta32x->watchdog_work, sta32x_watchdog);
sta32x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
/* Bias level configuration will have done an extra enable */
regulator_bulk_disable(ARRAY_SIZE(sta32x->supplies), sta32x->supplies);
return 0;
err_get:
regulator_bulk_free(ARRAY_SIZE(sta32x->supplies), sta32x->supplies);
err:
return ret;
}