static void __init ath79_misc_irq_init(void) { void __iomem *base = ath79_reset_base; int i; __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE); __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS); if (soc_is_ar71xx() || soc_is_ar913x()) ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask; else if (soc_is_ar724x() || soc_is_ar933x() || soc_is_ar934x() || soc_is_qca953x() || soc_is_qca955x()) ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack; else BUG(); for (i = ATH79_MISC_IRQ_BASE; i < ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT; i++) { irq_set_chip_and_handler(i, &ath79_misc_irq_chip, handle_level_irq); } irq_set_chained_handler(ATH79_CPU_IRQ(6), ath79_misc_irq_handler); }
void __init ath79_register_uart(void) { unsigned long uart_clk_rate; uart_clk_rate = ath79_get_sys_clk_rate("uart"); if (soc_is_ar71xx()) ath79_gpio_function_enable(AR71XX_GPIO_FUNC_UART_EN); else if (soc_is_ar724x()) ath79_gpio_function_enable(AR724X_GPIO_FUNC_UART_EN); else if (soc_is_ar913x()) ath79_gpio_function_enable(AR913X_GPIO_FUNC_UART_EN); else if (soc_is_ar933x()) ath79_gpio_function_enable(AR933X_GPIO_FUNC_UART_EN); if (soc_is_ar71xx() || soc_is_ar724x() || soc_is_ar913x() || soc_is_ar934x() || soc_is_qca953x() || soc_is_qca955x()) { ath79_uart_data[0].uartclk = uart_clk_rate; platform_device_register(&ath79_uart_device); } else if (soc_is_ar933x()) { platform_device_register(&ar933x_uart_device); } else { BUG(); } }
void __init ath79_register_uart(void) { struct clk *clk; clk = clk_get(NULL, "uart"); if (IS_ERR(clk)) panic("unable to get UART clock, err=%ld", PTR_ERR(clk)); if (soc_is_ar71xx()) ath79_gpio_function_enable(AR71XX_GPIO_FUNC_UART_EN); else if (soc_is_ar724x()) ath79_gpio_function_enable(AR724X_GPIO_FUNC_UART_EN); else if (soc_is_ar913x()) ath79_gpio_function_enable(AR913X_GPIO_FUNC_UART_EN); else if (soc_is_ar933x()) ath79_gpio_function_enable(AR933X_GPIO_FUNC_UART_EN); if (soc_is_ar71xx() || soc_is_ar724x() || soc_is_ar913x() || soc_is_ar934x() || soc_is_qca953x() || soc_is_qca955x()) { ath79_uart_data[0].uartclk = clk_get_rate(clk); platform_device_register(&ath79_uart_device); } else if (soc_is_ar933x()) { ar933x_uart_data.uartclk = clk_get_rate(clk); platform_device_register(&ar933x_uart_device); } else { BUG(); } }
void ath79_device_reset_clear(u32 mask) { unsigned long flags; u32 reg; u32 t; if (soc_is_ar71xx()) reg = AR71XX_RESET_REG_RESET_MODULE; else if (soc_is_ar724x()) reg = AR724X_RESET_REG_RESET_MODULE; else if (soc_is_ar913x()) reg = AR913X_RESET_REG_RESET_MODULE; else if (soc_is_ar933x()) reg = AR933X_RESET_REG_RESET_MODULE; else if (soc_is_ar934x()) reg = AR934X_RESET_REG_RESET_MODULE; else if (soc_is_qca953x()) reg = QCA953X_RESET_REG_RESET_MODULE; else if (soc_is_qca955x()) reg = QCA955X_RESET_REG_RESET_MODULE; else panic("Reset register not defined for this SOC"); spin_lock_irqsave(&ath79_device_reset_lock, flags); t = ath79_reset_rr(reg); ath79_reset_wr(reg, t & ~mask); spin_unlock_irqrestore(&ath79_device_reset_lock, flags); }
void __init arch_init_irq(void) { if (soc_is_ar71xx()) { ath79_ip2_handler = ar71xx_ip2_handler; ath79_ip3_handler = ar71xx_ip3_handler; } else if (soc_is_ar724x()) { ath79_ip2_handler = ar724x_ip2_handler; ath79_ip3_handler = ar724x_ip3_handler; } else if (soc_is_ar913x()) { ath79_ip2_handler = ar913x_ip2_handler; ath79_ip3_handler = ar913x_ip3_handler; } else if (soc_is_ar933x()) { ath79_ip2_handler = ar933x_ip2_handler; ath79_ip3_handler = ar933x_ip3_handler; } else if (soc_is_ar934x()) { ath79_ip2_handler = ath79_default_ip2_handler; ath79_ip3_handler = ar934x_ip3_handler; } else if (soc_is_qca953x()) { ath79_ip2_handler = ath79_default_ip2_handler; ath79_ip3_handler = ath79_default_ip3_handler; } else if (soc_is_qca955x()) { ath79_ip2_handler = ath79_default_ip2_handler; ath79_ip3_handler = ath79_default_ip3_handler; } else { BUG(); } cp0_perfcount_irq = ATH79_MISC_IRQ(5); mips_cpu_irq_init(); ath79_misc_irq_init(); if (soc_is_ar934x()) ar934x_ip2_irq_init(); else if (soc_is_qca955x()) qca955x_irq_init(); }
static void __init ath79_detect_sys_type(void) { char *chip = "????"; u32 id; u32 major; u32 minor; u32 rev = 0; u32 ver = 1; id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID); major = id & REV_ID_MAJOR_MASK; switch (major) { case REV_ID_MAJOR_AR71XX: minor = id & AR71XX_REV_ID_MINOR_MASK; rev = id >> AR71XX_REV_ID_REVISION_SHIFT; rev &= AR71XX_REV_ID_REVISION_MASK; switch (minor) { case AR71XX_REV_ID_MINOR_AR7130: ath79_soc = ATH79_SOC_AR7130; chip = "7130"; break; case AR71XX_REV_ID_MINOR_AR7141: ath79_soc = ATH79_SOC_AR7141; chip = "7141"; break; case AR71XX_REV_ID_MINOR_AR7161: ath79_soc = ATH79_SOC_AR7161; chip = "7161"; break; } break; case REV_ID_MAJOR_AR7240: ath79_soc = ATH79_SOC_AR7240; chip = "7240"; rev = id & AR724X_REV_ID_REVISION_MASK; break; case REV_ID_MAJOR_AR7241: ath79_soc = ATH79_SOC_AR7241; chip = "7241"; rev = id & AR724X_REV_ID_REVISION_MASK; break; case REV_ID_MAJOR_AR7242: ath79_soc = ATH79_SOC_AR7242; chip = "7242"; rev = id & AR724X_REV_ID_REVISION_MASK; break; case REV_ID_MAJOR_AR913X: minor = id & AR913X_REV_ID_MINOR_MASK; rev = id >> AR913X_REV_ID_REVISION_SHIFT; rev &= AR913X_REV_ID_REVISION_MASK; switch (minor) { case AR913X_REV_ID_MINOR_AR9130: ath79_soc = ATH79_SOC_AR9130; chip = "9130"; break; case AR913X_REV_ID_MINOR_AR9132: ath79_soc = ATH79_SOC_AR9132; chip = "9132"; break; } break; case REV_ID_MAJOR_AR9330: ath79_soc = ATH79_SOC_AR9330; chip = "9330"; rev = id & AR933X_REV_ID_REVISION_MASK; break; case REV_ID_MAJOR_AR9331: ath79_soc = ATH79_SOC_AR9331; chip = "9331"; rev = id & AR933X_REV_ID_REVISION_MASK; break; case REV_ID_MAJOR_AR9341: ath79_soc = ATH79_SOC_AR9341; chip = "9341"; rev = id & AR934X_REV_ID_REVISION_MASK; break; case REV_ID_MAJOR_AR9342: ath79_soc = ATH79_SOC_AR9342; chip = "9342"; rev = id & AR934X_REV_ID_REVISION_MASK; break; case REV_ID_MAJOR_AR9344: ath79_soc = ATH79_SOC_AR9344; chip = "9344"; rev = id & AR934X_REV_ID_REVISION_MASK; break; case REV_ID_MAJOR_QCA9533_V2: ver = 2; ath79_soc_rev = 2; /* drop through */ case REV_ID_MAJOR_QCA9533: ath79_soc = ATH79_SOC_QCA9533; chip = "9533"; rev = id & QCA953X_REV_ID_REVISION_MASK; break; case REV_ID_MAJOR_QCA9556: ath79_soc = ATH79_SOC_QCA9556; chip = "9556"; rev = id & QCA955X_REV_ID_REVISION_MASK; break; case REV_ID_MAJOR_QCA9558: ath79_soc = ATH79_SOC_QCA9558; chip = "9558"; rev = id & QCA955X_REV_ID_REVISION_MASK; break; case REV_ID_MAJOR_QCA956X: ath79_soc = ATH79_SOC_QCA956X; chip = "956X"; rev = id & QCA956X_REV_ID_REVISION_MASK; break; case REV_ID_MAJOR_TP9343: ath79_soc = ATH79_SOC_TP9343; chip = "9343"; rev = id & QCA956X_REV_ID_REVISION_MASK; break; default: panic("ath79: unknown SoC, id:0x%08x", id); } if (ver == 1) ath79_soc_rev = rev; if (soc_is_qca953x() || soc_is_qca955x() || soc_is_qca956x()) sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u", chip, ver, rev); else if (soc_is_tp9343()) sprintf(ath79_sys_type, "Qualcomm Atheros TP%s rev %u", chip, rev); else sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev); pr_info("SoC: %s\n", ath79_sys_type); }