void spm_go_to_sodi(u32 spm_flags, u32 spm_data) { struct wake_status wakesta; unsigned long flags; struct mtk_irq_mask mask; wake_reason_t wr = WR_NONE; struct pcm_desc *pcmdesc = __spm_sodi.pcmdesc; struct pwr_ctrl *pwrctrl = __spm_sodi.pwrctrl; int vcore_status = 0; //0:disable, 1:HPM, 2:LPM #if SPM_AEE_RR_REC aee_rr_rec_sodi_val(1<<SPM_SODI_ENTER); #endif #if defined (CONFIG_ARM_PSCI)||defined(CONFIG_MTK_PSCI) spm_flags &= ~SPM_DISABLE_ATF_ABORT; #else spm_flags |= SPM_DISABLE_ATF_ABORT; #endif if(gSpm_SODI_mempll_pwr_mode == 1) { spm_flags |= SPM_MEMPLL_CG_EN; //MEMPLL CG mode } else { spm_flags &= ~SPM_MEMPLL_CG_EN; //DDRPHY power down mode } set_pwrctrl_pcm_flags(pwrctrl, spm_flags); //If Vcore DVFS is disable, force to disable SODI internal Vcore DVS if (pwrctrl->pcm_flags_cust == 0) { if ((pwrctrl->pcm_flags & SPM_VCORE_DVFS_EN) == 0) { pwrctrl->pcm_flags |= SPM_VCORE_DVS_EVENT_DIS; } } //SODI will not decrease Vcore voltage in HPM mode. if ((pwrctrl->pcm_flags & SPM_VCORE_DVS_EVENT_DIS) == 0) { if (get_ddr_khz() != FDDR_S1_KHZ) { #if SPM_AEE_RR_REC aee_rr_rec_sodi_val(aee_rr_curr_sodi_val()|(1<<SPM_SODI_VCORE_HPM)); #endif /* //modify by mtk //if DRAM freq is high,SPM will not enter event_vector to enter EMI self-refresh if(pwrctrl->pcm_flags_cust == 0) { pwrctrl->pcm_flags|=0x80; } */ vcore_status = 1; //printk("SODI: get_ddr_khz() = %d\n", get_ddr_khz()); } else { #if SPM_AEE_RR_REC aee_rr_rec_sodi_val(aee_rr_curr_sodi_val()|(1<<SPM_SODI_VCORE_LPM)); #endif vcore_status = 2; } } //enable APxGPT timer soidle_before_wfi(0); lockdep_off(); spin_lock_irqsave(&__spm_lock, flags); mt_irq_mask_all(&mask); mt_irq_unmask_for_sleep(SPM_IRQ0_ID); mt_cirq_clone_gic(); mt_cirq_enable(); #if SPM_AEE_RR_REC aee_rr_rec_sodi_val(aee_rr_curr_sodi_val()|(1<<SPM_SODI_ENTER_UART_SLEEP)); #endif if (request_uart_to_sleep()) { wr = WR_UART_BUSY; goto RESTORE_IRQ; } #if SPM_AEE_RR_REC aee_rr_rec_sodi_val(aee_rr_curr_sodi_val()|(1<<SPM_SODI_ENTER_SPM_FLOW)); #endif __spm_reset_and_init_pcm(pcmdesc); /* * When commond-queue is in shut-down mode, SPM will hang if it tries to access commond-queue status. * Follwoing patch is to let SODI driver to notify SPM that commond-queue is in shut-down mode or not to avoid above SPM hang issue. * But, now display can automatically notify SPM that command-queue is shut-down or not, so following code is not needed anymore. */ #if 0 //check GCE if(clock_is_on(MT_CG_INFRA_GCE)) { pwrctrl->pcm_flags &= ~SPM_DDR_HIGH_SPEED; } else { pwrctrl->pcm_flags |= SPM_DDR_HIGH_SPEED; } #endif __spm_kick_im_to_fetch(pcmdesc); __spm_init_pcm_register(); __spm_init_event_vector(pcmdesc); #if 0 //In D2, can not set apsrc_req bit in SODI. It is used by Vcore DVS for GPU 550M in HPM mode //Display set SPM_PCM_SRC_REQ[0]=1'b1 to force DRAM not enter self-refresh mode if((spm_read(SPM_PCM_SRC_REQ)&0x00000001)) { pwrctrl->pcm_apsrc_req = 1; } else { pwrctrl->pcm_apsrc_req = 0; } #endif __spm_set_power_control(pwrctrl); __spm_set_wakeup_event(pwrctrl); #if SODI_DVT_PCM_TIMER_DISABLE //PCM_Timer is enable in above '__spm_set_wakeup_event(pwrctrl);', disable PCM Timer here spm_write(SPM_PCM_CON1 ,spm_read(SPM_PCM_CON1)&(~CON1_PCM_TIMER_EN)); #endif spm_sodi_pre_process(); __spm_kick_pcm_to_run(pwrctrl); #if SPM_SODI_DUMP_REGS printk("============SODI Before============\n"); spm_sodi_dump_regs(); //dump debug info #endif #if SPM_AEE_RR_REC aee_rr_rec_sodi_val(aee_rr_curr_sodi_val()|(1<<SPM_SODI_ENTER_WFI)); #endif #ifdef SPM_SODI_PROFILE_TIME gpt_get_cnt(SPM_SODI_PROFILE_APXGPT,&soidle_profile[1]); #endif spm_trigger_wfi_for_sodi(pwrctrl); #ifdef SPM_SODI_PROFILE_TIME gpt_get_cnt(SPM_SODI_PROFILE_APXGPT,&soidle_profile[2]); #endif #if SPM_AEE_RR_REC aee_rr_rec_sodi_val(aee_rr_curr_sodi_val()|(1<<SPM_SODI_LEAVE_WFI)); #endif #if SPM_SODI_DUMP_REGS printk("============SODI After=============\n"); spm_sodi_dump_regs();//dump debug info #endif spm_sodi_post_process(); __spm_get_wakeup_status(&wakesta); sodi_debug("emi-selfrefrsh cnt = %d, pcm_flag = 0x%x, SPM_PCM_RESERVE2 = 0x%x, vcore_status = %d, %s\n", spm_read(SPM_PCM_PASR_DPD_3), spm_read(SPM_PCM_FLAGS), spm_read(SPM_PCM_RESERVE2), vcore_status, pcmdesc->version); __spm_clean_after_wakeup(); #if SPM_AEE_RR_REC aee_rr_rec_sodi_val(aee_rr_curr_sodi_val()|(1<<SPM_SODI_ENTER_UART_AWAKE)); #endif request_uart_to_wakeup(); wr = __spm_output_wake_reason(&wakesta, pcmdesc, false); if (wr == WR_PCM_ASSERT) { sodi_err("PCM ASSERT AT %u (%s), r13 = 0x%x, debug_flag = 0x%x\n", wakesta.assert_pc, pcmdesc->version, wakesta.r13, wakesta.debug_flag); } #if SPM_AEE_RR_REC aee_rr_rec_sodi_val(aee_rr_curr_sodi_val()|(1<<SPM_SODI_LEAVE_SPM_FLOW)); #endif RESTORE_IRQ: mt_cirq_flush(); mt_cirq_disable(); mt_irq_mask_restore(&mask); spin_unlock_irqrestore(&__spm_lock, flags); lockdep_on(); //stop APxGPT timer and enable caore0 local timer soidle_after_wfi(0); #if SODI_DVT_SPM_MEM_RW_TEST { static u32 magic_init = 0; int i =0; if(magic_init == 0){ magic_init++; printk("magicNumArray:0x%p",magicArray); } for(i=0;i<16;i++) { if(magicArray[i]!=SODI_DVT_MAGIC_NUM) { printk("Error: sodi magic number no match!!!"); ASSERT(0); } } if (i>=16) printk("SODI_DVT_SPM_MEM_RW_TEST pass (count = %d)\n", magic_init); } #endif #if SPM_AEE_RR_REC aee_rr_rec_sodi_val(0); #endif }
/* status RESERVED[0] : mcusys dormant RESERVED[1] : APSRCSLEEP - (pass CHECK_APSRCWAKE) RESERVED[2] : EMI self-refresh & mem ck off Options RESERVED[16] : skip arm pll cg/pd RESERVED[17] : skip arm pll pd RESERVED[18] : skip AXI 26 SWITCH RESERVED[19] : skip EMI self-refresh & mem ck off RESERVED[20] : skip mem ck off RESERVED[24] : stop after cpu power down / cpu pll off RESERVED[25] : stop after emi down / mem ck off */ wake_reason_t spm_go_to_sodi(bool sodi_en,int cpu) { wake_status_t *wakesta; unsigned long flags; struct mtk_irq_mask mask; wake_reason_t wr = WR_NONE; u32 con0; spin_lock_irqsave(&spm_lock, flags); spm_stop_normal(); mt_irq_mask_all(&mask); mt_irq_unmask_for_sleep(MT_SPM0_IRQ_ID); mt_cirq_clone_gic(); mt_cirq_enable(); spm_direct_enable_sodi(); spm_write(SPM_PCM_RESERVE,pcm_config_sodi.pcm_reserved); #ifdef SPM_SODI_SECONDARY_KICK_IMPROVE if( spm_last_senario != pcm_config_sodi.scenario)//MCDI SPM Initialize #endif { //spm_direct_enable_sodi(); if (spm_init_pcm(&pcm_config_sodi)==false) goto RESTORE_IRQ; spm_write(SPM_SLEEP_CPU_IRQ_MASK,0x1); spm_write(SPM_PCM_CON1,(spm_read(SPM_PCM_CON1)| CON1_CFG_KEY )&0xffffffdf);//temporary disable pcm timer spm_wfi_sel(pcm_config_sodi.wfi_sel, SPM_CORE0_WFI_SEL_SW_MASK ); spm_wfi_sel(pcm_config_sodi.wfi_sel, SPM_CORE1_WFI_SEL_SW_MASK ); spm_kick_pcm(&pcm_config_sodi); spm_change_fw = 1; } #ifdef SPM_SODI_SECONDARY_KICK_IMPROVE else { spm_write(SPM_SLEEP_CPU_IRQ_MASK,0x1); spm_wfi_sel(pcm_config_sodi.wfi_sel, SPM_CORE0_WFI_SEL_SW_MASK ); spm_wfi_sel(pcm_config_sodi.wfi_sel, SPM_CORE1_WFI_SEL_SW_MASK ); if( spm_secondary_kick(&pcm_config_sodi)==false) goto RESTORE_IRQ; spm_change_fw = 0; } #endif //gpiodbg_infra_dbg_out();//measure bus clock to LPD15 soidle_before_wfi(); spm_trigger_wfi_for_dpidle(1);//SODI with cpu dormant soidle_after_wfi(sodi_en); wakesta = spm_get_wakeup_status(&pcm_config_sodi); wr = wakesta->wake_reason; spm_clean_after_wakeup(); spm_write(SPM_PCM_CON1,(spm_read(SPM_PCM_CON1)| CON1_CFG_KEY )|(CON1_PCM_TIMER_EN)); RESTORE_IRQ: mt_cirq_flush(); mt_cirq_disable(); mt_irq_mask_restore(&mask); spm_go_to_normal(); spin_unlock_irqrestore(&spm_lock, flags); return wr; }
wake_reason_t spm_go_to_mcdi_ipi_test(int cpu) { wake_status_t *wakesta; unsigned long flags; struct mtk_irq_mask mask; wake_reason_t wr = WR_NONE; u32 con0; bool sodi_en = 0; spin_lock_irqsave(&spm_lock, flags); //mt_irq_mask_all(&mask); //mt_irq_unmask_for_sleep(MT_SPM0_IRQ_ID); if(cpu==0)//except mcdi { mt_irq_mask_all(&mask); mt_irq_unmask_for_sleep(MT_SPM0_IRQ_ID); //spm_wdt_config(false); mt_cirq_clone_gic(); mt_cirq_enable(); } pcm_config_sodi.spm_request_uart_sleep = true; pcm_config_sodi.wake_src=WAKE_SRC_FOR_SODI; if((sodi_en==1)&&(cpu==0))//SODI { spm_direct_enable_sodi(); pcm_config_sodi.wfi_sel[0]=true; pcm_config_sodi.wfi_sel[1]=true; pcm_config_sodi.wfi_scu_mask=false; pcm_config_sodi.wfi_l2c_mask=false; spm_write(SPM_PCM_RESERVE,spm_read(SPM_PCM_RESERVE)&~0x1); } else if((sodi_en==0)&&(cpu==0))//CPU Dormant { pcm_config_sodi.wfi_sel[0]=true; pcm_config_sodi.wfi_sel[1]=true; pcm_config_sodi.wfi_scu_mask=false; pcm_config_sodi.wfi_l2c_mask=false; spm_direct_disable_sodi(); spm_write(SPM_PCM_RESERVE,spm_read(SPM_PCM_RESERVE)&~0x1); } else if((sodi_en==0)&&(cpu!=0))//MCDI { //pcm_config_sodi.wake_src=WAKE_SRC_FOR_MCDI; pcm_config_sodi.wake_src=0x0;//for test IPI only pcm_config_sodi.wfi_sel[0]=false; pcm_config_sodi.wfi_sel[1]=true; pcm_config_sodi.wfi_scu_mask=true; pcm_config_sodi.wfi_l2c_mask=true; pcm_config_sodi.spm_request_uart_sleep = false; spm_direct_disable_sodi(); spm_write(SPM_PCM_RESERVE,spm_read(SPM_PCM_RESERVE)|0x1); } else { printk("[SPM]Wrong para!!\n"); goto RESTORE_IRQ; } if( spm_last_senario != pcm_config_sodi.scenario)//MCDI SPM Initialize { //spm_direct_enable_sodi(); if (spm_init_pcm(&pcm_config_sodi)==false) goto RESTORE_IRQ; if(cpu==1)//except mcdi { spm_write(SPM_SLEEP_CPU_IRQ_MASK,0x2); spm_mcdi_init_core_mux(); } else spm_write(SPM_SLEEP_CPU_IRQ_MASK,0x1); spm_write(SPM_PCM_CON1,(spm_read(SPM_PCM_CON1)| CON1_CFG_KEY )&0xffffffdf);//temporary disable pcm timer spm_wfi_sel(pcm_config_sodi.wfi_sel, SPM_CORE0_WFI_SEL_SW_MASK ); spm_wfi_sel(pcm_config_sodi.wfi_sel, SPM_CORE1_WFI_SEL_SW_MASK ); spm_kick_pcm(&pcm_config_sodi); //spm_wfi_sel(pcm_config_sodi.wfi_sel, SPM_CORE0_WFI_SEL_SW_MASK ); //spm_wfi_sel(pcm_config_sodi.wfi_sel, SPM_CORE1_WFI_SEL_SW_MASK ); spm_change_fw = 1; } else { if(cpu==1)//except mcdi { spm_write(SPM_SLEEP_CPU_IRQ_MASK,0x2); //spm_mcdi_init_core_mux(); } else spm_write(SPM_SLEEP_CPU_IRQ_MASK,0x1); spm_wfi_sel(pcm_config_sodi.wfi_sel, SPM_CORE0_WFI_SEL_SW_MASK ); spm_wfi_sel(pcm_config_sodi.wfi_sel, SPM_CORE1_WFI_SEL_SW_MASK ); if( spm_secondary_kick(&pcm_config_sodi)==false) goto RESTORE_IRQ; spm_change_fw = 0; } if(cpu==0) { soidle_before_wfi(); spm_trigger_wfi_for_dpidle(1);//SODI with cpu dormant soidle_after_wfi(sodi_en); } else { spm_pre_SPM_PCM_SW_INT_SET=spm_read(SPM_PCM_SW_INT_SET); spm_pre_SPM_SLEEP_ISR_STATUS=spm_read(SPM_SLEEP_ISR_STATUS); spm_write(SPM_PCM_SW_INT_CLEAR,0xf); //mcidle_before_wfi(cpu); if (!cpu_power_down(DORMANT_MODE)) { switch_to_amp(); /* do not add code here */ wfi_with_sync(); } switch_to_smp(); cpu_check_dormant_abort(); //mcidle_after_wfi(cpu); spm_post_SPM_PCM_SW_INT_SET=spm_read(SPM_PCM_SW_INT_SET); spm_post_SPM_SLEEP_ISR_STATUS=spm_read(SPM_SLEEP_ISR_STATUS); spm_post_SPM_PCM_RESERVE = spm_read(SPM_PCM_RESERVE ); } #if 1 wakesta = spm_get_wakeup_status(&pcm_config_sodi); wr = wakesta->wake_reason; #endif spm_clean_after_wakeup(); spm_write(SPM_PCM_CON1,(spm_read(SPM_PCM_CON1)| CON1_CFG_KEY )|(CON1_PCM_TIMER_EN)); RESTORE_IRQ: if(cpu==0)//except mcdi { mt_cirq_flush(); mt_cirq_disable(); mt_irq_mask_restore(&mask); } //mt_irq_mask_restore(&mask); spin_unlock_irqrestore(&spm_lock, flags); return wr; }
void spm_go_to_sodi(u32 spm_flags, u32 spm_data) { struct wake_status wakesta; unsigned long flags; struct mtk_irq_mask mask; wake_reason_t wr = WR_NONE; struct pcm_desc *pcmdesc = __spm_sodi.pcmdesc; struct pwr_ctrl *pwrctrl = __spm_sodi.pwrctrl; #if SPM_AEE_RR_REC aee_rr_rec_sodi_val(1<<SPM_SODI_ENTER); #endif set_pwrctrl_pcm_flags(pwrctrl, spm_flags); /* set PMIC WRAP table for deepidle power control */ mt_cpufreq_set_pmic_phase(PMIC_WRAP_PHASE_SODI); soidle_before_wfi(0); lockdep_off(); spin_lock_irqsave(&__spm_lock, flags); mt_irq_mask_all(&mask); mt_irq_unmask_for_sleep(SPM_IRQ0_ID/*MT_SPM_IRQ_ID*/); mt_cirq_clone_gic(); mt_cirq_enable(); #if SPM_AEE_RR_REC aee_rr_rec_sodi_val(aee_rr_curr_sodi_val()|(1<<SPM_SODI_ENTER_SPM_FLOW)); #endif __spm_reset_and_init_pcm(pcmdesc); #if 0 /* 0: mempll shutdown mode; 1: cg mode */ gSpm_SODI_mempll_pwr_mode ? (pwrctrl->pcm_flags |= SPM_MEMPLL_CPU) : (pwrctrl->pcm_flags &= ~SPM_MEMPLL_CPU); #endif __spm_kick_im_to_fetch(pcmdesc); __spm_init_pcm_register(); __spm_init_event_vector(pcmdesc); /* set pcm_apsrc_req to be 1 if 10006b0c[0] is 1 */ if ((spm_read(SPM_PCM_SRC_REQ) & 1) || pwrctrl->pcm_apsrc_req) pwrctrl->pcm_apsrc_req = 1; else pwrctrl->pcm_apsrc_req = 0; __spm_set_power_control(pwrctrl); __spm_set_wakeup_event(pwrctrl); /* set pcm_flags[18] to be 1 if 10006b08[7] is 1 */ if ((spm_read(SPM_PCM_FLAGS) & SPM_MEMPLL_RESET) || gSpm_SODI_mempll_pwr_mode || (pwrctrl->pcm_flags_cust & SPM_MEMPLL_CPU)) pwrctrl->pcm_flags |= SPM_MEMPLL_CPU; else pwrctrl->pcm_flags &= ~SPM_MEMPLL_CPU; __spm_kick_pcm_to_run(pwrctrl); #if SPM_AEE_RR_REC aee_rr_rec_sodi_val(aee_rr_curr_sodi_val()|(1<<SPM_SODI_ENTER_WFI)); #endif spm_trigger_wfi_for_sodi(pwrctrl); #if SPM_AEE_RR_REC aee_rr_rec_sodi_val(aee_rr_curr_sodi_val()|(1<<SPM_SODI_LEAVE_WFI)); #endif __spm_get_wakeup_status(&wakesta); __spm_clean_after_wakeup(); wr = __spm_output_wake_reason(&wakesta, pcmdesc, false); /* for test */ /* wr = __spm_output_wake_reason(&wakesta, pcmdesc, true); */ #if SPM_AEE_RR_REC aee_rr_rec_sodi_val(aee_rr_curr_sodi_val()|(1<<SPM_SODI_LEAVE_SPM_FLOW)); #endif mt_cirq_flush(); mt_cirq_disable(); mt_irq_mask_restore(&mask); spin_unlock_irqrestore(&__spm_lock, flags); lockdep_on(); soidle_after_wfi(0); /* set PMIC WRAP table for normal power control */ mt_cpufreq_set_pmic_phase(PMIC_WRAP_PHASE_NORMAL); #if SPM_AEE_RR_REC aee_rr_rec_sodi_val(0); #endif //return wr; }