int __init arch_clockchip_init(void)
{
int rc;
u32 val;
virtual_addr_t sctl_base;
/* Map control registers */
sctl_base = vmm_host_iomap(V2M_SYSCTL, 0x1000);
/* Select 1MHz TIMCLK as the reference clock for SP804 timers */
val = vmm_readl((void *)sctl_base) | SCCTRL_TIMEREN0SEL_TIMCLK;
vmm_writel(val, (void *)sctl_base);
/* Unmap control register */
rc = vmm_host_iounmap(sctl_base, 0x1000);
if (rc) {
return rc;
}
/* Map timer0 registers */
ca9x4_timer0_base = vmm_host_iomap(V2M_TIMER0, 0x1000);
/* Initialize timer0 as clockchip */
rc = sp804_clockchip_init(ca9x4_timer0_base, IRQ_V2M_TIMER0,
"sp804_timer0", 300, 1000000, 0);
if (rc) {
return rc;
}
return VMM_OK;
}
int __init arch_clockchip_init(void)
{
int rc;
u32 val;
virtual_addr_t sctl_base;
/* Map control registers */
sctl_base = vmm_host_iomap(VERSATILE_SCTL_BASE, 0x1000);
/*
* set clock frequency:
* REALVIEW_REFCLK is 32KHz
* REALVIEW_TIMCLK is 1MHz
*/
val = vmm_readl((void *)sctl_base) |
(VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel);
vmm_writel(val, (void *)sctl_base);
/* Unmap control register */
rc = vmm_host_iounmap(sctl_base, 0x1000);
if (rc) {
return rc;
}
/* Map timer0 registers */
sp804_timer0_base = vmm_host_iomap(VERSATILE_TIMER0_1_BASE, 0x1000);
/* Initialize timer0 as clockchip */
rc = sp804_clockchip_init(sp804_timer0_base, INT_TIMERINT0_1,
"sp804_timer0", 300, 1000000, 0);
if (rc) {
return rc;
}
return VMM_OK;
}
