static int sunxi_spdif_resume(struct snd_soc_dai *cpu_dai)
{
u32 reg_val;
printk("[SPDIF]Enter %s\n", __func__);
#ifdef CONFIG_ARCH_SUN9IW1
/*spdf:dcdc1*/
spdif_vol = regulator_get(NULL, spdif_voltage.str);
if (!spdif_vol) {
printk("get audio spdif_vol failed\n");
return -EFAULT;
}
//regulator_set_voltage(spdif_vol, 3000000, 3000000);
regulator_enable(spdif_vol);
#endif
/*enable the module clock*/
if (clk_enable(spdif_moduleclk)) {
printk("try to enable spdif_moduleclk output failed!\n");
}
spdifregrestore();
reg_val = readl(sunxi_spdif.regs + SUNXI_SPDIF_CTL);
reg_val |= SUNXI_SPDIF_CTL_GEN;
writel(reg_val, sunxi_spdif.regs + SUNXI_SPDIF_CTL);
return 0;
}
static int sun5i_spdif_resume(struct snd_soc_dai *cpu_dai)
{
u32 reg_val;
printk("[SPDIF]Enter %s\n", __func__);
//disable the module clock
clk_enable(spdif_apbclk);
//enable the module clock
clk_enable(spdif_moduleclk);
spdifregrestore();
reg_val = readl(sun5i_spdif.regs + SUN5I_SPDIF_CTL);
reg_val |= SUN5I_SPDIF_CTL_GEN;
writel(reg_val, sun5i_spdif.regs + SUN5I_SPDIF_CTL);
//printk("[SPDIF]PLL2 0x01c20008 = %#x\n", *(volatile int*)0xF1C20008);
printk("[SPDIF]SPECIAL CLK 0x01c20068 = %#x, line= %d\n", *(volatile int*)0xF1C20068, __LINE__);
printk("[SPDIF]SPECIAL CLK 0x01c200C0 = %#x, line = %d\n", *(volatile int*)0xF1C200C0, __LINE__);
return 0;
}
