static int
spi_at91_set_config(cyg_spi_device *dev,
cyg_uint32 key,
const void *buf,
cyg_uint32 *len)
{
cyg_spi_at91_device_t *at91_spi_dev = (cyg_spi_at91_device_t *) dev;
switch (key)
{
case CYG_IO_SET_CONFIG_SPI_CLOCKRATE:
{
if (*len != sizeof(cyg_uint32))
return -EINVAL;
else
{
cyg_uint32 cl_brate = *((cyg_uint32 *)buf);
cyg_uint32 old_cl_brate = at91_spi_dev->cl_brate;
at91_spi_dev->cl_brate = cl_brate;
if (!spi_at91_calc_scbr(at91_spi_dev))
{
at91_spi_dev->cl_brate = old_cl_brate;
spi_at91_calc_scbr(at91_spi_dev);
return -EINVAL;
}
}
}
break;
default:
return -EINVAL;
}
return ENOERR;
}
static void
spi_at91_transaction_begin(cyg_spi_device *dev)
{
cyg_spi_at91_device_t *at91_spi_dev = (cyg_spi_at91_device_t *) dev;
cyg_spi_at91_bus_t *spi_bus =
(cyg_spi_at91_bus_t *)at91_spi_dev->spi_device.spi_bus;
cyg_uint32 val;
if (!at91_spi_dev->init)
{
at91_spi_dev->init = true;
spi_at91_calc_scbr(at91_spi_dev);
}
// Configure SPI channel 0 - this is the only channel we
// use for all devices since we drive chip selects manually
val = AT91_SPI_CSR_BITS8;
if (1 == at91_spi_dev->cl_pol)
val |= AT91_SPI_CSR_CPOL;
if (1 == at91_spi_dev->cl_pha)
val |= AT91_SPI_CSR_NCPHA;
val |= AT91_SPI_CSR_SCBR(at91_spi_dev->cl_scbr);
HAL_WRITE_UINT32(spi_bus->base+AT91_SPI_CSR0, val);
// Enable SPI clock
HAL_WRITE_UINT32(AT91_PMC+AT91_PMC_PCER, 1<<spi_bus->interrupt_number);
// Enable the SPI controller
HAL_WRITE_UINT32(spi_bus->base+AT91_SPI_CR, AT91_SPI_CR_SPIEN);
/* As we are using this driver only in master mode with NPCS0
configured as GPIO instead of a peripheral pin, it is necessary
for the Mode Failure detection to be switched off as this will
cause havoc with the driver */
// Put SPI bus into master mode
if (1 == at91_spi_dev->cl_div32) {
val = AT91_SPI_MR_MSTR | AT91_SPI_MR_DIV32;
#ifdef AT91_SPI_MR_MODFDIS
val |= AT91_SPI_MR_MODFDIS;
#endif
HAL_WRITE_UINT32(spi_bus->base+AT91_SPI_MR, val);
} else {
val = AT91_SPI_MR_MSTR;
#ifdef AT91_SPI_MR_MODFDIS
val |= AT91_SPI_MR_MODFDIS;
#endif
HAL_WRITE_UINT32(spi_bus->base+AT91_SPI_MR, val);
}
}
static void
spi_at91_transaction_begin(cyg_spi_device *dev)
{
cyg_spi_at91_device_t *at91_spi_dev = (cyg_spi_at91_device_t *) dev;
cyg_uint32 val;
if (!at91_spi_dev->init)
{
at91_spi_dev->init = true;
spi_at91_calc_scbr(at91_spi_dev);
}
// Configure SPI channel 0 - this is the only channel we
// use for all devices since we drive chip selects manually
val = AT91_SPI_CSR_BITS8;
if (1 == at91_spi_dev->cl_pol)
val |= AT91_SPI_CSR_CPOL;
if (1 == at91_spi_dev->cl_pha)
val |= AT91_SPI_CSR_NCPHA;
val |= AT91_SPI_CSR_SCBR(at91_spi_dev->cl_scbr);
HAL_WRITE_UINT32(AT91_SPI+AT91_SPI_CSR0, val);
// Enable SPI clock
HAL_WRITE_UINT32(AT91_PMC+AT91_PMC_PCER, AT91_PMC_PCER_SPI);
// Enable the SPI controller
HAL_WRITE_UINT32(AT91_SPI+AT91_SPI_CR, AT91_SPI_CR_SPIEN);
// Put SPI bus into master mode
if (1 == at91_spi_dev->cl_div32)
HAL_WRITE_UINT32(AT91_SPI+AT91_SPI_MR, AT91_SPI_MR_MSTR |
AT91_SPI_MR_DIV32);
else
HAL_WRITE_UINT32(AT91_SPI+AT91_SPI_MR, AT91_SPI_MR_MSTR);
}
